JPH02153445A - System for generating request for nullifying cache memory - Google Patents

Abstract

PURPOSE:To simplify a serialization processing circuit by nullifying(resetting) a means to display the incompletion of sending of a cache nullifying request when detecting the fact that information (S0,...) for recording the completion time of sending of the cache nullifying request is read out from a cache nullifying request holding device. CONSTITUTION:When a serialization processing identifier S0 is read out from the cache nullifying request holding device 23, a corresponding serialization processing latch is reset. Therefore, it is possible to respond to the increment of the number of processors by adding only one processor identifier V to identify the processor which nullifies a cache memory on the only one cache nullifying request holding device 23 provided in the memory controller of a multiprocessor system. Also, a serialization processing is performed by providing the serialization processing latch corresponding to the processor issuing the serialization processing request, and adding the serialization processing identifier S to control(reset) the latch on the cache nullifying request holding device 23. In such a way, the fact that the cache nullifying request is sent to all processors can be confirmed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiments Effects of the Invention [Summary] Store-through cache storage In a multi-processor system having devices, the number of processors that share the main memory device is increasing regarding a method for creating a cache memory invalidation request that ensures consistency between the contents of the main memory device and the contents of the cache storage device possessed by each processor. (1) The main purpose of the multiprocessor system is to avoid an increase in the amount of hardware for cache memory invalidation in the storage control device and to simplify the serialization processing circuit. A storage control device that controls access to the storage device maintains a copy of the cache directory of each processor, and when update access to the main storage device is performed, the copy of the cache directory in the storage control device is indexed. However, if a matching line does not exist, no cache invalidation request is created; - if a failing line exists, a cache invalidation request is created, and after storing it in the cache invalidation request holding device, A cache invalidation request creation device that sends a cache invalidation request to a corresponding processor, the cache invalidation request holding device being provided with a cache invalidation address and a processor identifier (VO, ~) to which the cache invalidation request is to be sent. ), and when the cache invalidation request holding device is read, the processor identifier (
It is configured to send a cache invalidation request to the processor indicated by vO9~). (2) In the cache invalidation request holding device, means for storing information (SO3-) for recording the time point at which the transmission of the cache invalidation request is completed, and means for displaying that the transmission of the cache invalidation request is not yet completed. In preparation, when it is detected that information (SO3-) for recording the time point at which the transmission of the cache invalidation request is completed is read from the cache invalidation request holding device, an indication that the transmission of the cache invalidation request is not completed is displayed. configured to disable (reset) the means to do so.

[Industrial application field]

The present invention relates to a cache memory invalidation request creation method that ensures consistency between the contents of the main memory and the contents of the cache memory possessed by each processor in a multiprocessor system having a store-through type cache memory.

There are limits to the advancement of technology in recent computer systems, so there is a limit to the improvement in processing power of a single computer system.

On the other hand, user programs are becoming increasingly large and require high-speed processing.

Therefore, attempts are being made to speed up data processing by arranging processors (PH) in parallel to form a multiprocessor system and executing different programs simultaneously.

At this time, if each processor has a store-through type cache storage device, when a certain processor updates the contents of the main storage device shared by each processor, the contents of the cache storage device of each processor, In order to ensure consistency with the contents of the shared main memory, when the updated data block is held in the cache memory of another processor, it is necessary to invalidate the data block.

To perform this cache memory invalidation process, for example,
A storage control device that controls access to the main storage device,
A copy of the cache directory (tag part) of the cache storage device owned by each processor is provided.
When there is a store access from one processor to main memory, the other processor's copy of the cache directory is indexed and, if a matching line position exists, the other processor that got the matching output A cache invalidation request signal for the line data is sent to the line data.

Conventionally, a cache memory invalidation request creation mechanism equipped with such a function, such as a cache invalidation request holding device (CIRS), has been provided independently for each processor. As the number of processors in a multiprocessor system increases, the amount of resources required for the cache invalidation process becomes non-negligible, and the amount of time required to confirm that the cache invalidation request is sent to all processors increases. There is a problem that the so-called serialization processing circuit becomes complicated, and an effective method for creating a cache memory invalidation request has become necessary.

[Prior art and problems to be solved by the invention] FIG. 2 is a diagram explaining a conventional cache memory invalidation request creation method, in which (a) shows an example of a system configuration, and (b) shows a storage control system. 1 shows a configuration example of a conventional cache invalidation request generation device provided in a device.

As mentioned above, in a multiprocessor system (see figure (a)) in which each of a plurality of processors 30 is equipped with a store-through type cache storage device (hereinafter referred to as cache memory), each processor 30. In the storage control device 2 that controls access to the main storage device 1,
Copy the cache directory (tag part) of the cache memory of each processor 30)
(DIR-CO, CI.

-) 21 is provided.

First, in the figure (b), when the processor 30 having the store-through type cache memory registers (i.e. moves in) the contents of the main storage device l into the cache memory, it requests the storage control device 2 to that effect. issue.

The storage control device 2 transfers the requested contents of the main storage device 1 to the processor 30 that made the request, and also copies the cache directory as follows: DIR-CO, C1, -
・Update 21.

In this way, a copy of the cache directory of the corresponding processor 30 is stored in the DIR-Co, C1, . . . -21.

Each processor 0. 130. Or channel processor (
Processor 2) request from 31 to update the contents of main memory 1 (
When store requests (store requests) are submitted to boats RO to R2, priority is given to one of them by request priority (PR), and the request given the priority is
One goes to the main memory access section, and the other goes to the request address register (R1!Q ADDRBSS R1!GIS
Tf! R, hereinafter omitted) is set to 20, and the above DIR-C
O, C1,...21 are indexed.

The index results are compared by a line address comparison unit (COPMo, 1°-.) 22, and if they match, the request address is stored in a cache invalidation request holding device (invalidation request storage device) provided for the processor along with a valid pit (V). R5)
23a, and discarded if they do not match.

Each cache invalidation request holding device (CIRS) 23a
When the cache invalidation request is read out and the valid pit (V) is turned on, the corresponding processor 0.
A cache invalidation request is sent at 130.

In the above indexing operation, for example, when a store request is issued from the processor 030, DIR-C1, . . . 21 corresponding to a processor other than the processor 030 is indexed.

Therefore, in the conventional method, the number of DIR-CO, CI, . . .
23, the cache invalidation request holding device (CIR)
S) 23a, and as the number of processors 30 increases recently, the invalidation request holding device (
CIRS) There was a problem that the quantity of 23 could no longer be ignored.

Next, a conventional serialization processing method related to the cache invalidation processing will be explained.

The serialization process is performed by processors 0.1, 2, . -.-30 confirms the completion of a series of store accesses to the main memory l shared by each processor, when issuing the last store command, etc. of the series of store accesses, a serialization processing request (S ) to indicate that the invalidation process is in progress (referred to as the serialization process latch) 24, which is provided corresponding to the other processor 30.
a and resets each latch 24 at the time of completion of sending the invalidation processing request to the other processor 30, thereby recognizing the completion point of sending the invalidation processing request to the other processor 30. It is processing.

The completion point can be recognized, for example, when executing an instruction that branches to another program, that is, when executing a load program status word (load PSW) instruction, or when executing 9 interrupt processing, when the latch 24a during the serialization processing is executed. monitor,
This can be done by detecting that all of the latches 24a are off during the serialization process.

For this reason, when a store instruction having the serialization processing request (S) is executed, the serialization processing latch 24a for the processor 30 other than the processor 30 equipped with a cache memory is set, and the corresponding invalidation request holding device (CIRS)
The serialization processing request (S) is stored in the serialization processing request (S), and when reading of the information of the serialization processing request (S) is detected, the corresponding serialization processing latch 24a is reset.

Therefore, the serialization processing circuit (
The above cache invalidation request holding device (CIRS) 2
Write circuit for 3a, latch 24a during serialization process,
There is a problem in that the logical sum circuit 25, etc.) becomes more complex as the number of processors 30 increases.

In view of the above-mentioned conventional drawbacks, the present invention provides a cache memory disabling system that guarantees that the contents of the main storage device and the contents of the cache storage device of each processor will be matched in a multiprocessor system having a store-through type cache storage device. When creating a cache memory invalidation request, as the number of processors that share the main memory increases, the amount of hardware for cache memory invalidation within the storage control device increases, and It is an object of the present invention to provide a method for creating a cache memory invalidation request that can simplify a cache memory invalidation processing circuit.

[Means to solve the problem]

The above problem is solved by a cache memory invalidation request creation method configured as follows.

(1) Each of the plurality of processors that share the main memory is provided with a store-through type cache storage and a cache directory having a plurality of line entries corresponding to the line positions of the cache storage. and a storage control device that controls access to the main storage device,
A copy of the cache directory of each processor is maintained, and when an update access to the main memory is performed,
indexing a copy of the cache directory in the storage control device; if a matching line does not exist, do not create a cache invalidation request; if a matching line exists, create a cache invalidation request; A cache invalidation request generation device that stores a cache invalidation request in a cache invalidation request holding device and then sends it to a corresponding processor as a cache invalidation request, the cache invalidation request generating device storing a cache invalidation request address and a cache invalidation request in the cache invalidation request holding device. A processor identifier (vO1~) to which a request should be sent is stored, and when the cache invalidation request holding device is read, a cache invalidation request is sent to the processor indicated by the processor identifier (VO, ~). Configure.

(2) In the cache invalidation request holding device, information (SO
3-), and a means (latch) for displaying the incomplete sending of the cache invalidation request, and records the time point at which the sending of the cache invalidation request is completed from the cache invalidation request holding device. Information to do (SO3
-) is detected, the means (latch) for indicating that the sending of the cache invalidation request is not yet completed is disabled.

[Effect]

That is, according to the present invention, in a multiprocessor system equipped with a store-through type cache memory, a storage control device that controls access to the main storage device includes: a copy of the cache directory of each processor;
O, CI, -) is provided, and one cache invalidation request holding device is provided in the system without being provided corresponding to the processor, and its entry format is configured as follows, for example.

When a processor having a cache memory registers the contents of the main storage device in the cache memory, it issues a request to the storage control device to that effect, and the storage control device registers the requested contents of the main storage device in the cache memory. At the same time, a copy of the cache directory is copied to DIRCO, C.
I, -) is updated.

In this way, a copy of the cache directory DIRC
O, CI, . . . ) stores a copy of the cache directory of the corresponding processor.

Here, when main memory content update requests (i.e. store requests) from each processor are submitted to each port of the storage control device, one of them is given priority based on the request priority (PR). It will be done.

Requests given priority are set on one side to the main memory access unit and on the other to the request address register, and are sent to the DIRC as a copy of the cache directory.
O, CI, -), and the index results are compared in a line address comparison section, and if they match, the request address is used as the only cache invalidation of the present invention, along with the processor identifier (VO, Vl, -). The requests are stored in the above entry format in the request holding device, and if they do not match, the requests are discarded.

The processor identifier (VO, Vl, -) is processor 0.
For requests from other processors, e.g.
Processor 1.2. - Processor identifier V1. indicating that the request is for invalidation. ν2. -... is created and stored in the cache invalidation request holding device.

Therefore, when a valid entry is read from the cache invalidation request holding device, the processor identifier ν1. V
2. - determines the processor (-1, 2, -) to which the cache invalidation request should be sent.

In other words, if there are two processors, the processor identifiers (VO, V
According to l), the processor identifier is "Vl' when the request is received from processor 〇, and the processor identifier is °vO゛ when the request is issued to processor l by the request from processor 1. When a request is issued to processor O, or from a processor without cache memory, such as a channel processor (processor 2), the processor identifier is VO/Vl'' and the request is sent to processor O.
/1, respectively, to send an invalidation request.

In addition, in order to confirm that a certain cache invalidation request has been sent to all processors, a latch is provided for each processor to indicate that serialization processing is in progress, and while this serialization processing latch is set, is made to indicate that the target cache invalidation request exists in the cache invalidation request holding device.

Specifically, for example, assume that processor 0 issues the above-mentioned serialization request (S) when updating the contents of a specific address in the main storage device.

Copy DI of the above cache directory at the address
RCO, C1, --...), and if they match, the processor identifier "Vl', the invalidation address, and the serialization processing identifier (SO) of the present invention are stored in the cache invalidation request holding device. In addition to storing the above processor 0
Sets the serialization latch corresponding to .

Then, when the serialization process identifier (SO) is read from the cache invalidation request holding device, the corresponding latch during the serialization process is reset.

As mentioned above, the serialization processing request (S) is a control for a certain processor to perform a series of store accesses and to recognize the point at which it has completed sending invalidation processing requests to all other processors. Since it is information, the serialization processing request (S) is made at the last store instruction of the series of store accesses.
By controlling the latch during serialization processing corresponding to the processor that issued the request (processor O in the above example), a cache invalidation request can be sent to all processors as in the conventional method. be able to recognize that.

It functions as described above, by adding a processor identifier (V) that identifies the processor whose cache memory should be invalidated to the only cache invalidation request holding device provided in the storage control device of the multiprocessor system. , it is possible to cope with the increase in the number of processors. Also, for the serialization process t, a latch is provided during the serialization process corresponding to the processor that issued the serialization process request, and the latch is controlled by the cache invalidation request holding device? 11 (Reset)
By adding the serialization processing identifier (S), it is possible to confirm that the cache invalidation request has been sent to all processors.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) shows an entry format of a cache invalidation request holding device, and (b) shows an example of storage in the cache invalidation request holding device, (c) shows a configuration example of a cache memory invalidation request device, in which there is only one cache invalidation request holding device 23. A latch 24 during serialization provided corresponding to the processor is a necessary means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The cache memory invalidation request creation method of the present invention will be explained below with reference to FIG.

Even if the present invention is implemented, the registration operation and search operation for the old RCO, CI, ...) 21 in the cache directory will not change in particular, so they will be omitted, and here, the cache invalidation of the present invention will be omitted. The cache memory invalidation request creation method of the present invention will be described with a focus on storage and read operations for the request holding device 23.

First, the contents of the cache invalidation request holding device 23 are (
An example will be explained in which the entry format shown in the figure (a) is as shown in the figure (b).

The contents of the cache invalidation request holding device 23 are stored through the following accesses.

(1) 'The processor 030 is the main memory °ADDRf
! 5S-0" 21 was updated. As a result of indexing °DIR-C1' with that address, there was a match, so the address was stored in the cache invalidation request holding device 23 along with the processor identifier 'Vl' and written. Point ladder T
P'25 was incremented.

(2) ADDRESS where the processor 130 is the main storage device
-1゛ content has been updated. At that address, “DIR-C”
As a result of indexing O゛21, there is a match, so the address is stored in the cache invalidation request holding device 23 along with the processor identifier "vOo", and the address is stored in the write point ladder - TP.
Incremented 5.

(3) Processor 231 writes DDRES to main memory
The contents of S-2゛ have been updated. °DIR− at that address
C.O.

As a result of indexing C1°21, a match was found, so the address was stored in the cache invalidation request holding device 23 along with the processor identifier 'vo, vt', and the write pointer 'WTP' 25 was incremented.

(4) The processor 030 stores °ADDRES in the main memory.
Updated the contents of S-3' and requested serialization processing (S).

As a result of indexing the °DIR-CI' 21 with that address, a - match was found, so the serialization processing identifier (SO) was stored in the cache invalidation request holding device 23 along with the processor identifier 'Vl' and the address, and the write pointer "-TP'
Incremented 25.

Incidentally, at the time when the priority of this request is taken, the serialization processing latch 24 corresponding to the processor 030
is set.

The contents of the cache invalidation request holding device 23 stored as described above (see figure (b)) are sent to each processor 0.130 by the following operations.

(1) The contents of the read pointer “RDP” 26,
The contents of the write pointer "WTP" 25 are constantly compared by a comparator (COMP2) 27, and if they do not match, it is determined that a valid entry is stored in the cache invalidation request holding device 23, If a reception OK signal (not shown) is input from each processor 0.130 (a signal indicating that the invalidation request stack on the processor side can still be received), the comparator (COMP2) 27 The read operation is continued until a match signal is output.

(2) The contents of entry 0 are read and cache invalidation request sending register (CIRARo, 1) 28.2
9, that address is set. At this time, since the processor identifier "vlo" is set, processor 1
Cache invalidation request sending register (C
IRARI) 29 valid latch (n) 29a is set. After this, the read pointer "RDP' 26 is incremented.

Only the processor in which this valid latch (Vl) 29a is set (ie, processor 1) takes in the contents of the cache invalidation request sending register (CIRARI) 29. (The same applies hereinafter) (2) The contents of entry l are read and cache invalidation request sending register (CIRARo, 1) 28.2
9, that address is set. At this time, since the processor identifier "VO" is set, processor 03
Cache invalidation request sending register (CI
RARO) 2B valid latch (VO) 28a is set. After this, the read point ladder RDP' 26 is incremented.

(3) The contents of entry 2 are read and cache invalidation request sending register (CIRARo, 1) 28.2
9, that address is set. At this time, since the processor identifier "VO, V1' is set, the cache invalidation request corresponding to processor 0.130 is sent L/'; Star (CIRARO, l) 28.29 (
7) Set valid latch (vO9Vl) 28a and 29a. After this, the read point ladder RDP' 26 is incremented.

(4) The contents of entry 3 are read and sent to the cache invalidation request sending register ((, IRARo, 1) 28
．． The address is set in 29. At this time, since the processor identifier 'vt' is set, the valid latch (vl) 29a of the cache invalidation request sending register (CIRARI) 29 corresponding to the processor 130
Set.

Also, in this case, the serialization processing identifier 'so' of the present invention
is set, the serialization processing latch 24 corresponding to the processor 030 is reset. After this, the read pointer R26 is incremented.

Each processor 0. 130. The contents of the serialization processing latch 24 sent to the processor 231 are determined by the latch 24 in each processor depending on a specific instruction or event (for example, load ps-instruction 1 interrupt processing), as described above. By monitoring the content and detecting that it has been reset to 0, it is recognized that the cache invalidation request has been sent to all processors.

As described above, the present invention provides a cache memory invalidation request signal that ensures consistency between the contents of the main memory and the contents of the cache memory possessed by each processor in a multiprocessor system having a store-through type cache storage. To create the cache invalidation request, the conventional method accesses the copy of the cache directory (DIRCO, CI, --), and when a match is found, the cache invalidation request holding device corresponding to each processor However, when storing cache invalidation requests sequentially in one stack memory and distributing them to the corresponding processors when the stored cache invalidation requests are read, Store the processor identifier (VO, Vl, -> that specifies the processor. Also, in a store access that requests serialization processing, when the priority is obtained, the corresponding latch during serialization processing is set, and the Copy DI of the Pig cache directory
RCO, C1, -) and when a match is found, the above invalidation target processor identifier (VO, Vl, -
), a serialization processing identifier (SO, -) is also stored, and when the serialization processing identifier (SO, -.) is read, the corresponding serialization processing flag is reset. The feature is that by checking the latch with a specific instruction, it is possible to recognize that the cache invalidation request has been sent to all processors.

〔Effect of the invention〕

As described above in detail, the cache memory invalidation request creation method of the present invention is applicable to a multiprocessor system having a store-through type cache storage device.
In order to create a cache memory invalidation request that ensures consistency between the contents of the main memory and the contents of the cache memory possessed by each processor, (1) control access to the main memory of the multiprocessor system; A copy of the cache directory of each processor is held in the storage control device, and when an update access is made to the main storage device, the copy of the cache directory in the storage control device is indexed and a matching line does not exist. in case of,
Cache invalidation does not create a cache invalidation request, but if a matching line exists, creates a cache invalidation request, stores it in the cache invalidation request holding device, and then sends it to the corresponding processor as a cache invalidation request. a cache invalidation request generating device, the cache invalidation request holding device having a cache invalidation address;

Processor identifier (V
), and when the cache invalidation request holding device is read, a cache invalidation request is sent to the processor indicated by the processor identifier (V).

(2) Information (S) for recording the time point at which the sending of the cache invalidation request is completed in the cache invalidation request holding device.
and means for displaying whether the transmission of the cache invalidation request has not been completed, the information (S) for recording the time point at which the transmission of the cache invalidation request is completed from the cache invalidation request holding device. When it is detected that the cache invalidation request has been read, it disables (resets) the means for displaying that the sending of the cache invalidation request is not yet completed. By adding a processor identifier (V) for identifying a processor whose cache memory should be invalidated to the cache invalidation request holding device, it is possible to cope with an increase in the number of processors. Furthermore, in the serialization processing, a serialization processing latch is provided corresponding to the processor that has issued the serialization processing request, and the latch is controlled by the cache invalidation request holding device. 11 (reset) serialization processing identifier (S
) has the effect of making it possible to confirm that the cache invalidation request has been sent to all processors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating a conventional cache memory invalidation request creation method. It is. In the drawings, 1 is a main storage device, and 2 is a storage control device. 21 is a cache directory copy or cache directory copy (DIRCO, CI, -). 22 is a line address comparison section or a comparator (COMP
o. 1). 23a and 23 are cache invalidation request holding devices (CIl);
? S). 24a and 24 are latches during serialization processing. 25 is a write pointer (匈TP). 26 is a read pointer (RDP). 27 is a comparator (COMP2). 28.29 Cache invalidation request sending register (CIR)
ARo, 1). 28a and 29a are cache invalidation request sending/output register valid latches (vO1νl); hO is a processor〇, l. 31 is a processor~2. Or a channel processor. RO~R2 are boats. PR is request priority. Vθ, C1. ~ is a processor identifier. SO, ~ is a serialization processing identifier. are shown respectively. , (σ) is created to protect the next cache memory.

Claims (2)

[Claims] (1) Multiple processors (
30) is provided with a store-through type cache storage device and a cache directory having a plurality of line entries corresponding to the line positions of the cache storage device; A storage control device (2) that controls access holds a copy (21) of the cache directory of each processor (30), and the main storage device (1)
), the cache directory copy (21) in the storage control device (2) is indexed, and if a matching line does not exist, a cache invalidation request is not created and a matching line is accessed. A cache invalidation request creation device that creates a cache invalidation request if there is a line to do so, stores it in a cache invalidation request holding device (23), and then sends it to the corresponding processor (30) as a cache invalidation request. A cache invalidation address (230) and a processor identifier (V0, ~) (231) to which the cache invalidation request should be sent are stored in the cache invalidation request holding device (23); A cache memory invalidation request characterized in that when the invalidation request holding device (23) is read, a cache invalidation request is sent to the processor (30) indicated by the processor identifier (V0, ~) (231). Creation method. (2) In the cache invalidation request holding device (23),
comprising means for storing information (S0, ~) (232) for recording the time point at which sending of the cache invalidation request is completed; and means (24) for displaying the incomplete sending of the cache invalidation request; When it is detected that the information (S0, ~) (232) for recording the time point at which the transmission of the cache invalidation request is completed is read from the cache invalidation request holding device (23), the transmission of the cache invalidation request is not yet completed. 2. The cache memory invalidation request creation method according to claim 1, wherein the means (24) for displaying the cache memory invalidation request is invalidated.