JPH02151902A - Programmable controller - Google Patents

Abstract

PURPOSE:To attain the simulation of an optional I/O circuit with high timing accuracy without connecting an external wiring by arranging a memory for writing simulation data in a programmable controller(PC). CONSTITUTION:The PC is provided with an I/O memory 5, a simulation data memory 6 having a bit area corresponding to at least an input relay in the I/O memory 5 and a specification data memory 7 formed correspondingly to respective bits of the memory 6. The memory 7 is referred in each cycle time and the simulation data of a specified I/O circuit 8 stored in the memory 6 is substituted by its corresponding data stored in the memory 5. Consequently, the simulation of an optional I/O circuit can be attained with high timing accuracy without connecting an external wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a programmable controller (hereinafter referred to as a PC) that allows easy simulation.

(Summary of the Invention) This invention enables simulation with excellent timing accuracy without external wiring for arbitrary input/output circuits by providing a memory for writing simulation data inside a PC. be.

(Prior Art and its Problems) Conventionally, when attempting to perform simulations in a system using a PC, a method was used in which switches were connected to the input terminals of the PC and the switches were manually opened and closed.

However, this method requires connecting the same number of switches as the number of input terminals, making the wiring work cumbersome.

In addition, if you want to forcibly change a specific input during operation with the actual machine connected, it is necessary to add a dedicated switching circuit to the input/output circuit, and the switching operation must be performed manually. Therefore, it was not possible to obtain sufficiently satisfactory results in terms of the accuracy of switching timing.

(Purpose of the Invention) This invention was made to solve the above-mentioned problems.The purpose of this invention is to create a PC that eliminates the need for external wiring and that can perform simulations at will even while the actual machine is in operation. It is about providing.

(Structure and Effects of the Invention) In order to achieve the above object, the present invention includes an I/O memory in which input/output values for each input/output circuit are stored;
A programmable controller that cyclically transfers I/O data between O memory and input/output circuits and has a fresh processing function corresponds to the above I/O memory and stores simulation data for each input/output circuit. A simulation memory, a designated data memory that stores list data of input/output circuits whose I/O data is to be forcibly changed, and information stored in the I/O memory regarding the input/output circuits specified in this designated data memory. The present invention is characterized by comprising means for executing a process of replacing the corresponding I/O data with the corresponding simulation data in the simulation memory at each cycle time.

Since the present invention is configured as described above, the designated data memory is referred to at each cycle time, and the simulation button stored in the simulation memory for the designated input/output circuit is set to the corresponding I/O memory. Since it can be replaced with data, there is no need to add switches etc. to the input/output circuit on the hardware (it is possible to freely change and process the input/output values in any input/output circuit, and the simulation is much faster than before. becomes easier.

Furthermore, by rewriting the simulation memory and specified data memory using peripheral equipment, simulation can be performed at any timing.

(Explanation of Examples) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the hardware configuration of a PC to which the present invention is applied.

As is well known, this PC has a CPUI, system memory 2
, a user memory 3, a work memory 4, a/O memory 5, and the like.

An input/output relay corresponding to the input/output circuit 8, an auxiliary relay, and a timer/counter are assigned to the I/O memory 5 formed by a RAM.

The simulation data memory 6 is also made of RAM, and has a memory area that is at least equal to the input relay in the I/O memory 5.

The specified data memory 7 also consists of the same <RAM, and the memory 6
It is formed corresponding to each bit inside.

The peripheral device 9 is composed of a personal computer or the like, and receives various commands such as registration and recall of simulation data, and simulation mode setting and cancellation.

Figure 2 shows P executed cyclically by the CPUI.
3 is a flowchart showing the processing operation of C.

In the figure, first, a well-known watchdog timer reset or the like is performed as a common process (step 401).

Next, the setting of the simulation mode is determined, and if it is set, simulation processing is performed (Yes at step 402, step 403).

This simulation process is performed using the steps shown in Figure 3.
It will be done. That is, using the negative value of the simulation bit selection data stored in advance in the designated data memory 7, the I/O memory 5 is masked bit by bit. At the same time, the simulation data memory 6 is masked using the simulation bit selection data of the designated data memory 7. The logical OR of the data thus obtained is stored in the I/O memory 5 again. As a result, only the input/output circuit of the bit specified in the specified data memory 7 is
The value is changed to the value specified in the simulation data memory 6.

Next, as peripheral device service processing, service processing for peripheral devices such as personal computers and professional computers is performed (step 404). In particular, various commands related to the above-mentioned simulation processing are input and output in the format shown in FIG.
, the designated data memory 7 is updated. Similarly, a simulation mode setting command is also input.

Next, the setting of the program mode is determined, and if it is not set, a well-known user program execution process is performed, and the I/O memory 5 is rewritten based on the calculation result (step 405 affirmative, step 406).

Next, I/O refresh processing is performed, the input value of the input circuit 8 is transferred to the I/O memory 5, the value of the I/O memory 5 is transferred to the output circuit 8 (step 407), and one cycle of processing is completed. Return to top.

By executing the above processing cyclically, simulation data can be input from the outside via the peripheral device 9 even when the PC is actually operating, as well as when the actual machine is not connected. Furthermore, when the simulation mode is set, the actual input value is ignored in the designated input circuit, and simulation is performed based on the designated data.

FIG. 4 is a diagram showing an example of the format of various commands and responses exchanged between the PC main body and the peripheral device 9.

Figure a shows the format of a read command sent from the peripheral device 9 to the PC main body, with the header code $27 common to simulation commands at the beginning, and the sub-ladder code representing the processing type following.

The figure shows the format of the response sent from the PC to the peripheral device 9 in response to the command in figure a. After the common ladder code $27 at the beginning, the end code section is located, and then the end code is specified as a simulation target. The area type and channel number 1 in the I/O memory are displayed. The simulation bit selection data and simulation data for the designated channel are then displayed. Thereafter, if there is simulation data for other channels, they will be displayed continuously in the same way. Note that the simulation pit selection data and the simulation data are configured as shown in Figures g and 1, respectively.

FIG. The area type and channel number 3 in the I/O memory designated as the simulation target are displayed. Next, simulation pit selection data and simulation data of the channel to be registered are displayed.

FIG. d shows the format of the response sent from the PC to the peripheral device when the registration of simulation data is completed, and the end code is shown after the header code $27.

Figure e shows the format of a command that instructs to cancel registered simulation data.

Figure f shows the format of the response in the case of deregistration.

In addition, commands for setting and canceling the simulation mode, and responses to these commands are also used.

As is clear from the above embodiments, the present invention comprises an I/O memory 5, a simulation data memory 6 in which at least a bit area corresponding to an input relay is located in this I/O memory 5, and a bit area in this memory 6. By providing the specified data memory 7 formed corresponding to each channel, it becomes possible to forcibly change the manual input value for any part of the input circuit consisting of a large number of channels at any timing. In addition to depacking programs, abnormal situations that occur during actual system control operations can be dealt with accurately by changing input values with simple key operations using peripheral devices such as a personal computer.

Furthermore, in the above example, the case where input values are forcibly changed during the execution of the user program has been described, but it is also possible to forcefully change stored values in areas other than input values in the I/O memory 5. .

Note that if the output value is to be forcibly changed, the above simulation process may be executed after the user program execution process and before the refresh process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the hardware configuration of a PC to which the present invention is applied, FIG. 2 is a flowchart showing the operation, FIG. 3 is a diagram showing the I/O memory rewriting procedure, and FIG.
The figure shows the format of commands and responses related to simulation. 1... CPU 2... System memory 3... User memory 4... Work memory 5... I/O memory 6... ...Simulation data memory 7...
- Specified data memory 8... Input/output circuit 9... Peripheral equipment

Claims (1)

[Claims] 1. Refresh processing that includes an I/O memory in which input/output values for each input/output circuit are stored and cyclically transfers I/O data between the I/O memory and the input/output circuit. In a programmable controller having this function, a simulation memory that corresponds to the above I/O memory and stores simulation data for each input/output circuit, and a specification that stores list data of input/output circuits whose I/O data is forced to be changed. Regarding the data memory and the input/output circuit specified in this specified data memory, the process of replacing the corresponding I/O data stored in the I/O memory with the corresponding simulation data in the simulation memory is executed every cycle time. A programmable controller characterized by comprising: a means for doing so;