JPH02148904A - Delay line - Google Patents

Abstract

PURPOSE:To improve the delay time accuracy by operating a tap position extracting a signal in a delay line from a delay stage number signal and a delay quantity instruction signal and outputting a tap position signal to a 2nd selector. CONSTITUTION:A selector 6 extracts a signal from an optional position (input/ output terminal of each delay element) of a delay line 5 normally and keeps its output to either H or L during test. A delay number stage detection section 7 is operated synchronously with a clock 13, takes a change point of a test signal 3 passing through a delay element forming the delay line 5 by a test instruction signal 14 and what number of delay elements are passed through in a time of one period of the clock 13 is obtained and it is outputted as a delay stage number signal 10. Then an arithmetic section 8 is operated synchronously with the clock 13 and the output position of the selector 6 is decided by using the signal from the delay stage number detection section 7 and the delay command signal 12 given externally. Thus, the accuracy of delay time is taken sufficiently.

Description

[Detailed Description of the Invention] [Summary of the Invention] This invention relates to a delay line that can provide an accurate delay time even when integrated into an integrated circuit. The purpose is to provide a delay line configuration method that does not require manual adjustment and can ensure sufficient delay time accuracy.The purpose is to provide a method for configuring a delay line that does not require manual adjustment and can ensure sufficient delay time accuracy. a first selector that selects a signal, a delay line to which the output of the selector is applied and which is formed by connecting delay elements of n (Il) in series, and a second selector that can extract a signal from any tap of the delay line. a selector and a delay stage number signal that detects the position of a signal change point in the delay line when a test signal is applied and indicates the number of delay elements included between the change point positions at the beginning and end of a certain period; a delay stage number detection unit that outputs the delay stage number signal, the predetermined period, and the delay amount instruction signal, calculates a tap position from which the signal in the delay line should be extracted, and outputs the tap position signal to the second selector. The configuration includes an arithmetic unit that performs the following operations.

[Industrial application field]

TECHNICAL FIELD The present invention relates to a delay line that allows accurate delay time to be obtained even when it is integrated into an integrated circuit.

BACKGROUND OF THE INVENTION With the advancement of semiconductor technology in recent years, digitization of circuits has been actively carried out. This is due to digitalization,
This is because circuit stabilization, no adjustment, miniaturization, etc. can be easily realized. Furthermore, as digitalization progresses, circuits are becoming faster.

As the speed of this circuit increases, it becomes necessary to finely adjust the timing between each signal. Delay lines are often used for this timing adjustment, but most of the delay lines currently available are made based on conventional analog technology, making it difficult to eliminate adjustments and downsize, which are characteristics of digitalization. .

There are delay lines that utilize digital technology, such as delay lines that utilize the delay time of basic gates in digital circuits.
Currently, this is only used to delay signals, and there is no one yet that has the precision to withstand delicate timing adjustments. For this reason, a highly accurate delay line using digital technology is required.

[Conventional technology]

Conventional delay lines are based on analog technology using coils, capacitors, resistors, etc., or digital technology using several stages of basic gates connected in series. FIG. 5(a) shows an example of the former, and FIG. 5(C) shows an example of the latter. In Figure 5(a), B+ is the input cover sofa, R is the resistance, and C
is a capacitor, and B2 is an output buffer, as shown in the same figure (b).
As shown in the figure, when the input signal undergoes a step-like change, the input signal of the output buffer B2 rises slowly, and when this exceeds the dark value, the output of the output buffer rises in a step-like manner.

The time between each rising edge of the output signal is the delay time.

Further, in FIG. 5(C), G + -03 is a basic gate such as an AND, OR, or inverter, and there is a certain delay between the gate and the output, and when connected in multiple stages, a delay corresponding to the number of stages is obtained. In this example, there are three stages of gates in series, so Figure 5(d)
As shown in the figure, a delay time equivalent to three stages of basic gates is obtained between input and output.

56-10763 for those belonging to Figure 5 (C).
There is. In this method, each series connection point of n basic gates connected in series is used as a tap, and a tap is selected by a selection circuit.
The desired delay time specified by the selection signal is obtained.

[Problem to be solved by the invention]

The analog technology delay line shown in Figure 5(a) requires parts such as coils, capacitors, and resistors, and the IC of the circuit.
There are problems such as the need for adjusting the delay time (for example, adjusting the capacitance of a capacitor), which is not easy to do with an IC.

Furthermore, in the case of the digital technology shown in Fig. 5(C),
The accuracy of delay time cannot be guaranteed. For example, depending on the IC process, the difference between the minimum value and the maximum value of delay time may be five times. In a device that selects taps as in JP-A-56-10763, the delay time of each tap varies widely in each circuit, making it difficult to obtain a delay time that is a regular selection signal with high accuracy.

The present invention improves these points, eliminates the need for parts unsuitable for integrated circuits such as coils and capacitors, eliminates the need for manual adjustment of delay time, and provides a delay line that can ensure sufficient precision in delay time. The purpose is to provide a composition method.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. In the figure, 1 is an input signal, where the signal to be actually delayed is input. Reference numeral 2 denotes a test signal generating section, which operates in synchronization with the clock 13 and generates a signal for measuring the delay time of each delay element constituting the delay line 5 based on the test instruction signal 14. . Hereinafter, measuring the delay time for each delay element will be referred to as a test. Reference numeral 3 denotes a test signal generated from a test signal generator, which is a positive or negative pulse signal. Reference numeral 4 denotes a selector which is switched by a test instruction signal 14 and normally passes input signal 1, but during a test passes test signal 3 generated from a test signal generator. 5 is n delay elements 5. This is a delay line consisting of ~5n, and obtains a signal obtained by delaying the output of the selector 4 by an arbitrary time. 6 is a selector, which normally takes out a signal from any position on the delay line 5 (the input/output terminal of each delay element), and sets the output to either H (high) or L (low) during the test. It is something to keep. Reference numeral 7 denotes a delay stage number detection unit, which operates in synchronization with the clock 13, detects the change point of the test signal 3 passing through the delay elements constituting the delay line 5 according to the instruction of the test instruction signal 14, and detects the change point of the test signal 3 passing through the delay elements constituting the delay line 5.
Find how many delay elements pass through one cycle of
This is output as a delay stage number signal 10. 8
is an arithmetic unit which operates in synchronization with the clock 13 and determines the output position of the selector 6 based on the signal from the delay stage number detection unit 7 and the delay amount instruction signal 12 given from the outside. Reference numeral 9 denotes an output signal, which is normally a signal obtained by delaying the input signal l by the amount indicated by the delay amount instruction signal 12.

The delay stage number signal 10 is a signal indicating the number of delay elements forming the delay line 5 for one period of the clock 13.

The tap position signal 11 is obtained by the calculation unit 8 and is a signal that indicates the output position of the selector 6. The delay amount instruction signal 12 is a signal that indicates the delay time between the input signal 1 and the output signal 9.

The clock 13 is a signal that determines the operation timing of the test signal generating section 2, the delay stage number detecting section 7, and the calculating section 8 during the test period. The test instruction signal 14 measures the delay time of each delay element constituting the delay line 5 according to the instruction of this signal.

[Effect]

The operation will be explained using the timing chart of FIG.

This FIG. 2 shows the state of the signals at each part when a negative pulse is added to the input signal 1.

In the figure, 10 to t gel indicate each delay element 51, 5□, . . . 5. , shows the signals input to and output from these. If the value of the tap position signal 11 output from the calculation section 8 is 5, the signal i5 is delayed by the delay time of the selector 6 and is output as the output signal 9 (waveform ■). Similarly, if the value of the tap position signal 11 is k, the output signal 9 will have a waveform like ■.

In this way, the selector 6 operated by the tap position signal 11
By changing the signal extraction position from the delay line 5, an arbitrary delay time can be obtained.

Next is the measurement of the delay time, this is the test instruction signal 1
This is done according to the instructions in step 4. The waveforms of each part at this time are shown in FIG.

In accordance with the instruction of the test instruction signal 14, the test signal generator 2 generates the test signal 3 in synchronization with the clock 13, and selector 4
passes this test signal 3 through a delay line 5. Two points are the rising or falling positions of the signal passing through this delay line 5.
The delay stage number detection section 7 detects, digitizes this position, and outputs the difference as a delay stage number signal 10. In Figure 3, two falling points are detected, and when clock 13 enters (
In a), when i falls (ii is H, i is set, i falls) and the next clock 13 enters (
In b), i3a falls, so the difference is 38-5=33, and this 33 is output as the delay stage number signal 10.

The calculation unit 8 calculates the delay time per delay element by calculations such as division using the delay stage number signal 10 and the time of one cycle of the clock 13, and achieves the delay time commensurate with the value of the delay amount instruction signal 12. The number of delay elements required for this is determined and outputted as the tap position signal 11.

In this way, the delay time per delay element is actually measured, and the tap position of the selector 6 with respect to the delay amount instruction signal 12 is determined according to the actual measurement result, and the selector 6 is operated by the signal 11 instructing the tap position to output the output signal. 9, when integrated into an IC, it is possible to fully cope with changes in delay time due to variations in characteristics of each IC due to IC manufacturing, and changes in delay time due to changes in the operating environment, etc.
The maximum error in the delay time at this time can be suppressed to the delay time per one delay element.

〔Example〕

FIG. 4 is a configuration diagram of an embodiment of the present invention. In the figure, the same components as those shown in FIG. 1 are indicated by the same numbers. For example, 1 is an input signal, which is the signal to be delayed using this delay line. In this example, the test signal generating section 2 is constituted by a counter, operates in synchronization with the clock 13 and at the falling edge of the test instruction signal 14, and outputs a negative pulse as the test signal 3. The test signal 3 is a negative pulse generated by the test signal generator 3 based on the falling edge of the test instruction signal 14. The waveforms of these signals 14.3, etc. are as shown in FIG. The selector 4 outputs the input signal 1 during the period when the test instruction signal 14 is H, and outputs the test signal 3 during the period when the test instruction signal 14 is L.

5 and 51 have the same shape as the selector 4, and together constitute a delay line 5, and the delay time of the entire delay line is set to be longer than the maximum value of the target delay time. The selector 6 is a selector having the same shape as the selector 4, and selects a signal of an arbitrary tap among the taps of the delay line 5 (n+1) and sets it as an output signal 9. The selector 6 consists of a selector element group 6a and a decoder 6b, and has a SL(,,.

1□, . . . are subscripts to distinguish one from the other, and these are omitted as appropriate) are the selector elements that perform 2-1 selection and are connected in a tree shape as shown. The decoder 6b is
The signal 11 from the arithmetic unit 8 is decoded and the selector element S
It generates an L switching signal, and stops generating this switching signal while the test instruction signal 14 is L.

The delay stage number detection unit 7 includes a register group 7a, an AND gate group 7b, an encoder 7c, latches 7d and 7f, and an adder 7e.
Equipped with The register group 7a includes (n+1) registers R.
0 to R1, and these registers hold the states of the signals of (n+1) taps of the delay line 5 in synchronization with the clock 13. Since these are flip-flops, the outputs are Q and Q (denoted by XQ), and each element A 1 , A z , . The output Q of the register of the relevant stage is inputted and the logical product is taken. The logical product output is H only when XQ=Q=H, and is L otherwise, so the logical product group A 1
1 A Z l...The output of An is 000100
0..., and the cough "1" part is delay line 5.
The above O-1 change point is shown. The n-input encoder 7c is
The output of this AND group converts the position of 1 into a numerical value, and the latch 7d holds the value of the output of the encoder 7c while the test instruction signal 14 is L. Register R0~R0
For example, the delay line tap output is captured by the first clock and the second clock, and the logical product group 7b and therefore the encoder 7
c produces the above output each time, and the first encoder 7c
The second output is taken into the latch O of the latch 7d, and the second output is taken into the same latch l. The subtracter 7e selects these latches 0
．． The difference of 1 is obtained and the latch 7f captures this difference. latch 7
f holds the value of the output of the subtracter 7e and outputs it as the delay stage number signal 10. In the example in Figure 3, the latch O
The value taken in is 5, the value taken in latch 1 is 38, so the output of subtracter 7e is 33, and the value taken in latch 7f is 38.
captures this.

The calculation unit 8 includes dividers 8a and 8b that perform division of A+B.
and a subtracter 8C. The divider 8a divides the length T of one period of the clock 13 by the delay stage number signal 10 to obtain the delay time for each of the delay elements 51 to 5o. Further, the divider 8b divides the delay amount instruction signal 12 by the output of the divider 8a, and divides the delay amount instruction signal 12 by the delay element 5.5 necessary to achieve the delay time of the delay amount instruction signal 12. Find the number of ~57. The subtracter 8c corrects the difference in delay time caused by the selectors 4 and 6, and subtracts the offset signal 8d from the output of the divider 8b. The offset signal 8d has a delay time between the selector 4 and the selector 6 that is determined by the delay elements 51 to 5. This is a signal indicating how many pieces of data corresponds to this number. The output signal 9 is a signal obtained by delaying the input signal 1 by a desired time, and the delay stage number signal 10 is a signal obtained by delaying the input signal 1 by a desired time, and the delay stage number signal 10 is a signal obtained by delaying the input signal 1 by a desired time. This is a signal representing the number of ~5o. Further, the tap position signal 11 is a signal representing the output position of the delay line 5 to achieve the delay time instructed by the delay amount instruction signal 12.
2 is a signal for instructing the delay time from input signal 1 to output signal 9. In addition, the clock 13 is connected to the delay element 5I.
The test instruction signal 14 determines the operation timing when measuring the delay time per delay element 5a by setting this signal to L. is started.

Next, the delay element 5. shown in FIG. 4, which is particularly a feature of the present invention. ~
The delay time measuring operation of No. 57 will be explained in its entirety with reference to the timing chart of FIG.

Delay element5. -57 delay time measurement is performed using test instruction signal 1
It starts from the falling edge of 4. Further, all of the following operations are performed in synchronization with the clock 13.

At the falling edge of the test instruction signal 14, the test signal generator 2 generates a test signal 3, which passes through the delay line 5. The state of signal propagation in the delay line 5 is held by the register group 7a. In the timing chart of FIG. 3, the signal value immediately before the dotted line indicating the clock position is held. This register group 7
Holds the signal value held by a. The contents of the signals held by this register group 7a and the output values of the AND group 7b connected immediately after this register group 7a are as shown in Table 1.

The encoder 7c converts the portion where the output of the logical product group 7b is 1 into a number, and this number is held by 0.1 of the latch 7d. The subtracter 7e takes the difference between the outputs of the two latches 0.1 and outputs it as a delay stage number signal 10. In this example, latch O
5 is held in latch 1, 38 is held in latch 1, and delay stage number signal 1 is held.
The value of 0 is 33. The divider 8a receives the delay stage number signal 10.
Divide the length T of one cycle of the clock 13 by the value. Here, if one period of the clock 13 is 100ns, the divider 8
The output of a is 100÷33=3.3 ns, which represents the delay time per delay element. The divider 8b divides the delay amount instruction signal 12 by the output of the divider 8a to find the number of required delay elements 5a. Here, if the value of the delay amount instruction signal 12 is 60 ns, the output of the divider 8b is 60 ns.
+3.3=18, and it can be seen that 18 delay elements are required. The subtracter 7c corrects the deviation caused by the delay time of the selector 4.6 from the output of the divider 8b. Here, delay element 5. ~5. ．． Since ゛ is isomorphic to selector 4,
The selector 4 has a delay time equivalent to one delay element, and the selector element SL has the same shape as the selector 4. If the hierarchy of the selector element SL is 6, then the selector 6 has delay elements 5. ~5. ．． It will have a delay time of 6 times,
The value of the offset signal 8d is 1+6=7. From this, the value of the tap position signal 11 becomes 1B-7=11. Through the above operations, the output position of the delay line 5 to obtain the delay time of 60 ns instructed by the delay amount instruction signal 12 is determined.

Note that the polarity of the signals of each part is not limited to the polarity of the above-mentioned embodiment, and H and L may be reversed. As shown in FIG. 3, counter 2 may be of any type as long as it produces an output that changes from H level to L level (or vice versa), but one flip-flop is required to ensure sufficient H level and L level periods. 1/4 of that as a 2-3 bit counter. The 1/8 frequency divided output is used.

As explained above, according to the present invention, it is possible to digitize the entire circuit, making it extremely easy to integrate it into an IC, and by adding a delay stage number detection circuit, each circuit constituting the delay line can be digitized. Even if the delay time of the delay element changes, it becomes possible to obtain a stable and highly accurate delay time, which greatly contributes to improving the performance and downsizing of the delay line.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a timing chart for explaining delay operation, FIG. 3 is a timing chart for explaining test operation, and FIG. 4 is a block diagram showing an embodiment of the present invention. FIG. 5 is an explanatory diagram of a conventional example. In Figure 1, 4 is the first selector, 5 is the delay line, 5, ~5
．． ．． 6 is a delay element, 6 is a second selector, 7 is a delay stage number detector, and 8 is an arithmetic unit. [Effect of the invention] tel - Explanatory diagram of the conventional example Fig. 5

Claims (1)

[Claims] 1. The first selector (
4), a delay line (5) to which the output of the selector is applied and formed by connecting n delay elements in series, and a second selector (6) capable of extracting a signal from any tap of the delay line. ), and a delay stage number signal that detects the position of the change point of the signal in the delay line when the test signal is applied and indicates the number of delay elements included between the change point positions at the beginning and end of a certain period. a delay stage number detection unit (7) that outputs the delay stage number signal, the predetermined period, and the delay amount instruction signal, calculates a tap position from which a signal in the delay line should be extracted, and outputs the tap position signal to a second delay stage number detection unit (7); A delay line characterized by comprising an arithmetic unit (8) for outputting to a selector.