JPH02148199U - - Google Patents
Info
- Publication number
- JPH02148199U JPH02148199U JP5739789U JP5739789U JPH02148199U JP H02148199 U JPH02148199 U JP H02148199U JP 5739789 U JP5739789 U JP 5739789U JP 5739789 U JP5739789 U JP 5739789U JP H02148199 U JPH02148199 U JP H02148199U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- control
- control program
- circuit
- speech synthesis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000003786 synthesis reaction Methods 0.000 claims description 11
- 230000002194 synthesizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例による音声合成装置
のシステムブロツク図、第２図は同外部メモリ内
の各データ類の格納例、第３図は同外部メモリ内
の制御プログラムのフローチヤートの一部、第４
図は同タイムチヤート、第５図は従来の音声合成
装置のシステムブロツク図である。
１……制御回路、２……ＣＰＵ、３……外部メ
モリ、４……音声合成回路、５……主メモリ、７
……データバスバツフア、８……アドレスバスバ
ツフア、９……メモリ制御バスバツフア、１６…
…音声合成終了信号、３１……音声データヘツダ
、３２……音声データ、３３……制御プログラム
データ。
Fig. 1 is a system block diagram of a speech synthesizer according to an embodiment of the present invention, Fig. 2 is an example of storage of various data types in the external memory, and Fig. 3 is a flowchart of a control program in the external memory. Part, 4th
The figure is a time chart of the same, and FIG. 5 is a system block diagram of a conventional speech synthesizer. 1...Control circuit, 2...CPU, 3...External memory, 4...Speech synthesis circuit, 5...Main memory, 7
...Data bus buffer, 8...Address bus buffer, 9...Memory control bus buffer, 16...
...Speech synthesis end signal, 31...Sound data header, 32...Sound data, 33...Control program data.
Claims (1)
を実行するＣＰＵ２を含んだ制御回路１と、音声
合成用の複数の音声合成に係わる音声データヘツ
ダ３１、及び音声データ３２とＣＰＵ２を制御す
る制御プログラムデータ３３を格納し、かつ、前
記制御回路１にデータバスバツフア７、アドレス
バスバツフア８及びメモリ制御バスバツフア９を
介して接続されている外部メモリ３と、制御回路
１からの制御によつて音声合成を開始するととも
に音声合成中は外部メモリ３とのみアクセスする
音声合成回路４と、音声合成時には前記制御プロ
グラムデータ３３及びこの制御プログラムデータ
３３内の一部が転送されるとともに制御回路１の
みがアクセスし、かつ、制御回路１からアドレス
デコーダ６を介して制御回路１に接続された主メ
モリ５と、制御回路１と音声合成回路４との双方
から前記の音声データヘツダ３１、音声データ３
２及び制御プログラムデータ３３を読出すことの
出来る音声合成装置において、音声合成中は制御
回路１から外部メモリ３へのアクセスを禁止する
とともに主メモリ５へ転送された制御プログラム
データ３３及び制御プログラムデータ３３内の一
部を制御回路１からアクセスし、音声合成回路４
からの音声合成終了信号１６によつて制御回路１
から外部メモリ３へのアクセスを再開することを
特徴とする音声合成装置。 A control circuit 1 including a CPU 2 that executes a control program for generating a target voice, an audio data header 31 for synthesizing a plurality of voices, and control program data 33 for controlling the audio data 32 and the CPU 2. and an external memory 3 connected to the control circuit 1 via a data bus buffer 7, an address bus buffer 8, and a memory control bus buffer 9, and performs voice synthesis under control from the control circuit 1. The speech synthesis circuit 4 accesses only the external memory 3 when the speech synthesis starts, and the control program data 33 and a part of the control program data 33 are transferred and accessed only by the control circuit 1 during speech synthesis. , and the main memory 5 connected from the control circuit 1 to the control circuit 1 via the address decoder 6, and the audio data header 31 and the audio data 3 from both the control circuit 1 and the audio synthesis circuit 4.
2 and control program data 33, access from the control circuit 1 to the external memory 3 is prohibited during speech synthesis, and the control program data 33 and control program data transferred to the main memory 5 are prohibited. 33 is accessed from the control circuit 1, and the speech synthesis circuit 4
The control circuit 1 receives the voice synthesis end signal 16 from the
A speech synthesis device characterized in that access to an external memory 3 is resumed from the start.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5739789U JPH02148199U (en) | 1989-05-18 | 1989-05-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5739789U JPH02148199U (en) | 1989-05-18 | 1989-05-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02148199U true JPH02148199U (en) | 1990-12-17 |
Family
ID=31582065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5739789U Pending JPH02148199U (en) | 1989-05-18 | 1989-05-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02148199U (en) |
-
1989
- 1989-05-18 JP JP5739789U patent/JPH02148199U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3384290B2 (en) | Sound source device | |
| US5753841A (en) | PC audio system with wavetable cache | |
| US5847304A (en) | PC audio system with frequency compensated wavetable data | |
| JPH02148199U (en) | ||
| JPH02136298U (en) | ||
| KR100384685B1 (en) | PC audio system with frequency-compensated wave table data | |
| JP2527393Y2 (en) | Speech synthesizer | |
| JPH0540560Y2 (en) | ||
| JPH0375498U (en) | ||
| JPH0356983U (en) | ||
| JPS59164098U (en) | Speech synthesis control device | |
| JPH0241300U (en) | ||
| JP2000122668A (en) | Digtal sound data processor, and computor system | |
| JPS6294498U (en) | ||
| JPH03110497U (en) | ||
| JPS60159796A (en) | Voice data access system | |
| JPH01162164U (en) | ||
| JPH0341349U (en) | ||
| JPS6257297U (en) | ||
| JPH01120251U (en) | ||
| JPS6314194U (en) | ||
| JPS5896498U (en) | Grain dryer with audio alarm | |
| JPH0458761U (en) | ||
| JPH03110499U (en) | ||
| JPH0165571U (en) |