JPH03110499U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is an external view of a system of a speech synthesis device showing an embodiment of the present invention, Fig. 2 is a system block diagram of the speech and sound production device, Fig. 3 is a time chart thereof, and Fig. 4 is its gate. A circuit diagram is shown. 1a...CPU, 4...Storage means (flexible disk), 10...Speech synthesis element, 11...
Gate circuit, 12...Writable memory (memory RAM), 16...Speech synthesis detection signal.

Claims (1)

[Claims for Utility Model Registration] 1. After reading the speech or onomatopoeic data from the data storage means 4 storing speech or onomatopoeic data in units of words, phrases, or sentences, and storing the data in the read/write memory 12, read/write the read/write memory. In a speech synthesis device that applies speech synthesis that generates speech or onomatopoeic signals controlled by a CPU 1a by a speech synthesis means using a speech synthesis element 10 that reads data from a CPU 1a and performs speech synthesis, the speech synthesis device The device is characterized in that the CPU 1a is prevented from accessing the read/write memory 12 when the element 10 is reading the audio data stored in the read/write memory 12 and outputting voice synthesis. Speech synthesizer. 2. The speech synthesis element 10 outputs a speech synthesis detection signal 16 during speech synthesis output, and using this speech synthesis detection signal 16, a gate circuit 11 is provided between the CPU 1a and the read/write memory 12,
2. The speech synthesis device according to claim 1, wherein transmission and reception of control signals and data is not possible.