JPH02146198A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To confirm the held voltage of all the memory cells and to obtain a high quality semiconductor memory by variably controlling read out control potential from the external terminal of the semiconductor memory applied prescribed connection with the respective cells. CONSTITUTION:A memory cell composed of transistors QR1 and QR2 of the semiconductor memory composed of a memory cell array and a read/write circuit as partially shown in a figure is selected, and write data are inverted, and signal terminals WDT and WDF are respectively set to high potential and low potential when this cell is under a holding state in which the cell never outputs information to a bit line. Further, when the potential of an external terminal VHC is gradually lowered, and the potential of a terminal RC, for which potential change corresponds to that of the VHC in the ratio of 1:1, is lowered accompanying the lowering of the potential of the VHC, the potential of the RC becomes lower than that of the WDT, QRT1 and the QWT1 are respectively switched to an ON state, and the holding state never changes. When the potential is further lowered, the cell is inverted at a point where the potential of the RC becomes lower than the base potential of a QH1. Here, the potential variation of the VHC is expressed as the held voltage in the cell. A data inverted state can be also grasped from the output waveform of a sense amplifier. The same processing is also executed for the other cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory having a test function.

[Conventional technology] A conventional semiconductor memory will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing the periphery of a memory cell portion of a conventional semiconductor memory. The memory cell 300 has multi-emitter transistors QHI, QRI, Q)12.
It has a flip-flop configuration in which the collector and base of QR2 are cross-coupled with each other, and the collector of each transistor is connected to the word line WTH through resistive loads RF and RT, the emitter on the transistor QHI side is connected to the holding line WBH, and the emitter on the other QRI side is connected to the holding line WBH. The emitter is connected to the bit line DF, the emitter on the Q Hl side of the transistor is connected to the holding line WBH, and the emitter on the QR2 side is connected to the bit line DT. Memory cell U12. U21. The same configuration applies to U22, including word lines ~VTH, WTL, holding lines WBH, WBL,
Bit lines DF, DT, DF2. Connected to DT2. The emitter of the write transistor QWI and the emitter of the read transistor QRFI are connected to the bit line DF.
The emitter of the write transistor QWT1 and the emitter of the read transistor QRTI are connected to the bit line DT. Bit line DF2. Similarly, write transistor QWF2. QWT2 and read transistor QRF2. The emitter of QRT2 is connected. The collectors of read transistors QRFI and QRF2 are commonly connected to sense resistor R5F and input to sense amplifier SA, and the collectors of read transistors QRT1 and QRT2 are commonly connected to sense resistor RST and input to sense amplifier SA. . Write transistors QWF1 and QW
The base of F2 is commonly connected to the write data terminal WDF, the bases of transistors QWTI and QWT2 are commonly connected to the write data terminal ~VDT, and the read transistor QR
FI, QRF2. The bases of QRTI and QRT2 are commonly connected to the emitter output of the emitter follower circuit of the transistor QRC1, and the base of the transistor QRC1 is connected to the read control terminal RCI. The bit lines DF and DF2 have transistors QDFI and QDF2 as common emitters, and the bit lines DT and DT2 have transistors QDTI and QDT2 as common emitters, so that the base input terminal B1 of transistors QDF1 and QDTl and the base input terminal of transistors QDF2 and QDT2 A bit line selection signal applied to the base input terminal B2 of the terminal selects the read current rD1. ID2 can be passed through the bit line. Word lines WTH and WTL are connected to word line selection terminals WDH and WDL via word driver transistors QWDI and QWD2, respectively. The memory cell transistor has a flip-flop configuration, and one of the pair of multi-emitter transistors is in a conductive state,
The other is in the cut-off state and remains stable due to the difference in potential effects occurring between the loads RF and RT. Here, the operating state of the memory cell will be explained with reference to the potential diagram of FIG. For the sake of explanation, a memory cell consisting of transistors QRI and QR2 will be selected here. For this purpose, the word line selection signal WDH and bit line selection signal Bl are set to high potential, and the word line selection signal WDL and bit line selection signal B2 are set to low potential.

Here, explanation will be given assuming that the transistor QF(2, QR2) on the side having a multi-emitter has information indicating that it is in a conductive state.

When the memory cell is in the read state (4-a), the read control signal RC is at a potential between the base and collector potentials VB and VC of the transistor QR2 of the selected memory cell, and the write data WDT , WDF signal input is at a potential sufficiently lower than the collector potential VC of the memory cell, and in this potential relationship, the transistor QR2 is conductive, and the read current ID2 flows through the transistor QDTI.

Transistors QRT1 and QWT1 are in the cutoff state. On the other hand, transistors QRI and QWFl are in a cutoff state, and the read current flows through sense resistor RSF and transistor QR.
Information of the flow memory cell is read out via FI and QDF1.

In the write state (4-b) of the memory cell, the read control signal RC is made sufficiently lower than the collector potential VC of the memory cell, and one input of the write data signal ~VDT is made higher than the base potential VB of the memory cell. By setting the potential,
Memory cell transistor QR that was in a conductive state until now
2 is cut off, and the collector potential and the base potential VC of the transistor QRI are set to the other write data input WDF.
Since the voltage is sufficiently higher than that, the transistor QRI becomes conductive and the write operation is completed.

In the holding state (4-c), the word line WT)! Potential and memory cell base, collector potential VB.

VC is at a lower potential than read control signal RC and write signals WDT, WDF, and memory cell transistors QRI, QR
2 is in the cut-off state, and the memory cell information is transferred to the transistor Q.
It is maintained by a holding current by current source IH1 flowing through H2. Here, the holding voltage VH, which is the collector-base voltage of the transistor QR2 in the holding state, is VH=
IH1 (RT-RF/hFE), current amplification factor hF
If E is sufficiently large, VHKIHIRT occurs, and at this time, the base node VB is approximately equal to the word line potential WTH. If the holding voltage VH of the memory cell is small, the information retention margin will be small and the memory cell will not operate stably, and the error ratio will be high for alpha ray soft errors, and if the voltage VH is too large, the readout AC, which increases the write time due to the address access delay and the time required for cell inversion during writing.
The key point in design is to set the memory cell holding voltage VH to an appropriate value to avoid deterioration of characteristics, and a memory that can confirm this is required.

[Problems to be Solved by the Invention] In the conventional semiconductor memory described above, there is no means for confirming the holding voltage VH of a memory cell from an external terminal, and the only way is to estimate the holding voltage from the characteristics of each transistor and resistor. Furthermore, in semiconductor manufacturing, it is difficult to maintain uniform characteristics of all memory cells at all times, and variations in memory cell characteristics or defective characteristics unique to a single memory cell may occur due to crystal defects, etc. This is directly linked to memory cell malfunction. In such cases, it is necessary to inspect all cells one by one, and although it is possible to remove defects to some extent by sorting through operation tests, it is difficult to confirm the degree of variation in holding voltage between memory cells. The drawback was that there was a limit to how much quality could be improved through sorting.

[Differences between the Invention and the Prior Art] The present invention differs from the conventional memory cells described above in that it is possible to check the holding voltage VH of all memory cells by variably controlling the read control potential from an external terminal.

[Means for Solving the Problems] The gist of the present invention is to provide a semiconductor memory having a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, each memory cell having a first . a first multi-emitter transistor having a second emitter; a second multi-emitter transistor having a third and fourth emitter;
The first emitter and the third emitter of the multi-emitter transistor are connected to the first holding line, the second emitter is connected to the first bit line, and the fourth emitter is connected to the second bit line, respectively. the collector of the first transistor is alternately connected to the base of the second transistor and the collector of the second transistor is connected to the base of the first transistor;
The collector of the first transistor is connected to the first word line through the first load means, the collector of the second transistor is connected to the first word line through the second load means, and the collector of the second transistor is connected to the first word line through the second load means. 1. The second bit line can selectively conduct current, and the first bit line is connected to the emitter of the third transistor for writing and the emitter of the fourth transistor for reading, and the second bit line is connected to the emitter of the third transistor for writing and the emitter of the fourth transistor for reading. The emitter of a fifth transistor for writing and the emitter of a sixth transistor for reading are respectively connected to the line, write data output terminals are connected to the bases of the third and fifth transistors, and the fourth
．． The collectors of the fifth transistors are each connected to the output of the read data output circuit; The bases of the fifth transistors are connected to each other, and the emitters of the sixth transistor whose base input is the readout control signal and the seventh transistor whose base input is the holding voltage control signal are connected in common. The common emitter of the switch is connected to the fourth. It is connected to the common base of the fifth transistor.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a memory cell array and part of a read/write control circuit constituting an embodiment of a semiconductor memory according to the present invention. Each memory cell U11, U12 . U21
．． U22 is the transistor QRI, QR2 as in the conventional example.
, QHI, QH2 and load resistors RF, RT, word line 1vVTH1 holding line WBH, bit line DF
, DT, and a holding current in the memory cell holding state is supplied from a current source IHI to the holding line WBH.
A read current is applied to the bit line DF or DT when selecting a bit.
D1 and ID2 flow. The word line WTH is driven by word drivers Q to VDI, and its control potential WDH is at a high potential when the word line is selected. Bit line DF, DT
Each write data transistor QWF 1.
Q”vVT 1, read transistor QRFI, QRT
I is connected to read transistors QRFI and QRTI.
The bases of the transistors are commonly connected to a common emitter terminal RC of a current changeover switch consisting of a readout control transistor QRCI and a holding voltage detection transistor QRC2.

A read control signal is applied to the base of the read control transistor QRC1, and a holding voltage detection transistor QRC2 is applied to the base of the read control transistor QRC1.
The base of is connected to an external control terminal VHC via a resistor RCH, and is also connected to the anode of a diode F'DHC, which has a common cathode with a diode DRC and constitutes a power switch. Next, the operation of this circuit will be explained.

In a normal memory operation state, the holding voltage detection external terminal VHC is kept at a sufficiently low potential with respect to the terminals VRH and RCI, usually clamped to the lowest potential. In this state, the holding voltage detection transistor QRC2 is in a cutoff state, and the read control transistor QRC1 is in a conduction state.
The memory operation is exactly the same as in the conventional example. For the sake of explanation, terminals VDH and BI are at high potential, a memory cell consisting of transistors QRI and QR2 is selected, and when this memory cell is in a write state, write data terminal WDF is at high potential and WDT is at high potential. Assume that a low potential data signal is applied. The potential relationship at this time is shown in Figure 2 (2-
Shown in a).

Here, the memory cell transistor QRI is in a cut-off state, and the transistor QR2 is in a conductive state, through which current ID2 flows. In addition, read transistors QRFI and QRTI
(7) Base potential RC! , f! In the write state, the write transistor QWFI is at a sufficiently lower potential than the write data signal WDF and the memory cell Vc and VB terminals, and in the cutoff state, the write transistor QWFI becomes conductive because the base signal input is at a higher potential than the cell terminal VC, allowing current IDI to flow. ing.

Here, in order to detect the holding voltage, the external terminal VHC is raised from the lowest potential to the highest potential, here the ground level. As a result, the potential of the terminal CCH is set to a higher potential than either of the terminals VRH and PCI, so that the diode DHC and the transistor QRC2 become conductive. Resistance RC
The current source IVH and the current source IVH are level adjustment circuits, and are set to be equal to the word line selection control potential WDH when the external terminal VHC is set to the highest potential, which is the ground potential. The current densities of the transistors are made equal so that the emitter voltages of the hold detection transistor QRC2 when conductive are also equal, and in this state, the emitter potentials RC of the selected word line WTH and the hold detection transistor QRC2 are equal. In this state, the base potential VB of transistors QRI and QR2
, VC are both lower than the holding detection potential RC, so the transistors QRI and QR2 are both cut off,
Although the memory cell is selected, it enters a holding state in which no information is output to the bit line.

In this state, QH2 of the memory cell transistor is in a conductive state, and the collector terminal VC is at the word line level WT.
The potential of the terminal VB is approximately equal to D of the word line WTH if the current amplification factor of the transistor is large enough, and the transistor QHI is in a cut-off state. The cell holding voltage VH=VB-VC=I H1·RT.

In this state, the write data is inverted, and VDT is set to a high potential and WDF is set to a low potential. In this state, all memory cells are in a holding state, so no writing is performed.

The potential relationship in this state is shown in FIG. 2 (2-b).

From this state, the potential of external terminal VHC is gradually lowered, and accordingly, a one-to-one potential change occurs at the corresponding terminal R.
When the potential of C is lowered, the potential of terminal RC first becomes lower than VDT, which is the high potential of the write data, and transistor Q
RTI switches to the cut-off state and transistor QWTI to the conductive state.

In this state, the holding state of the memory cell remains unchanged. When the potential of the external terminal VHC is further lowered and the potential of the terminal RC is lowered, when the potential of the terminal RC becomes lower than the base potential VC of the non-conducting transistor QHI in the memory cell, the transistor QRF1 is in a cut-off state. Then, the memory cell transistor QRI becomes conductive and the memory cell is inverted (see (2-C) in FIG. 2).

Here, the base potential VC of the transistor QHI is lower than the word line WTH by IHI・RTVH, so the external terminal V
The amount of change in potential from the highest potential of HC is expressed as a retention voltage inside the memory cell.

Further, the data inversion state of the memory cell can be easily observed because changes in the cutoff and conduction of the read transistors QRFI and QRTI result in changes in the output waveform via the sense amplifier.

The holding voltage detection for the selected memory cell has been described above, but all non-selected memory cells maintain their holding state and have no effect at all. Furthermore, by changing the address signal and selecting another memory cell, it is possible to detect the holding voltage of each memory cell.

QRI, QR2...Memory cell transistors, [Effects of the Invention] As explained above, the present invention stabilizes a selected memory cell in a holding state by applying a holding voltage control signal from an external terminal; Since the memory cell content inversion operation can be determined by external terminals, the memory cell holding voltage can be tested for each memory cell in the memory circuit, and a high quality semiconductor memory can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory cell array of a semiconductor memory according to the present invention and its peripheral circuit, FIG. 2 is a diagram explaining the potential relationship of the circuit according to FIG. 1, and FIG. 3 is a conventional memory cell array and its peripheral circuit. FIG. 4, a circuit diagram showing the circuit, is a diagram for explaining the potential relationship in the circuit diagram shown in FIG. 3. QHI, QH2゜QWTI, QWT2゜Q"vVFl, QWF2...Transistor for write data, QRTI, QRT2゜QRFI, QRF2...Transistor for reading, QW
DI, QWD2...Word driver transistor, QDFl, QDTI. QDF2. QDT2...Transistor for read current switching, QRCI...Transistor for read control, QR
C2...Holding voltage detection transistor, DHC,
DRC...Level adjustment diode, SA...
...Sense amplifier, IDI, ID2/IHI, IH2/U12. U21°RCH, R9F. WDH, WDL φ Bl, B2 ・ ・ ・ WDT, WDF ・ Zl Life Φ ・ ・ φ Fist RCI ・ ・ ・ ・ ・ VHC ・ ・ ・ φ VB, VCφ ◆ ・

Claims (1)

[Claims] A semiconductor memory having a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each memory cell having a first multi-emitter transistor having first and second emitters and third and fourth emitters. A first emitter and a third emitter of a second multi-emitter transistor are connected to the first hold line, the second emitter is connected to the first bit line, and the fourth emitter is connected to the second bit line. the collectors of the first transistors are alternately connected to the bases of the second transistors, the collectors of the second transistors are alternately connected to the bases of the first transistors, and the collectors of the first transistors are connected to the first load means. the collector of the second transistor is connected to the first word line via a second load means;
, the second bit line is capable of selectively passing current, and the first bit line is connected to the emitter of the third transistor for writing and the emitter of the fourth transistor for reading,
The emitter of a fifth transistor for writing and the emitter of a sixth transistor for reading are connected to the second bit line, and write data output terminals are connected to the bases of the third and fifth transistors, respectively. The collectors of the fourth and fifth transistors are each connected to the input of the read data output circuit, the bases of the fourth and fifth transistors are connected to each other, and the sixth transistor whose base input is the read control signal and the holding voltage A semiconductor memory characterized in that a common emitter of a current switch is connected to a common base of the fourth and fifth transistors, the common emitter of a current switch having a configuration in which the emitters of each of a seventh transistor whose base input is a control signal are connected in common. .