JPH02146193A - Cascade connecting circuit driving system for shift register - Google Patents

Abstract

PURPOSE:To compensate the delay of data transmission to occur in a connecting line by partitioning the internal part of each shift register into a front stage part and a rear stage part, driving the respective parts by internal shift pulses, and advancing the pulse phase of the rear stage part from the pulse phase of the front stage part. CONSTITUTION:For a shift register 10, its last several or fewer stages are made into a rear stage part 12, all the other stages are made into a front stage part 11, and both parts are respectively driven by the internal shift pulses. These pulses are generated by a waveform shaping circuit 14 and a driving circuit 15. For a pulse S1 for the part 12, the output pulse of the circuit 14 is used. The circuit 15 receives the pulse S1, amplifies the pulse S1 so that the pulse S1 can be suitable for the driving of the part 11, uses slight time-lag to occur accompanying the amplification work for making the phase difference between a pulse S2 for the part 11 and the pulse S2, and makes the output of the circuit 15 into the pulse S2. Consequently, the phase of the pulse S1 is advanced from the phase of the pulse S2 for the time-lag in the circuit 15. The adverse effect of column connection can be completely compensated, and a high-speed operation can be attained by setting the phase difference larger.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to shift registers connected in series, and particularly to integrated circuit devices for driving printers, display panels, etc. each having a large number of data output points. The present invention relates to a method suitable for driving shift registers connected in cascade with a loading voltage on the basis of a common shift pulse.

[Conventional technology]

As is well known, a shift register sequentially transmits and stores data received at its data input terminal to each internal stage in synchronization with a shift pulse, but depending on the application, the total number of stages may exceed 1000. Therefore, this is divided into a plurality of shift registers, connected in series as described above, and then driven as a whole by a common shift pulse. For example, this is the case with the shift register incorporated in the driving integrated circuit of the printer mentioned above, and the situation is briefly shown in FIG.

In FIG. 3, printing elements provided for each dot to be printed are indicated by reference numeral 3, and these printing elements 3
receives a common power supply voltage V as shown in the figure, and 1 as described above.
Although more than 1,000 printing elements 3 can be lined up, an integrated circuit device 1 for driving them is provided for every several dozen printing elements 3, for example, 64 printing elements 3 due to connection reasons. Each integrated circuit device l includes a drive circuit 2 provided for each printing element and a shift register 1o that stores print data to be given to them.The drive circuit 2 receives data from each stage of the shift register 10, and receives the data. Each printing element 3 is turned on and off based on the following. In the drive circuit 2, latches, gates, output transistors, etc. are usually provided for each printing element, but these are simply shown as blocks in the figure.

Each integrated circuit device 1 is equipped with terminals for data input Di and data output Do for the shift register 1o, and the shift registers 10 of all integrated circuit devices 1 are connected to each other via these data input/output terminals as shown in the figure. are connected in cascade and driven by a common shift pulse S.

Therefore, in order to load the print data to drive the illustrated print elements into these shift registers, it is necessary to load the data in the shift register 10 of the leftmost integrated circuit device [1] in the figure.
Serial print data D may be applied to the shift registers 10 as shown in the figure, and a common shift pulse S may be applied to all shift registers 10 at the same time a predetermined number of times. After predetermined print data is loaded into these shift registers 1o, the drive circuits 2 in each integrated circuit device 1 are operated all at once to drive the printer elements 3, thereby printing a desired pattern. can.

[The problem that the invention seeks to solve]

To load predetermined data into multiple shift registers connected in cascade as described above, it is easy to see that a common shift pulse must be applied a number of times equal to the total number of stages of shift registers connected in cascade. Therefore, it is necessary to increase the repetition frequency of the shift pulse to complete data loading within as short a time as possible. For example, in the above-mentioned printers, the loading of print data into the shift register in each integrated circuit device and the printing operation based on the data are repeated, so in order to increase the printing speed of the printer, it is necessary to load the print data into the shift register. The time required must be shortened as much as possible.

However, when multiple shift registers are connected in series, a delay in data transmission is likely to occur within the connection line between the shift registers, and this transmission delay time is usually longer than the data transmission time inside the shift register, so this is not the rule. There is a problem that the frequency of the shift pulse cannot be increased as desired. As is well known, the length of connecting lines within an integrated circuit device is very short, but the length of connecting lines between integrated circuit devices must be below a minimum determined by the physical layout of the integrated circuit devices. Since it cannot be shortened, delays in data transmission inevitably occur.

An object of the present invention is to provide a shift register cascade connection circuit driving system that can alleviate such problems and compensate for data transmission delays that occur in connection lines for cascade connection of shift registers. .

[Means to solve the problem]

The present invention provides a method for driving a plurality of shift registers connected in series via a data transmission connection line with a common shift pulse, and divides the inside of each shift register into a front stage portion and a rear stage portion for supplying the shift pulse. By separately driving each part with an internal shift pulse based on a common shift pulse, and by advancing the phase of the internal shift pulse given to the latter part than the phase of the internal shift pulse given to the former part, the above purpose can be achieved. The goal is to achieve the following.

[Effect]

The present invention utilizes the fact that the data transmission speed inside the shift register is high enough to compensate for all or a considerable portion of the delay time of data transmission within the connection line, so that each shift register By advancing the phase of the internal shift pulse given to the latter part of the internal shift pulse from the phase of the internal shift pulse given to the former part, the delay time of data transmission in the connection line is compensated for by the time equivalent to this phase difference. They also succeeded in driving a cascaded circuit of shift registers with a high frequency common shift pulse.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure illustrates a circuit in the case where the present invention is implemented in the shift register 10 in each integrated circuit device 1 shown in FIG.
FIG. 2 shows the waveforms of the main signals and how the data changes.

In FIG. 1, the shift register 10 usually consists of several tens of stages, as mentioned above, but in the practice of the present invention, the last few or less of the stages are considered to be the latter stage part 12, and all the remaining parts are The image portions are each driven by a separate internal shift pulse. Although the number of stages in the rear stage section 12 may be at least one, it is usually desirable to have several stages in order to ensure smooth interstage transmission of data throughout the shift register 10. Although the image portions 11 and 12 are shown slightly separated from each other in the figure for convenience, they are actually continuous and integral. In addition, the figure also shows the latter part 1.
A waveform shaping circuit 13 consisting of two inverters is located behind the
This is conventionally used to shape the on/off of the data output DO of each shift register or the switching of rH, jJLJ into a clear waveform when multiple shift registers are connected in series. , does not have a particularly important meaning in terms of the essence of the present invention.

The internal shift pulses for the front part In and the rear part 12 of the shift register 10 are each 2 in this embodiment.
The waveform shaping circuit 14 and drive circuit 15 each include two inverters. The internal shift pulse S1 for the subsequent stage portion 12 may be the common shift pulse S received by the shift register IO, but in this example, a shift pulse passed through the waveform shaping circuit 14 is used. The drive circuit 15 receives the internal shift pulse Sl, which is the output shift pulse of the waveform shaping circuit 14, and originally amplifies it so that it is suitable for driving a large number of stages in the front stage section 11, but this implementation In the example, a slight time delay caused by the amplification effect is used to create a phase difference with the internal shift pulse Sl, and the output thereof is used as the internal shift pulse S2 for the pre-stage section 11. Therefore, the phase of the internal shift pulse S1 is advanced from the phase of the internal shift pulse S2 by the time delay within the drive circuit 15. Of course, this phase difference can be increased by inserting a simple delay circuit element between the waveform shaping circuit 14 and the drive circuit 15.

Figure 2) ~ (ω is a common shift pulse S and these two
The waveforms of internal shift pulses S1 and S2 are shown. As can be seen from the figure, the phase of the internal shift pulse St is delayed from the common shift pulse S by an amount corresponding to the operation delay time H of the waveform shaping circuit 14, and the phase of the internal shift pulse S2 is delayed from the common shift pulse S by an amount corresponding to the operation delay time H of the waveform shaping circuit 14. Shaping circuit 1
In this example, the phase difference between the in-plane shift pulses S1 and S2 is equal to the operation delay time Δ of the drive circuit 15.
It becomes equal to t=t2-H.

FIG. 2(a) shows the data input D1 of the shift register 10.
In other words, it shows how the data stored in the first stage in the previous stage portion 11 changes. The shift register is of a so-called master-slave type, for example, and reads the stored data in the previous stage in synchronization with the rising edge of the shift pulse, for example from rLJ to rHJ.
Data is transmitted to the next stage in synchronization with the falling edge of . The front stage portion 11 of the shift register 10 receives an internal shift pulse S.
As shown in FIGS. 2(a) and 2(d), the data input D is read into the first stage of the front stage section 11 in synchronization with the rise of the internal shift pulse S2.
1 is switched.

FIG. 2(e) shows the data output DO of the shift register 10.
The state of change is shown. In the present invention, since the rear stage part 12 of the shift register lO is driven by the internal shift pulse S1, the signal from the final stage in the rear stage part 12 is synchronized with the falling edge of this internal shift pulse S1 shown in FIG. The data output Do is switched after some transmission delay time td. For comparison, FIG. 2(f) shows how the data output 00 changes when all stages of the shift register 10 are driven by the shift pulse S2 as in the conventional case. Internal shift pulse S2 in figure (6)
The data output Do is switched in synchronization with the falling edge of , and after a delay time td.

As can be seen by comparing FIG. 2(e) and (0), in the case of the present invention, the internal shift pulse S
The data output DO is advanced by the above-mentioned time ΔL, which is advanced from the internal shift pulse S2 which gives the phase of
switching can be accelerated. Therefore, if this time Δt is set to be greater than or equal to the transmission time delay occurring in the cascade connection lines of the shift register, the present invention can completely compensate for the negative influence of the cascade connection, even if it is less than Some of the negative effects can be compensated for. When shift registers built in integrated circuit devices are connected in series, the phase difference between internal shift pulses S1 and S2 should be made larger than the transmission delay time in the connection line, unless the distance between the integrated circuit devices is extremely long. can be set to completely compensate for the negative effects of cascade connection.

Incidentally, in the above embodiment, the latter part 1 of the shift register 10 is
Although this is for the case where the number of 20 stages is smaller than the number of stages of the front stage part 11, the above is not limited to this, and the front stage part 11 may have at least one stage, and the remaining part may be the rear stage part 12. It is clear from the description of the present invention and embodiments. That is, in the present invention, the front part 11
The ratio of the number of stages in the second stage portion 12 is essentially not particularly important.

〔Effect of the invention〕

As explained above, according to the present invention, when driving a plurality of soft registers connected in series via a data transmission connection line with a common shift pulse, the interior of each shift register is transferred to the previous stage for supplying the shift pulse. It is divided into a section and a subsequent section, and each section is driven by an internal shift pulse based on a common shift pulse,
By leading the phase of the internal shift pulse applied to the latter part than the phase of the internal shift pulse applied to the former part, it is possible to compensate for the delay time of data transmission occurring in the connection line.

This increases the frequency of the common shift pulse to nearly the limit of each shift register's inherent high-speed performance, while eliminating or at least mitigating the negative effects of cascade connection, thereby increasing the frequency of the common shift pulse to almost the limit of each shift register's inherent high-speed operation performance, and transmitting data to all stages of the cascade shift registers. Loading time can be shortened. This feature is particularly important when used in a group of integrated circuit devices for driving printers or display panels. The printing or display speed of the display panel can be improved.

[Brief explanation of the drawing]

Claims (1)

[Claims] (1) A method in which a circuit in which a plurality of shift registers are connected in series via connection lines for data transmission is driven by a common shift pulse, and the inside of each shift register is connected to the front stage for supplying shift pulses. and a rear stage part, each part is driven by an internal shift pulse based on a common shift pulse, and the phase of the internal shift pulse given to the latter part is advanced from the phase of the internal shift pulse given to the former stage part. A cascade-connected circuit drive system for shift registers.