JPH02144772A - Magnification/reduction controller - Google Patents

Abstract

PURPOSE:To easily and quickly calculate an approximate value by setting a complementary constant at the idle part of a higher rank bit. CONSTITUTION:When data are stored in a source register 2 via a data bus 1, a controller 3 interprets an instruction code received from outside and sets the value of a constant register 6. When the controller 3 receives an instruction to apply the logical arithmetic to 2 bits contiguous to the data stored in the register 2, the controller 3 decides the arithmetic to be applied to the data out of all logical arithmetic functions and sends a control signal to an arithmetic unit 4 to perform a logical arithmetic and to output the arithmetic result. The register 6 stores its holding data into a idle part if produced in a higher rank bit of a destination register 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an enlargement/reduction control device suitable for use in reducing image data.

(Prior Art) Generally, reducing image data requires a thinning operation, and enlarging it requires a copying operation.

To specifically reduce data, have a table of bit patterns and operation results for them, search the table using the bit pattern of the data to be operated as a key, obtain the result, and then fill the upper bits with free space. When this occurred, a logical operation was performed and this part was cleared to 0.

(Problems to be Solved by the Invention) If the above operations are implemented using software, the processing is complicated and takes time. Therefore, it has been difficult to employ it in applications that require high speed, such as image processing. It also had the disadvantage of requiring a large amount of memory for tables and being uneconomical.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an enlargement/reduction control device that performs data reduction etc. at high speed using an arithmetic mechanism built into a central processing unit of a computer.

[Structure of the Invention] (Means for Solving the Problems) The enlargement/reduction control device of the present invention includes an arithmetic device that performs a logical operation for every two adjacent bits on data to be arithmetic, and a It decodes the logic operation command and instructs the above-mentioned arithmetic unit to perform the necessary logic operation function, and when the upper bit becomes vacant as a result of the above-mentioned operation,
It is composed of a control device that sets constants to be supplemented therewith.

(Operation) In the above configuration, the arithmetic device has an arithmetic function that compresses the data by performing a logical operation on every two adjacent bits on the data to be arithmetic, and then adds O or 1 to the upper vacant bit. By providing the
a and d) functions such as reduction and OR reduction are realized. By realizing AND reduction and OR reduction of data as arithmetic functions of the central processing unit, data thinning in image processing and calculation of approximate values in approximate calculations such as Newton's method can be performed easily and quickly. effective.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a data bus, and data is transferred bit-parallel here. Reference numeral 2 is a source register in which data to be subjected to an operation is stored. Reference numeral 3 denotes a control device, which has a function of interpreting instructions given from the outside, determining and controlling a logical operation function to be performed by the arithmetic device, and a function of setting a value of a constant register to be described later.

4 is an arithmetic unit which performs a logical operation specified by the control unit 3 on each pair of bits of the source register 2; 5
is a destination register, and the data of the operation result is stored. 6 is a constant register, which holds the value to be placed in the upper empty bit.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. Data to be operated on passes through a data bus 1 and is stored in a source register 2. The control device 3 interprets command codes given from outside the control device 3. When the control device 3 receives an instruction to change the value of the constant register 6, it sets the value of the constant register 6 in accordance with the instruction. The control device 3 stores two adjacent data of the source register 2.
When a command to perform a logical operation on the bits is given, it determines the operation to be performed on the data from among all the logical operation functions according to the command and sends a control signal to the arithmetic unit 4.

The data of each bit of the source register 2 is input to the arithmetic unit 4 every two adjacent bits. The arithmetic unit 4 performs a specified logical operation on the input bit data according to the signal from the control unit 3 and outputs the result to each bit of the destination register 5. The constant register 6 holds a value to be filled in when the upper bit of the destination register 5 becomes vacant.

The output from the arithmetic unit 4 is stored in each bit of the destination register 5 starting from the lower bit, and when an empty space occurs in the upper focus, the data held in the constant register 6 is stored in this portion.

[Effects of the Invention] As explained above, according to the present invention, by realizing AND reduction, OR reduction, etc. of data as an arithmetic function of a central processing unit, data thinning in image processing and approximation of Newton's method etc. This has the advantage that approximate values can be easily and quickly calculated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Data bus, 2...Source register, 3...
- Control device, 4... Arithmetic device, 5... Destination register, 6... Constant register. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] An arithmetic unit that performs a logical operation on each adjacent 2 bits on the data to be operated on, and an arithmetic unit that decodes the logical operation command that comes from the outside and instructs the arithmetic unit to perform the necessary logical operation function. 1. An enlargement/reduction control device comprising: a control device that sets a constant to fill in a vacant space in upper bits when a vacant space is generated in the upper bit as a result of an operation.