JPH02144626A - Microprocessor - Google Patents

Abstract

PURPOSE:To rapidly execute a branching instruction without disturbing a pipeline by registering a branching address, instruction length and a branched address in a branch forecasting table at the time of generating a branch, and at the time of prefetching the branch instruction, fetching the branched instruction without fetching its succeeding instruction. CONSTITUTION:An instruction prefetch is executed by outputting a prefetch pointer 202 to the outside of a microprocessor through a prefetch address bus 101 and updating the pointer 202 by an output from an address incrementer 203. Simultaneously with said operation, the branch forecasting table is indexed, and at the time of prefetching an instruction registered in the table, the prefetch is informed to a prefetch pointer control circuit 204 by an output signal 105 from an address comparator 206. The circuit 204 prefetches a branch instruction hit by a branch instruction length 111 hit in the branch forecasting table up to the final byte and then sets up a forecasting branched address 104 in the prefetch pointer 202. Thus, the branching instruction can be rapidly executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Vibrine processing type microprocessor.

[Conventional technology]

Instruction vibe line processing assumes that the instruction addresses are consecutive, so if a branch occurs,
It is necessary to invalidate all instructions on the vibe line and start over from fetching instructions. Conventionally, in the Vibrine method, in order to reduce losses due to branches, a table is prepared for caching branch instruction addresses and branch destination instructions.When a branch instruction is executed, this table is searched and the branch instruction to be fetched is searched. If the address was written, the branch destination instruction was obtained.

[Problem to be solved by the invention]

The above-mentioned prior art attempts to shorten recovery from a vibeline flush when a branch occurs, but cannot reduce the vibeline flush itself.

Another disadvantage is that increasing the number of words of branch instructions to be cached increases the required resources by (number of entries) x (increase in branch destination instructions).

[Means to solve the problem]

A pipeline processing type microprocessor with a built-in branch prediction control mechanism according to the present invention has a branch prediction table that registers a prefetch pointer, the start address of a branch instruction, a branch instruction length, and a branch destination address, and a branch prediction table that registers a prefetch pointer, the start address of a branch instruction, a branch instruction length, and a branch destination address. Mechanism for registering in the table and prefetch/
When an address hits the branch prediction table, the branch instruction is fetched as many instructions as necessary from the branch instruction length, and then the branch destination address is hit in the prefetch pointer.

In this way, the address where the branch instruction is located and the bare branch destination address are stored in the branch prediction table, and when the branch instruction registered in the branch prediction table is executed again, the instruction can be executed at high speed without disturbing the pipeline. can be executed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing functional blocks that perform processing from instruction prefetch to instruction decoding in a pipeline processing type microprocessor.

The instruction decoder 201 has a function of decoding a prefetched instruction, generating a branch destination address according to the instruction code when the instruction is a branch instruction, and transferring the branch destination address via the branch destination address bus 102. If the branch instruction is an unconditional branch instruction that does not change dynamically, that is, it does not refer to registers or memory values to calculate the branch destination address, the start address of the branch instruction (hereinafter referred to as the branch source address) and the branch instruction It has the function of outputting the length and issuing registration instructions. The prefetch pointer 202 holds the main memory address at which instructions should be prefetched, and is output to the outside of the microprocessor via the prefetch address 101. The prefetch control circuit 204 controls updating of the prefetch pointer 202, and the contents of the prefetch pointer are stored in the address incrementer 2.
03 output 103. Predicted branch destination address path 104,
One of the branch destination address buses 102 is selected and updated. The branch prediction table 207 includes branch source address 3
01. Valid flag 302° Branch instruction length 3032 Branch destination and branch source addresses are registered, and registration is performed by the branch prediction table control circuit 205 when a branch occurs.

Next, the branch prediction operation of this embodiment will be explained. Instruction prefetching is performed by outputting prefetch pointer 202 to the outside of the microprocessor via prefetch address bus 101 and updating prefetch pointer 202 with the output of address incrementer 203. If the branch prediction table is indexed at the same time and an instruction registered in the branch prediction table is prefetched (hereinafter referred to as a branch prediction table hit), the address comparator 20
6 output signal 105 causes prefetch control circuit 204
will be notified. The prefetch control circuit prefetches the hit branch instruction up to the final byte based on the branch instruction length 111 stored in the branch prediction table, and then sets the predicted branch destination address 104 in the prefetch pointer 202.

FIG. 2 is a block diagram of another embodiment of the present invention, in which a return address register 209 and a prediction error signal 114 are added to the above embodiment.

In this embodiment, since the start address of the instruction following the predicted branch instruction is stored in the return address register 209, there is an advantage that branch prediction of a conditional branch can be performed.

Next, the branch prediction operation of this embodiment will be explained. When an instruction is prefetched, if the branch prediction table is hit, the hit branch instruction is prefetched to the final byte according to the branch instruction length, and then the start address of the following instruction is stored in the return address register 209, and the predicted branch destination is Set the address to prefetch pointer 202. When the instruction decoder 201 is notified by the misprediction signal 114 that the condition of the predicted branch instruction has not been met, the contents of the prefetch pointer 202 are updated to the contents of the return address register 203, and the predicted branch instruction is executed. Prefetch subsequent instructions. If the condition is met, prefetching continues.

〔Effect of the invention〕

As explained above, the present invention registers a branch source address and an instruction length 2 branch destination address in a branch prediction table when a branch occurs, and then when that branch instruction is prefetched, the following instruction is By fetching the branch destination instruction without fetching, the branch instruction can be executed at high speed without disturbing the vibe line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment. 101... Prefetch address bus, 10
2... Branch destination address bus, 103...
・Address incrementer output, 104...
Predicted branch destination address bus, 105... Branch prediction table/hit signal, 106... Branch prediction table/branch source address bus, 107... Branch instruction signal, 108... ...Branch prediction table/registration instruction signal, 109...Branch source address bus, 1
10... Branch instruction length, 111... Branch instruction length hit in the branch prediction table, 112...
...Prefetch pointer update instruction signal, 113...
...Return address pointer update instruction signal, 1
14...Branch prediction error signal, 201...
・・Instruction decoder, 202 ・・Prefetch・
Pointer, 203... Address incrementer, 204... Prefetch, control circuit, 20
5... Prefetch pointer input Kamarichi lexer, 206... Address comparator, 2
07... Branch prediction table, 208...
・Branch prediction table control circuit, 209...Return address register, 301...Branch prediction table/branch source address section, 302...Branch prediction table Paris, flag , 303... Branch prediction table/instruction length section, 304... Branch prediction table/branch destination address section. Agent Patent Attorney Uchihara Otohaku 1 Zuko? Possible

Claims (1)

[Claims] A prefetch pointer indicating an instruction prefetch address, a branch prediction table for caching the start address, branch instruction length, and branch destination address of a branch instruction whose branch destination address does not change dynamically, and a branch prediction table for caching the branch instruction length and branch destination address when a branch occurs. means for registering in a prediction table, and when a prefetch address hits the branch prediction table, prefetching the hit branch instruction as many instructions as necessary from the branch instruction length, and then registering the branch destination in the prefetch pointer; A microprocessor comprising: means for setting an address.