JP3394854B2 - Unconditional jump instruction processing method, unconditional jump instruction processing device therefor, and general-purpose register - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an unconditional jump instruction processing method and an apparatus therefor, and particularly when a predecoded instruction is an unconditional jump instruction, a first branch in a specific area of a general-purpose register. The second branch destination address specified by this prefetches and holds the branch destination instruction from the storage area of the destination address, and at the time of executing the decoded unconditional jump instruction matches the first branch destination address. It is confirmed that the branch destination instruction is continuously executed.

Generally, in order to speed up the branch processing of an unconditional jump instruction in a processor, a branch destination address is held in a specific area of a general-purpose register, and this branch is executed when the unconditional jump instruction is predecoded. Prefetching the branch destination instruction at the destination address is performed.

Then, for example, in the case of a high-reliability system in which the outputs of multiple processors each performing pipeline processing are compared with each other, a parity error or the like generated in the first processor is notified to the second processor. Before the processor executes a new instruction to change the contents of the specific area, that is, the branch destination addresses specified by the general-purpose registers of the first processor and the second processor do not match, It is desirable to suppress the occurrence of an error state in which the branch destination instructions that are prefetched differ when an unconditional jump instruction is issued after both processors have started resynchronization, and the present invention addresses such a demand.

[0004]

2. Description of the Related Art FIG. 5 is an explanatory view showing an outline of a conventional unconditional jump instruction processing system. 11 is a main memory, 12 is an instruction cache, 13 is an instruction buffer, and 14 is a predecode in this instruction buffer. Section, 15 is an instruction type signal, 16 is a decoding section, 17 is a data cache, 18 is a general register, 19 is a specific area (eg GR3) in this general register, and 20 is a branch stored in this specific area. A destination address, 21 is an arithmetic unit, and 22 is a gate unit.

Here, the instruction group transferred from the main memory 11 to the instruction cache 12 is fetched into the instruction buffer 13 in the order instructed by the program counter (not shown) and predecoded by the predecoding section 14 there. It is determined whether the content is an unconditional jump instruction.

If the result of this determination is "unconditional jump instruction", an instruction type signal 15 to that effect is sent to the gate section 22 to open it, and the specific area in the general register is opened.
The branch destination address 20 of 19 is given to the main memory 11 and the instruction cache 12 as prefetch data, and the instruction (branch destination instruction) in the area of the branch destination address 20 is prefetched and stored in the instruction buffer 13.

Then, when the unconditional jump instruction fetched from the instruction buffer 13 is decoded by the decoding unit 16 and the content thereof is executed by the arithmetic unit 21, the processor deactivates the data in the general-purpose register area designated by the instruction. -Whether it matches the target address (original branch destination address) and the branch destination address 20 used during prefetch.

If the result is "match", the branch destination instruction already stored in the instruction buffer 13 is continuously executed, and if "no match", this branch destination instruction is canceled and the original The process moves to the fetch processing to the branch destination address of.

As described above, in the case of an unconditional jump instruction, the branch destination address to be executed following the instruction is prefetched into the instruction buffer 13 in advance by predicting the branch destination address at the time of predecoding. Then, the prefetched branch destination instruction is used after confirming that the original branch destination address and the previous predicted value match when the unconditional jump instruction is executed thereafter.

In order to improve the prediction accuracy of this branch destination address, the program creator must: -Data of the general-purpose register area designated by the unconditional jump instruction (original branch destination address) and predecoding of the instruction. Create each program such that the data (predicted branch destination address) of the specific area 19 at the time is matched as much as possible, and the specific area 19 is used as much as possible as a general-purpose register area specified by the unconditional jump instruction. become.

The general-purpose register 18 generally does not have a valid flag like a cache memory or an address translation buffer. This is because the setting of general-purpose registers is performed by the program, so that the creator can know which area the data is written to and which area is invalid data (undefined data). This is because the program content should not refer to this invalid data area.

As an example of the unconditional jump instruction,
For example, the return address is stored in a general-purpose register by a subroutine call instruction, and the value of this general-purpose register is used when returning from the subroutine.

FIG. 6 is an explanatory diagram showing a state where a parity error occurs in one of the conventional dual processors, and both CPU # 1 and CPU # 2 pipeline the same instruction group. . The contents of each instruction are decoded (Decode) -operation (Execute) -write (Write).
Is a series of processing.

The CPU # 1 cancels the instruction execution of the next cycle due to the occurrence of a parity error in the decode cycle of the instruction 1 (first cycle), generates an interrupt, and then shifts to sequential processing.

The CPU # 2 receives the parity error notification from the CPU # 1 in the fifth cycle, cancels the instruction execution in the cycle, generates an interrupt, and then shifts to the sequential processing.

That is, the CPU # 1 is the CPU # 1.
Even after the parity error occurs, the process is continued to process the instructions 1 to 4, and as a result of the execution of the instruction 2, the contents of the GR3 area (specific area) of the general-purpose register 18 of the CPU # 2 are It is updated with the added value of the data in the GR4 area and the data in the GR5 area.

On the other hand, the GR of the general-purpose register 18 of the CPU # 1
Since such an update is not performed for the three areas, the contents of the GR3 area in each CPU at the time of the interrupt occurrence (the final cycle of the process execution), that is, the branch destination address will be inconsistent. However, a mismatch of branch destination addresses at this stage does not result in an error.

The sequential processing is to wait for the completion of the push-out processing which has not been completed at the time of occurrence of the interrupt. For example, when writing to the memory is requested by an instruction before that and there is a waiting for the writing. This is to make the state transition to the interrupt processing wait until the execution of this is completed.

Both CPU # 1 and CPU # 2 start resynchronization at the time of t _{1 in} the stopped state and shift to the save / switch processing. At this time, each CPU has a PSW (processor status wor) that indicates its own state at the time of occurrence of an interrupt.
d) or a PC (programm counte) that indicates the address of the execution instruction
The contents of r) are temporarily saved in the respective control registers and the like, and the contents of PSW and PC are switched to new data for interrupt processing.

Subsequently, CPU # 1 and CPU # ₂ set t ₂
At the point of, the process is restarted (interrupt processing). At this time, each CPU invalidates each flag of its own cache memory and address translation buffer, and also matches the contents of corresponding internal registers and the like, and then returns. The general-purpose register of each CPU does not have a flag and is not invalidated.

Here, "return" means returning from interrupt processing to normal processing, that is, process execution using each data of PSW, PC and general-purpose register restored to match in each CPU. It is to restart.

Further, in order to match the contents of the internal registers of each CPU, the saved data and the like are written to the memory with reference to an arbitrary one of the multiple CPUs and read by all CPUs. Done.

On the other hand, the illustrated CPU # 1 and CPU # 2
Even if the interrupt processing is started, G of each general-purpose register 18 is kept until the processing for matching the internal states of the CPUs is completed.
The data in the R3 area (specific area) remains inconsistent.

Therefore, when the unconditional jump instruction in the interrupt processing program is pre-decoded, the branch destination address fetched from the GR3 area of the general-purpose register 18 by the CPU # 1 does not match that of the CPU # 2. An error will occur.

[0025]

In such a conventional unconditional jump instruction processing system, the branch destination address predicted at the time of predecoding the instruction and the branch destination address expected by the unconditional jump instruction are different from each other. If they do not match,
There is a problem that the prefetch processing performed using this predicted address becomes useless.

In addition, before a second processor is notified of a parity error or the like that has occurred in the first processor in a high-reliability system in which the outputs of multiple processors are compared with each other, the contents (prediction of a specific area of the processor) When the branch destination address) is changed, the predicted addresses do not match, so after the two processors have started resynchronization, the contents of this specific area remain unmatched and unconditional in the interrupt processing program. When the jump instruction is pre-decoded, there is an inherent problem that the branch destination addresses of the two differ.

Therefore, in the present invention, a flag indicating valid / invalid is provided in the general-purpose register area that stores the predicted value of the branch destination address of the unconditional jump instruction at the time of predecoding, and this is set to "invalid". In this case, by prohibiting the prefetch processing of the branch destination instruction of the unconditional jump instruction, it is possible to eliminate the waste of the prefetch processing of the branch destination instruction and to improve the reliability of the prefetch processing of the branch destination instruction in the multiprocessor. With the goal.

[0028]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, reference numeral 1 denotes a storage means, which holds a branch destination instruction of an unconditional jump instruction at a branch destination address A ₀ (predicted value). Reference numeral 2 denotes an instruction executing means, which performs a series of processes such as predecoding, decoding, and execution of the instruction fetched from the storage means 1. Reference numeral 3 is a prefetch requesting means, which outputs a prefetch request when the instruction type is "unconditional jump instruction" and a flag 6 described later is "valid (set state)". Reference numeral 4 is a general-purpose register that holds the branch destination address of the unconditional jump instruction. A specific area 5 holds a branch destination address A ₀ (predicted value). Reference numeral 6 is a flag that indicates whether the branch destination address A ₀ is valid /
Indicates invalid. A flag setting means 7 invalidates (resets) the flag 6 when the power is turned on or when various errors (parity error, bus error, etc.) are detected. The flag 6 is validated by rewriting the specific area 5.

The outline of the processing in the instruction executing means 2 is as follows. The instruction fetched from the storage means 1 is predecoded and its type is notified to the prefetch request means 3. Holds the prefetched branch destination instruction. Decode the instruction. Execute the decoded contents. When the instruction is an unconditional jump instruction and the branch destination address specified there is coincident with the predicted value A ₀ , the branch destination instruction already held is continuously executed.

FIG. 2 is an explanatory diagram showing a situation when a parity error occurs in one of the dual processors of the present invention, and CPU # 1 and CPU # 2 are the same as in the case of FIG.
Both pipeline the same instruction group.

6 differs from the case of FIG. 6 in that the flag 6 is invalidated at any time from when the occurrence of a parity error is detected to when the process execution is restarted (t ₂ ). When the process execution is restarted (t ₂ ), the branch destination address A ₀ of the specific area (eg, GR3) 5 of the general-purpose register 4 is, so to speak, prohibited from being used.
Unless the specific area 5 of U # 1 and CPU # 2 is written, the branch destination instruction is not prefetched at the time of predecoding an unconditional jump instruction.

The basic configuration of the unconditional jump instruction processing method of the present invention is that "when the predecoded instruction is an unconditional jump instruction, the first branch destination address in the specific area of the general register is While prefetching and holding the branch destination instruction from the storage area, when executing the unconditional jump instruction after decoding, it is possible that the second branch destination address specified thereby matches the first branch destination address. After confirming, in the unconditional jump instruction processing method for executing the branch destination instruction following the unconditional jump instruction, a flag that is invalidated in a predetermined state is provided corresponding to the specific area, The branch destination instruction is prefetched only when is valid. "

The basic configuration of the unconditional jump instruction processing device of the present invention is that "when the predecoded instruction is an unconditional jump instruction, the first branch destination address in the specific area of the general register is While prefetching and holding the branch destination instruction from the storage area, when executing the unconditional jump instruction after decoding, it is possible that the second branch destination address specified thereby matches the first branch destination address. In the unconditional jump instruction processing device that continuously executes the branch destination instruction after checking, a flag corresponding to the specific area and invalidated in a predetermined state, and the flag only when the flag is valid And a prefetch request means for outputting a prefetch request for a branch destination instruction. "

The basic structure of the general-purpose register of the present invention is as follows: "In a general-purpose register in which a branch destination address indicating a prefetch destination when an unconditional jump instruction is predecoded is held in a specific area, Corresponding and provided with a flag that is invalidated in a predetermined state to suppress the prefetching. "

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. FIG. 3 is an explanatory diagram showing an outline of the unconditional jump instruction processing method of the present invention. The flag 6 and the flag setting means 7 described above are added to those shown in FIG.
A new AND circuit 23 is provided.

A flag signal 24 and an instruction type signal 15 are input to the AND circuit 23, and the output signal of the AND circuit 23 controls the gate section 22 so that the flag signal 24 indicates the "valid flag" and the instruction type signal 15 Are "unconditional jump instructions" respectively, the specific area 19 (GR
The branch destination address A ₀ written in 3) is the gate section.
It is sent to the main memory 11 through 22.

FIG. 4 is an explanatory diagram showing a processing procedure for an instruction fetched in the instruction buffer, and the contents thereof are as follows. (1) The prefetch unit 14 predecodes the instruction fetched in the instruction buffer 13, and proceeds to the next step. (2) Determine whether the instruction type is an "unconditional jump instruction" and flag 6 is enabled (set),
If the result is "YES", proceed to the next step and select "N
If “O”, proceed to step (4). (3) The branch destination instruction at the branch destination address A ₀ specified by the specific area 19 (GR3) of the general-purpose register 18 is prefetched from the main memory 11 and held in the instruction buffer 13, and the process proceeds to the next step. (4) The decoding unit 16 decodes the instruction fetched from the instruction buffer 13.
Decode with and proceed to the next step. (5) Determine whether the instruction type is an "unconditional jump instruction". If the result is "YES", proceed to the next step, and if "NO", proceed to step (9). (6) The branch destination address specified by this instruction and the step
It is determined whether or not the branch destination address A ₀ obtained in (3) matches, and if the result is "YES", the process proceeds to the next step, and if "NO", the process proceeds to step (8). (7) The branch destination instruction prefetched in step (3) is fetched from the instruction buffer 13 and executed, and the instruction decoded in step (4) is canceled. (8) Cancel the branch destination instruction prefetched in step (3) and proceed to the next step. (9) Execute the instruction decoded in step (4).

The branch destination address is specified in step (6) by extracting the data written in the general-purpose register area specified in the instruction. In addition,
As this general-purpose register area, any area including the specific area 19 is generally used.

In the case of an instruction that follows the route from step (8) to step (9), the data (branch destination address) in the general-purpose register area specified in the instruction is read out and the address is stored in the main memory 11. Fetch processing is performed such as fetching the branch destination instruction that is present.

[0040]

As described above, according to the present invention, a flag indicating validity / invalidity is provided in the general-purpose register area for storing the predicted value of the branch destination address of the unconditional jump instruction at the time of predecoding. , The prefetch processing of the branch destination instruction of the unconditional jump instruction is prohibited.

Therefore, it is possible to eliminate the waste of the prefetch process due to the mismatch between the branch destination address (predicted value) at the predecoding of the unconditional jump instruction and the branch destination address (expected value) at the decoding.

Further, in a system in which processors are multiplexed, consistency of outputs of respective processors is ensured when a branch destination instruction prefetched at the time of predecoding an unconditional jump instruction is executed at the time of decoding the unconditional jump instruction. The reliability of the system can be increased.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram showing a situation when a parity error occurs in one of the dual processors of the present invention.

FIG. 3 is an explanatory diagram showing an outline of an unconditional jump instruction processing system of the present invention.

FIG. 4 is an explanatory diagram showing a processing procedure for an instruction fetched in an instruction buffer according to the present invention.

FIG. 5 is an explanatory diagram showing an outline of a conventional unconditional jump instruction processing method.

FIG. 6 is an explanatory diagram showing a state when a parity error occurs in one of the conventional dual processors.

[Explanation of symbols]

In FIG. 1 ... storage means 2 ... Instruction execution means 3 ... Prefetch request means 4 ... General purpose register 5: Specific area 6 ... Flag 7 ... Flag setting means

Continuation of front page (56) Reference JP-A-6-266556 (JP, A) JP-A-2-166520 (JP, A) JP-A-5-216852 (JP, A) JP-A-2-59822 (JP , A) JP-A-7-84786 (JP, A) JP-A-8-123686 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/38

Claims (6)

(57) [Claims] 1. When the predecoded instruction is an unconditional jump instruction, the branch destination instruction is prefetched and held from the storage area of the first branch destination address contained in the specific area of the general-purpose register, and after decoding. When executing the unconditional jump instruction, the unconditional jump for executing the branch target instruction continuously after confirming that the second branch target address specified thereby matches the first branch target address. In the instruction processing method, a flag to be invalidated in a predetermined state is provided corresponding to the specific area, and the branch destination instruction is prefetched only when the flag is valid. Jump instruction processing method. 2. The unconditional jump instruction processing method according to claim 1, wherein the predetermined state is immediately after power is turned on or when a hardware abnormality such as a parity error is detected. 3. When the predecoded instruction is an unconditional jump instruction, the branch destination instruction is prefetched and held from the storage area of the first branch destination address in the specific area of the general-purpose register, and after decoding When executing the unconditional jump instruction, the unconditional jump for executing the branch target instruction continuously after confirming that the second branch target address specified thereby matches the first branch target address. The instruction processing device includes a flag that corresponds to the specific area and is invalidated in a predetermined state, and a prefetch request unit that outputs a prefetch request of the branch destination instruction only when the flag is valid. An unconditional jump instruction processing device characterized by the above. 4. The unconditional jump instruction processing device according to claim 3, wherein the predetermined state is immediately after power-on, when a hardware abnormality such as a parity error is detected, or the like. 5. A general-purpose register in which a branch destination address indicating a prefetch destination at the time of predecoding an unconditional jump instruction is held in a specific area, which corresponds to the specific area and is invalidated in a predetermined state. A general-purpose register having a flag for suppressing the prefetch. 6. The general-purpose register according to claim 5, wherein the predetermined state is immediately after power-on or when a hardware error such as a parity error is detected.