JPH02143999A - Shift register circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of a source voltage to a minimum in the case of performing a fast operation by using a fast circuit device by allocating position logic and negative logic on both the serial direction and parallel direction of a shift register with multiple stages. CONSTITUTION:Either the odd bit or the even bit of each row is allocated to the positive logic and the other to the negative logic, and also, either the same bit of an add row or an even row is allocated to the positive logic and the other to the negative logic. Therefore, when all the data of (n) bits inputted in parallel change from High to Low, the output of around the half of circuit devices change from High to Low, and that the remaining half of the circuit devices change from Low to High, and so as whole, the number of outputs of the circuit device changing from High to Low becomes almost equal to that of the outputs of the circuit device changing from Low to High. In such a way, influence on a power source can be eliminated, which prevents the malfunction of a circuit occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift register circuit, and particularly to a shift register circuit that is suitable for driving multi-stage shift registers simultaneously in a high-speed image processing device or the like.

[Conventional technology]

Image processing devices and the like require multi-stage shift registers, but when multi-stage shift registers operate simultaneously, fluctuations in power supply voltage become large, which in extreme cases can induce malfunctions. Conventionally, as a method for dealing with this, for example, as described in Japanese Unexamined Patent Publication No. 61-50292, a multi-stage shift register is sequentially switched and operated at every predetermined clock, and the shift register that is operating at a certain time is switched. There is a method of reducing the instantaneous value of current consumption by always making it a part of the whole.

[Problem to be solved by the invention]

The above-mentioned prior art assumes that even if the power supply voltage momentarily drops due to a certain clock pulse, the power supply voltage will return to its original normal state before the next clock pulse.

This is fine when using relatively low-speed circuit elements such as 0MO5-IC, but when using high-speed circuit elements such as ECL-IC and driving a multi-stage shift register with high-speed clock pulses, the power supply voltage due to a certain clock pulse A situation occurs in which the fluctuation in tj2 does not return to the original normal state until the next clock pulse. In this case, the voltage fluctuation caused by a certain clock pulse overlaps with the fluctuation of the power supply voltage caused by the next clock pulse, and then overlaps with the fluctuation of the power supply voltage caused by the next clock pulse, and so on, the power supply voltage changes in a bad direction one after another. It may change. As described above, the above conventional technology does not take into consideration the case where high-speed circuit elements are used and driven by high-speed clock pulses, and in the case of high-speed operation, it is difficult to prevent malfunction due to overlapping fluctuations in the electric voltage. There was a problem that it was not sufficient.

An object of the present invention is to reduce fluctuations in power supply voltage as much as possible when high-speed circuit elements are used to simultaneously drive multi-stage shift registers with high-speed clock pulses.

[Means for Solving the Problems] In order to achieve the above object, the present invention alternately assigns positive logic and negative logic in both the serial direction and the parallel direction of a multi-stage shift register with m bits per column and n columns. This is what I decided to add.

[For production]

All n-bit data input in parallel is “High”
” to “Low”, the output of about half of the circuit elements changes from “High” to 11 Low u
The output of about half of the remaining circuit elements changes to re Lo
, ,.

The number of outputs of the circuit elements and M
The number of circuit elements changing from "Low'" to "High" is equal to Z. Therefore, the influence on the power supply becomes ZERO, there is no fluctuation in the power supply voltage, and one circuit does not malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, m is used in the data shift direction by the clock pulse CLK.
+1 line, input data D (., ~D, n.

Each even number of n+1 columns of numbers, total (m+1)X
This figure shows a shift register circuit in which (n+1) flip-flops are arranged in a matrix. 2N, the first row of flip-flops F Oo+ Flot
”'r FnO and the flip-flop F Om l F 1 m +..., F
The flip-flop F is an even number of bits. . .

FZ[l! ”'l Fn-10 and F Oml FZ
M? ``' t F n-1,a takes the output from the Q terminal where the input data is inverted and output, and is an odd bit flip-flop F1o + F 30 + ``' l
F nO and Flml F311? ”'l Fnll
takes the output from the Q terminal, where the input data is output as is. In addition, the flip-flops in each row from the second row to the m-th row, which is the row before the final row, take out the output from the output terminal Q where the input data is inverted and output, and input the output to the next stage flip-flop. Connect to the terminal.

Now, the first row of flip-flops F0゜tFott・
- When focusing on IPOIm, input data D,. , if "L O, It" is input continuously as "L O, It", "Low" and "High" (hereinafter tt
The difference between the numbers (abbreviated as L##HII) is 1. The data handled in image processing is relatively "L" and It HI.
t is consecutive. “After L 71 is input continuously, I
If tH# is input, flip-flop F. . +
FO1+"'rFOm output Q no r Qox +
"' + Qo, Il change as shown in Figure 3. At this time, from it L pt to # HJ+ or I H
The number of flip-flops that change from II to L''' is always one. All the flip-flops in the odd-numbered rows perform this same operation at the same time. For the flip-flops in the even-numbered rows, the input data is When II L II is input, the difference between tt L tp and 41 HII is 3
However, if 11 H11 is input continuously, “
L” to “H'' or tt Hn to 11 L n
The number of flip-flops that change to is always one as in the odd columns.

Next, when looking at the row direction, input data D,. .

~D. , changes from “L II to tt Hrp”, the flip-flops F0° Fl, , in the first row
:...The output of FnO changes as shown in FIG. That is, even-column flip-flops p', , F,. ,...
・Fn-z. The output Q [101Qzo 9 ”'
l Qn-1° changes from 'H' to l(L++, odd-numbered column flip-flop F'to t F2O1'''
t F nO output Q 10 t Q30 t...
Qn changes from 'L' to 'H'. Here, since the number of even and odd columns is the same, in the first row, the difference between lj H71 and 11 L ++ before and after the change is the same, and the voltage change due to the change in current value is There is no change.

Input data D for input of next clock pulse CLK
,. , ~D [if nl remains zi HIt, then the first
Output data row processing. rQz. , ... * Even if Qno does not change and changes to 11 L ++, the above #
The difference between It HII and LL L ++ does not change except that H++ and "L ++ are reversed. At this time, the flip-prop FOIP Fil+ "'9 Fnz in the second row
Since the output of Q ott Qxxt "'Qo1" is the inverted data of the input data, the output which was 11 HH changes to "ztL", and the output which was "L II" changes to "H11", and the output which was "L II" changes to "H11". Similarly to the first line, “HPI” and “L”
The same process is repeated according to the input of the clock pulse CLK, but the difference between "H" and "L11" does not change rapidly.

In the embodiment shown in FIG. 1, the E
Although the CL-IC is taken as an example, even if it does not have a Q terminal, the same operation can be performed by using an inverter or the like between flip-flops. Also, data D, which is input in the first line. .

~D(n) have the same polarity, but data D in odd rows
t1. The same operation can be performed by inverting +o(31?++, I)(n) using an inverter or the like and inputting the same as the flip-flops in the first and even rows.

Also, if you create a matrix with an even number of flip-flops and an even number of flip-flops, if you can obtain the expected output,
This is not the case.

Furthermore, although ECL-IC is taken as an example, for example, ECL-IC is used as an example.
The same can be said for CL-LSI and the like.

According to this embodiment, taking the flip-flop F1□ of FIG. 1 as an example, the output data of the output terminal Q of F12 is
□ is a negative logic, and by assigning positive logic and negative logic so that it becomes a positive logic with the output element of the Fxt in the previous stage, the input data can be changed from "H++" to "L +1" or "L" at the same time.
Even if the shift register changes from 11 HII to iz L ++, there is almost no difference between 11 HII and iz L ++ as a whole.
Voltage fluctuations due to sudden changes in current consumption can be prevented.

〔Effect of the invention〕

As explained above, in the present invention, all n-bit data input in parallel changes from "High" to "Lotz".
Even if there is a sudden change from 1 (Lo) to ``High'', approximately half of the circuit elements that make up the shift register and the other half of the circuit elements work to cancel out the fluctuations in the power supply voltage. This eliminates fluctuations in the power supply voltage for the entire circuit, which has the effect of eliminating malfunctions of the circuit due to fluctuations in the power supply voltage.It is particularly effective when driving a large number of shift registers at the same time in high-speed image processing devices, etc. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a state diagram of the input/output data of the first column in the shift register circuit of FIG. 1, and FIG. FIG. 4 is a transition diagram of input/output data in the first column. FIG. 4 is a transition diagram of data in the first row in the shift register circuit of FIG. D. , ~Dcn, ... input data, CLK ... clock pulse, F OO"" F 11111 ... flip-flop, Qo. ~Q111...Output data. Causes Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a shift register circuit that has an n-column shift register consisting of m bits per column, and in which parallel n-bit data is input to each column and shifted by a clock, either the odd bits or even bits of each column 1. A shift register circuit characterized in that one of the bits is assigned to positive logic and the other is assigned to negative logic, and one of the same bits in odd and even columns is assigned to positive logic and the other to negative logic. (2) The shift register circuit according to claim 1, wherein the first stage bit and the last stage bit of each column, and the first stage column and the last stage column are assigned to any logic of positive logic or negative logic.