JPH02143374A - Product sum arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain the sum of products at a speed higher than that in a case when up to the products are obtained using a multiplier by keeping the part of a multiplication in the shapes of a partial sum and a partial carry and repeating the multiplication without obtaining up to the products. CONSTITUTION:The partial sum and the partial carry to the obtained before a product is obtained are used for an operation instead of the product, and the partial sum and the partial carry of the preceding operation cycle are to be added in a circuit to generate the partial sum and the partial carry. Here, since the partial sum and the partial carry can be obtained in the middle of a process to generate the product, the circuit to generate the partial sum and the partial carry can execute its operation at the speed higher than that of the multiplier to obtain the product. Further, since the partial sum and the partial carry of the preceding operation cycle are added in the generating circuit in each operation cycle, processing for obtaining each sum to be executed whenever the product is obtained becomes unnecessary, and a high-speed operation can be attained. Thus, the sum of the products can be obtained at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic device that rapidly executes a sum-of-products operation used in various types of calculations, including signal processing and image processing.

[Conventional technology]

Figure 2 shows, for example, S. Tsujimichi et al.
e+ct-Generation 32-old t V
LSI Signal Processor
(rcAssP86 PROCEEDrNGS) is a diagram showing the circuit configuration of a conventional product-sum operation device.
In the figure, (1) is the 2nd step of calculating the product in the above product-sum operation.
Base multiplier, (2) is a binary addition that calculates the sum among the above product-sum operations! , +31 is the register that supplies the multiplicand to the binary multiplication gain (1), (4) is the register that supplies the multiplier to the binary multiplier (1), and (5) is the register that supplies the product from the binary multiplier (1). a register that inputs and also supplies an addend to the binary adder (2), (
6) A register for inputting the sum from the binary adder (2) and further supplying the summand to the binary adder (2), and (7) for clearing the contents of the summand register (6) to zero. is the input selector for

Next, the operation of the conventional product-sum calculating device shown in FIG. 2 will be described in the case where a product-sum Z as expressed by the following formula is calculated.

In the conventional product-sum arithmetic device, first, a binary number corresponding to x and a binary number corresponding to Y are input to a binary multiplier (1) through registers (3) and (4) to calculate the product. Next, the above tank outputted from the binary multiplier (1) at this time is input to the binary adder [2] through the register (5), and is added to the contents of the register (6) cleared to zero by the input selector (force). Input the sum into register (6).At the same time, the binary multiplier (11) multiplies the binary number corresponding to the next X and the binary number corresponding to Y2, and inputs the product into register (5). .Next, the contents of register (6) and register (5) at the time of B are added to the binary adder (2).
and input the sum into register (6).

By the operation up to this point, register (6) is set to X, Y□10X.
,Y.

The final sum of products Z is obtained by repeating the above operation until n=n. In other words, in the conventional product-sum calculation device, the product-sum is calculated by repeating the above operations.

[Problem to be solved by the invention]

Since the conventional product-sum calculation device is configured as described above, the product is calculated for each calculation cycle.

Each time a product is calculated, it is necessary to calculate the sum with the previously calculated sum of products, and the problem that must be solved is that the sum of products operation cannot be performed at high speed.

This invention was made in order to solve the above-mentioned problems, and it is possible to calculate the sum of products without requiring the sum every time the product is calculated, and it is also possible to calculate the sum of products using the binary multiplier described above. The object of the present invention is to obtain a product-sum operation device that can operate faster than an arithmetic unit.

[Top means to solve problems]

The product-sum calculation device according to the present invention uses partial sums and partial carries obtained before calculating products in calculations instead of products, and uses the partial sums and partial carries of the previous calculation cycle in a circuit that generates the partial sums and partial carries. and partial carries can be added.

[For production]

The circuit that generates partial sums and partial carries in this invention can operate faster than a multiplier that calculates products because the partial sums and partial carries are determined during the process of generating products, and each Since in an arithmetic cycle, the generating circuit adds the partial sum and partial carry of the previous arithmetic cycle, there is no need to perform a process of calculating a sum each time a product is calculated, and high-speed calculation becomes possible.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (3) is the register that sets the multiplicand, (
4) is a register that sets a multiplier, (+1) is a register that sets a partial sum, ■ is a register that sets a partial carry, Q3) is a partial product generation circuit, and (2) is a tree circuit that uses the carry-save method. , (2) is a binary adder to convert the partial sum and partial carry into a sum form.

(19 is a register that receives the output of the binary adder (2), (
7) is an input selector for clearing the contents of the partial sum register 01) and the partial carry register (01) to zero.

Next, the operation of the sum-of-products calculation device according to an embodiment of the present invention will be described in the case where the sum-of-products Z as expressed by the above equation is calculated in the same way as in the conventional example.

In the product-sum calculation device of the embodiment, first, 2 corresponding to the above equation x1 is calculated.
The binary number corresponding to the base number and Y is input to the partial product generation circuit () () through register (3) and register (4) to generate a partial product group.Then, the generated partial product group and the input selector ( 7) The contents of register θ1) and register ■ cleared to zero by tree circuit (2)
The above tree times m ()4) are input as input data. The tree circuit (2) employs a carry-save method, and outputs the input data in the form of a partial sum and a partial carry, which are intermediate results before being converted into a product form. The above partial sum and the above partial carry output from the tree circuit (2) at the time of B are respectively stored in registers (11).
and input into register ■. Then register (3)
The binary number corresponding to the next xi and the binary number corresponding to Y2 are passed through the register (4), and the contents of the register 01 (in which the above partial sum and the above partial carry are set) and register 13) and Tory times #! (2), and set the new partial sum and partial carry in register 01〉 and register (Φ) respectively.By the operation so far, register 01) and register , can be found in the form of a partial sum and a partial carry, and by repeating the above operation up to -n, the final sum of products Z can be found in the form of a final partial sum and a partial carry. Next, in order to convert the form of the partial sum and partial carry into the final product-sum form, the partial sum and partial carry of Z are input to the binary adder (2) through register 01) and register Register (set to 19).

In other words, in the arithmetic device for calculating the sum of products according to an embodiment of the present invention, the sum of products is obtained in the form of a partial sum and a partial carry by repeating the above operation, and finally, the binary adder (2) is used only once to finalize the sum of products. This means that we have obtained the sum of products.

Here, the operating speeds of the embodiment and the conventional example will be compared.

The part of the product-sum operation that calculates the product is a process from adding partial products to generating partial sums and partial carries, whose operating speed depends only on the bit width of the multiplier register (4).
(hereinafter referred to as process A), and the process from addition of the partial sum and partial carry to generation of the product (similarly,
Divided into process B). In the conventional example, the product is generated by the above binary multiplier (1), and the above process A and the above process B are repeatedly executed in each calculation cycle, so the @production speed is determined by the above multiplicand register (3). and the above multiplier register (4
) depends on the bit width of both. On the other hand, in the embodiment, only the above-mentioned process A in which the operating speed depends on the bit width of the multiplier register (4) is repeatedly executed in each calculation cycle, and only once in the last calculation cycle, the operating speed depends on the bit width of the multiplicand. The configuration is such that the above process B is executed depending on the bit width of register (3). In other words, while the operating speed of each arithmetic cycle in the conventional example depends on the bit width of each multiplicand and multiplier, the operating speed of each arithmetic cycle in the embodiment depends on the bit width of the multiplicand in the last arithmetic cycle. depends on
Since the remaining arithmetic cycles depend only on the bit width of the multiplier, the embodiment is better because it does not need to execute process B, whose operating speed depends on the bit width of the multiplicand register (3), for each arithmetic cycle. It enables high-speed product-sum operations.

The above will be explained using FIGS. 3 and 4. 3rd rI! J and FIG. 4 are time charts showing the execution operation of the product-sum operation in the conventional example and the embodiment, respectively. In FIG. 1, (D is the part that executes the above process A, and (r/) is the The part that executes process B, (■ is the addition process that calculates the sum of the product-sum operations in the conventional example (hereinafter referred to as
(referred to as process C). In addition.

3 and 4 assume that the operating speeds of process A and process B are the same because the multiplicand and the multiplier are usually considered to have the same bit width, and the number of terms in the product-sum operation is nJ.
T! It is assumed that n=6. Processes A and B for each calculation cycle
, C are the process people i, Bi, and C, respectively. In Fig. 3, the process CI is the process of adding the product obtained by executing the process and the process B] and the initial value 0, The operating speed is substantially the same as in process B. Also, process C2 is for process and product from process B2 and process C
The result of I becomes an addition-plus process, and the same applies hereafter. However, as mentioned in the explanation of the conventional example, processes A, B, and C operate in parallel, so in this case, the last one appears in the actual calculation cycle. Only process C6 is required. In FIG. 4, as in the above embodiment, only process A is repeated one time t! Step B is executed. ” From the assumption in item 1, it can be said that while the conventional example executes the above process A and the above process B once, the embodiment can execute the above process A twice, and the example shown in FIGS. From a comparison of the figures, it can be seen that, except for the last calculation cycle 7 of the conventional example and the last calculation cycle 4 of the embodiment, the embodiment can perform product-sum calculations twice as fast as the conventional example. The bit width of the multiplicand register (3) becomes larger as the multiplicand becomes wider (as the operation speed of one calculation cycle of the above process A becomes relatively faster compared to the above process). The higher the number of repetitions, that is, the larger the number of terms n in the product-sum 5ii arithmetic, the faster the speed is achieved by using the embodiment.

In the above embodiment, one register was provided to receive the output of the binary adder (2), but the tree time is
A register (11
) or may also be used as a register (to) that receives the output of a partial carry.

In addition, in the above embodiment, register 01) and register
Although an input selector (7) is provided to give an initial value O to the input selector (7), the input selector (7) does not need to be provided as long as the circuit can clear the register (11) and the register (2) to zero.

〔Effect of the invention〕

As described above, according to the present invention, instead of calculating the sum of products by repeating multiplication and addition, it is now possible to perform only one addition by repeating multiplication.
! Find the I sum.The arithmetic device can be easily implemented, and since the 1 multiplication part is stopped at the form of partial sum and partial carry and is repeated without finding the product, use a square multiplier to find the product. This has the effect of obtaining the sum of products faster than in the case of

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a product-sum calculation device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional product-sum calculation device, and FIG. 3 is a conventional product-sum calculation execution operation. The time of
Chart Figure 4 is a time chart diagram of the execution operation of the product-sum operation in the embodiment. (2) is a binary adder, (I+) is a partial sum register, (
Φ is a partial carry register, 03) is a partial product generation circuit, (
2) is tri-age old. Note that in the two figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 32 Figure 15 Output register

Claims (1)

[Claims] A product-sum calculation device that performs a product-sum calculation by repeating calculation cycles includes first and second registers that store intermediate results of calculations, a circuit that generates a partial product group from input multiplicands and multipliers, and a circuit that generates a partial product group from input multiplicands and multipliers; The product generating circuit and the first and second
The partial product group is connected to the register of , and the contents of the first and second registers are added to generate a partial sum and a partial carry, and the partial sum and partial carry are added to the first and second registers to perform a new operation. A tree circuit employing a carry-save method that outputs an intermediate result of In each operation cycle, the partial product generation circuit and the tree circuit generate products in the form of partial sums and partial carries, and at the same time, the sum of products up to the previous operation cycle is partially calculated. A product-sum calculation device characterized in that a product-sum calculation is realized by inputting the sum and partial carry as they are to the tree circuit.