JPH02141995A - High-speed peak holding circuit - Google Patents

Abstract

PURPOSE:To increase the speed of a response characteristic and to obtain a satisfactory holding characteristic by providing first and second peak holding circuits to respectively execute peak holding at mutually different response speeds and selectively outputting a higher or lower output signal out of the output signals of these first and second peak holding circuits. CONSTITUTION:An input signal for the whole of the title circuit is inputted to the first and second peak holding circuits 11 and 12, and the outputs from these circuits 11 and 12 are inputted to the third peak holding circuit 13 and after that outputted from the whole of the circuit. Here, the circuit 11 is made into a circuit having a high response speed, the response speed of the circuit 12 is made lower compared with that of the circuit 11, and the circuit 13 is operated as a level selecting circuit to operate so as to selectively output the lower-level output out of the outputs of the circuits 11 and 12. Thus, the circuit can be the holding circuit appropriate for an application to highly speedily detect input signal amplitude like an ATC circuit in an optical receiver.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to peak hold circuits. More specifically, the present invention relates to the configuration of a novel peak hold circuit that responds quickly to input signals and has excellent peak hold characteristics.

2. Description of the Related Art Conventionally, as a peak hold circuit that operates at high speed, a current switching circuit as described below is known.

FIG. 2 is a circuit diagram showing a typical configuration example of a conventional peak hold circuit.

As shown in Figure 2, this circuit supplies a current to a comparator 1 whose non-inverting input receives an input signal, a transistor Q whose base is connected to the output of comparator 1, and a collector of the transistor Q. A capacitor C is connected to the connection point between the transistor Q and the current source I and has one end grounded.

The operation of this circuit is as follows.

That is, when the input signal is lower than a predetermined peak hold output level, the output of the comparator becomes high level. Therefore, since the transistor Q becomes conductive, the electric charge stored in the capacitor C is discharged, and the peak hold level output from the circuit decreases, thus ensuring that the negative peak of the input signal is always held. Ru.

Problems to be Solved by the Invention The conventional peak hold circuit as described above determines its output level by charging and discharging the capacitor C. That is, in the conventional peak hold circuit, the following equation holds true.

Therefore, if such a circuit configuration is to be adapted to high-speed operation, it is understood from equation (1) that the capacitance of the capacitor C needs to be reduced, assuming that the amount of current discharged by the transistor Q is constant.

However, if we reduce the capacitance of capacitor C and increase the charging/discharging rate, the peak hold time also decreases.
Since the length becomes shorter according to equation (1), the holding characteristic deteriorates.

That is, with the conventional peak hold circuit configuration, it is difficult to increase only the operating speed and maintain good holding characteristics. SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a novel peak hold circuit that operates at high speed and has excellent holding characteristics.

Means for solving the problem, that is, according to the present invention, is a peak hold circuit for extracting the peak level of an input signal.
First and second peak hold circuits that perform peak hold at mutually different response speeds, and selection of selectively outputting either the higher or the lower of the output signals of the first and second peak hold circuits. A peak hold circuit is provided.

Further, according to a preferred aspect of the present invention, a third peak hold circuit can be used as the selection circuit.

The main feature of the peak hold circuit according to the present invention is that it uses two peak hold circuits with different response speeds and is configured to selectively output preferable characteristics of each peak hold circuit. It is said that

That is, the peak hold circuit according to the present invention has two peak hold circuits having different response speeds to an input signal.
Each performs peak hold operation. Here, as described above, a high-speed peak hold circuit has a high-speed response, but the time it takes to hold a detected peak is short. On the other hand, a low-speed peak hold circuit has a slow response speed but holds an extracted peak for a long time.

Therefore, by always outputting the lower (higher) level signal from the outputs of the two peak hold circuits, it is possible to achieve both high-speed response and good holding characteristics.

Here, as a circuit that selects and outputs the lower level (higher one) from the outputs of the two peak hold circuits, for example, a third peak hold circuit can be applied, as will be specifically described later. .

That is, the third peak hold circuit inputted with the outputs of the two peak hold circuits having different response speeds first extracts the peak of the input signal at high speed in response to the output of the high speed peak hold circuit, and then extracts the peak of the input signal at high speed. It operates to hold the peak in response to the output of the slow peak hold circuit.

Thus, the peak hold circuit according to the present invention achieves both high-speed response and good holding characteristics.

It should be noted that for each of the peak hold circuits for configuring the peak hold circuit according to the present invention as described above, a conventional peak hold circuit as shown in FIG. 2, for example, can be used.

The present invention will be described in more detail below with reference to the drawings, but the following disclosure is only one example of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram showing the basic configuration of a peak hold circuit according to the present invention.

This circuit includes first and second peak hold circuits 11 and 12 that receive input signals that apply to the entire circuit;
It mainly consists of a third peak hold circuit 13 which receives both outputs of this peak hold circuit 1112 manually, and the output of the third peak hold circuit 13 is the output of the entire circuit.

Here, the first peak hold circuit 11 is a peak hold circuit with a fast response speed, and the second peak hold circuit 12 is a peak hold circuit with a slow response speed at least compared to the first peak hold circuit 11. .

Further, as will be described later, the third peak hold circuit 13 is a level selector that operates to selectively output the output of the lower level among the outputs of the first $ and second peak hold IL 12. used as a circuit.

Note that the first, second and third peak hold circuits 11.
12 and 13 are peak hold circuits each having a conventional configuration as shown in FIG. 2, and differ only in the setting of response speed.

3(a) and 3) are diagrams for explaining the operation of the peak hold circuit according to the present invention shown in FIG.
Figure (a) is a waveform diagram focusing particularly on the operations of the first and second peak hold circuits 11 and 12.

That is, as shown in FIG. 3, the moment the input to this circuit changes from a no-signal state to a signal input state, the peak hold circuit 11 responds quickly and quickly reduces the output level; In response to this, the output level begins to rise again. On the other hand, the second peak hold circuit 12 maintains a low output level for a long period of time, although its response is slow and the speed at which the output level decreases is slow.

FIG. 3(b) is a waveform diagram focusing on the operation of the third peak hold circuit 13 in the circuit shown in FIG.

As mentioned above, the third peak hold circuit 13
The lower output level of the output signals of the second peak hold circuits 11 and 12 is selectively outputted, so the output level varies depending on the continuation of the input signal, as shown in Figure 3 et al. continue to maintain a low level.

In this way, the peak hold circuit according to the present invention shown in FIG. 1 simultaneously achieves high-speed response and good holding characteristics.

As described in detail, the peak hold circuit according to the present invention can simultaneously achieve high-speed response characteristics and good holding characteristics.

Therefore, for example, in the information and communication field, ATC (Automatic Threshold) in optical receivers is
It is effective when used in applications where it is necessary to detect input signal amplitude at high speed, such as in d Control circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a peak hold circuit according to the present invention, FIG. 2 is a circuit diagram showing a typical configuration of a conventional peak hold circuit, and FIG. 1A and 2B are waveform diagrams for explaining the operation of the peak hold circuit according to the present invention shown in FIG. 1. FIG. [Main reference numbers and reference symbols] 1...Comparator, 11...First peak hold circuit, 12...Second peak hold circuit, C...Capacitor, ■...Current source, Q ...transistor,

Claims (2)

[Claims] (1) A peak hold circuit for extracting the peak level of an input signal, comprising first and second peak hold circuits that perform peak hold on the input signal at mutually different response speeds; 1. A peak hold circuit comprising: a selection circuit that selectively outputs either the higher or the lower of the output signals of the two peak hold circuits. (2) The peak hold circuit according to claim 1, wherein the selection circuit is a third peak hold circuit.