JPH02141129A - Echo canceller by step type tap coefficient - Google Patents

Abstract

PURPOSE:To attain large scale integration by digital processing and to save circuit scale by adopting a step type for a tap coefficient of an echo canceller. CONSTITUTION:An impulse response value obtained for several kinds of transmission lines is shored in a nonvolatile memory 2 stepwise as a tap coefficient. While a 2-wire side reception signal is not applied to a 2-wire side input output terminal 7, an output of an adder 10 is integrated by an integration circuit 14 to obtain a mean value and an address of the nonvolatile memory 2 minimizing an output of the integration circuit 14 is outputted from an address control circuit 15. Thus, an optimum tap coefficient is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to impedance correction of a hybrid circuit using an analog two-wire transmission system, and particularly relates to an echo canceller using a stepped tap coefficient.

[Conventional technology]

Conventionally, the impedance of these 11 analog two-way transmission hybrid circuits has been corrected by using an analog circuit called a balancing network consisting of resistors and capacitors, or by calculating tap coefficients using an adaptive algorithm. There are two methods of realizing this using a digital circuit called a successive response knee canceller that attenuates the signal.

In the former method using an analog circuit, 41!
The wraparound signal of the I side transmission signal is generated when the balance of the hybrid circuit is disrupted due to the impedance of the two-wire side transmission line, so several types of resistors and capacitors are prepared, and a combination of these resistors and a capacitor is used. Manual selection corrects the impedance of the hybrid circuit and reduces cross-talk signals.

On the other hand, the latter method using a sequentially adaptive echo canceller uses a transversal filter that generates pseudo-echoes with variable tap coefficients, and successively modifies the tap coefficients using residual echo components after subtracting the pseudo-echoes to find the optimal tap. It consists of an adaptive algorithm section that calculates coefficients.

[Problem to be solved by the invention]

The problem with the impedance correction of the conventional analog two-wire transmission hybrid circuit described above is that the former method is difficult to integrate into an LSI because it is an analog circuit, and correction of the ti impedance can only be performed manually. In addition, in the latter method, tap coefficients are automatically calculated, but the adaptive algorithm is complex, so there is a problem that the circuit scale is significantly off.

[t1! Means for Solving the Problem] The echo canceller using step-type tap coefficients of the present invention approximates the impulse response of a transmission-side wrap-around signal caused by an impedance shift in impedance correction of a hybrid circuit of an analog two-wire transmission system. a memory that stores tap coefficients in a stepwise manner, and an arithmetic circuit that configures a transversal filter that generates a pseudo echo using the digitized 4-wire side transmission signal and the tap coefficients output from the memory. , an adder for subtracting the pseudo echo generated by the arithmetic circuit I) from the transmitting side wrap-around signal, and an integrating circuit for integrating the residual echo component after the pseudo echo is subtracted by the adder. , the memory address control circuit for selecting the optimum tap that minimizes the integration result of the residual echo component obtained by the integrating circuit.

[For production]

In the present invention, the impulse response values obtained for several types of transmission lines are stored in a non-volatile memory in steps as tap coefficients, and the 2-line side received signal is applied to the 2-line side human output terminal. The output of the adder is integrated by an integrating circuit in the idle state to obtain the average value, and the address control circuit outputs the address of the non-volatile memory where the output of the integrating circuit is at least 7Th, thereby determining the optimal tag coefficient. Select.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, 1 is the 4-wire side input terminal to which the 4-wire side transmission signal is applied, and 2 is the tap coefficient that holds the tap coefficient in steps for approximating the impulse response of the transmission side wrap-around signal caused by impedance deviation. 3 is an A/D converter that converts analog transmission No. 1 into a digital signal; 4 is a digitized 94-line side transmission signal and tap coefficients output from nonvolatile memory 2; This is an arithmetic circuit that constitutes a transversal filter for generating a pseudo echo, and the arithmetic circuit 4 is an A/D
Consists of a shift register 4-1 synchronized with the sampling phase of the converter 3, a multiplier 4-2 that multiplies the contents of this shift register 4-1 by a tap coefficient output from the nonvolatile memory 2, and an adder 4-3. has been done.

5 is a driver on the transmitting side, 6 is a hybrid circuit that performs 2-wire to 4m conversion, 7 is an input/output terminal on the 2-wire side for transmitting and receiving signals on the 2-wire side, 8 is a receiver on the receiving side, and 9 is a 4-wire side analog receiving signal. A/D converter for converting into a digital signal, 10
11 is an adder for subtracting the pseudo echo generated by the performance circuit 4 from the transmission-side wraparound signal; 11 is a D/A converter that converts the digital signal after attenuating the wraparound signal into an analog signal; and 12 is a 4 The 4-wire side output terminal 13 of the line side received signal is a tap coefficient selection section, and this tap coefficient selection section 13 is connected to an integrating circuit 14 for integrating the residual echo component after the pseudo echo is subtracted by the adder 10. It is constituted by an address control circuit 15 of the nonvolatile memory 2 for selecting the optimal table tap that minimizes the integration result of the residual echo component obtained by the integration circuit 14.

Next, the operation of the embodiment shown in this figure will be explained.

First, the transmission side wrap-around signal passes through the hybrid circuit 6 and wraps around to the receiving side depending on the impedance of the 2-wire transmission line connected to the 2-wire side input/output terminal 7, so the wrap-around signal There is a one-to-one relationship between the level and waveform of and the impedance characteristics of the two-wire transmission line.

Therefore, since the impulse response of the input signal can be easily calculated by computer simulation, the impulse response values obtained for several types of transmission paths are stored in the nonvolatile memory 2 as tap coefficients in steps. I'll keep it.

Next, the residual echo component after subtracting the pseudo echo is:
The larger the amount of attenuation of the wrap-around signal, the smaller it becomes.
A non-volatile memory in which the output of the adder 10 is integrated by the integrating circuit 14 and the average value is taken when the 2-wire side received signal is not applied to the 2-wire side input/output terminal 7, and the output of the integrating circuit 14 is minimized. By outputting address No. 2 from the address control circuit 15, the optimum tap coefficient can be selected.

Furthermore, if the tap coefficient selection section 13 is provided outside the device, it is possible to manually select the optimum tap coefficient, similar to the balancing network setting means using an analog circuit. Further, if the tap coefficient selection section 13 is provided inside the device, an adaptive echo canceller in which the tap coefficients change stepwise can be obtained. In this case, the difference from the prior art sequential adaptive echo canceller described above is that the sequential adaptive echo canceller had to provide an adaptive algorithm section independently for each line, whereas the present invention's step In the type echo canceller, the tap coefficient selection unit 13 can be used in common for #9 type lines by simply providing a memory that holds the address of the optimum tap coefficient for each line independently. .

〔Effect of the invention〕

As described above, the present invention has the effect of reducing the LSI and circuit scale through digital processing by making the tap coefficients of the echo canceller step type.

That is, it can be mass-produced at low cost.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 2...Non-volatile memory (memory), 3...A/
D converter, 4...Arithmetic circuit, 6...Hybrid circuit, 10...Adder, 13...Tap coefficient selection section, 14...Integrator circuit, 15...・Address control circuit. For patents) Section 6 NEC Corporation Miyagi NEC Corporation

Claims (1)

[Claims] When correcting the impedance of a hybrid circuit using an analog two-wire transmission system, a memory that stores tap coefficients in steps to approximate the impulse response of a wrap-around signal on the transmitting side caused by an impedance shift, and a digital four-wire side transmitter are used. an arithmetic circuit constituting a transversal filter for generating a pseudo echo using a signal and a tap coefficient output from the memory; and an arithmetic circuit for subtracting the pseudo echo generated by the arithmetic circuit from the transmission side wrap-around signal. An adder, an integrating circuit for integrating the residual echo component after subtracting the pseudo echo by the adder, and an optimal integration circuit that minimizes the integration result of the residual echo component obtained by the integrating circuit. An echo canceller using a step type tap coefficient, comprising an address control circuit for the memory for selecting a tap.