JPH02141048A - Digital transmission equipment, digital receiver, and digital communication equipment - Google Patents

Abstract

PURPOSE:To obtain the title digital transmission equipment necessary for executing accurate digital communication by executing sum conversion based on time delay equivalent to the double of one bit length of a digital data signal to be transmitted. CONSTITUTION:The digital transmitter is composed of a sum converter 3 connected so as to receive a digital S1 to be transmitted, a phase modular 33 connected to the output of the sum converter 3, a high-frequency amplifier 35 connected to the output of the phase modulator 33, and a transmitting antenna 36 connected to the output of the high-frequency amplifier 35. Further, the bit string of the digital data signal to be transmitted is sum-converted by the sum converter 3 based on the time delay equivalent to the double of one bit length, and the converted signal is modulated by the modulator 33 and after that transmitted by the transmitting antenna 36. Thus, the digital transmission equipment necessary for executing the accurate digital communication can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal transmission, reception, and communication device, and particularly to a transmission, reception, and communication device that utilizes summation transform and delay detection.

[Prior Art and Problems to be Solved by the Invention] In conventional digital communication systems using phase modulation and demodulation, a receiving system using delayed detection is widely used on the receiving side. This means that the digital data to be sent is subjected to 1-bit summation conversion on the sending side, and then sent.
This method obtains the transmitted digital data signal by performing differential detection on the receiving side, that is, by detecting the phase difference between the current signal and the signal one bit before.

FIG. 4 is a characteristic diagram showing delayed detection characteristics according to a conventional reception method. In FIG. 4, a solid line 41 indicates correct differential detection characteristics, while a dotted line 42 indicates incorrect differential detection characteristics. Note that the vertical axis indicates the detection level, and the horizontal axis indicates the phase.

For example, when detecting a binary phase shift keying (BPSK) modulated wave on the receiving side, when correct delay detection characteristics are obtained, the signal "0" is demodulated by detecting a phase difference of 0 (point A), Further, the signal "1" is demodulated by detecting the phase difference π (point B).However, due to factors such as carrier wave frequency fluctuations and delay time variations, an incorrect delay detection characteristic 42 may be obtained. In that case, as shown in Figure 4, the relationship between the detection level, that is, the demodulated signal "0" and "1°" and the phase is completely reversed, making it impossible to correctly demodulate the transmitted signal. The problem was that it couldn't be done.

In order to solve the above-mentioned problems, the invention of claim (1) aims to provide a digital transmission device necessary for performing accurate digital communication. Furthermore, an object of the invention as claimed in claim (2) is to provide a digital receiving device necessary for performing accurate digital communication. Furthermore, the invention of claim (3) aims to provide a digital communication device necessary for performing accurate digital communication.

[Means for Solving the Problem] A digital transmitter according to the invention of claim (1) receives a digital data signal to be transmitted consisting of a bit string and performs summation conversion based on a time delay twice the length of one bit. the summation conversion means; modulation means for modulating the output signal from the summation conversion means for transmission; and transmission means for transmitting the signal modulated by the modulation means.

The digital receiving device according to the invention of claim (2) includes receiving means for receiving a signal including a digital data signal consisting of a bit string from the outside, and a receiving means based on a time delay of one bit length in response to the received signal. The method includes a first delay detection means that performs delay detection, and a second delay detection means that further performs delay detection based on a time delay of one bit length in response to the output signal from the first delay detection means. .

The digital communication device according to the invention of claim (3) includes: a summation conversion means for receiving a digital data signal to be transmitted consisting of a bit string and performing summation conversion based on a time delay twice the length of one bit; modulating means for modulating the output signal of the minute converting means for transmission; transmitting means for transmitting the modulated signal; receiving means for receiving the transmitted signal; a first differential detection means for performing differential detection based on a time delay of bit length; and a first differential detection means for performing differential detection based on a time delay of one bit length in response to the output signal from the first differential detection means. 2 delay detection means.

[Operation] In the invention as claimed in claim (1), the bit string of the digital data signal to be transmitted is subjected to summation conversion by the summation conversion means based on a time delay twice the length of one bit. The converted signal is modulated by the modulation means and then transmitted by the transmission means.

In the invention of claim (2), after the receiving means receives the digital data signal from the outside, the first and second delay detection means sequentially perform the delay detection operation. Each differential detection operation is performed based on a time delay of one bit length making up the bit string of the received signal.

In the invention of claim (3), on the transmitting side, the digital data signal to be transmitted is subjected to summation conversion by the summation conversion means based on a time delay twice the length of one bit. The converted signal is modulated by the modulation means and then transmitted by the transmission means.

On the receiving side, the signal transmitted by the receiving means is received. The received signal is sequentially subjected to a delay detection operation by first and second delay detection means. Each differential detection operation is performed based on a time delay of one bit length constituting the bit string. As a result, even if the delayed detection characteristics are reversed due to carrier wave frequency fluctuations, delay time variations, etc., the transmitted signal is correctly received.

[Embodiment of the Invention] FIG. 2 is a block diagram of a digital transmitting device showing an embodiment of the invention of claim (1). Referring to FIG. 2, this digital transmitter includes a summing converter 3 connected to receive a digital signal S1 to be transmitted, and a phase modulator 33 connected to the output of the summing converter 3. , a high frequency amplifier 35 connected to the output of the phase modulator 33, and a high frequency amplifier 3
and a transmitting antenna 36 connected to the output of 5. The summing converter 3 has two outputs, an exclusive OR (hereinafter referred to as EXOR) gate 31 connected to receive the digital signal S1 to be transmitted, and an output of the EXOR gate 31. and a D flip-flop 32 for a 2-bit delay connected between the other input. Phase modulator 33 is connected to receive a signal from oscillator 34 .

FIG. 2 is a block diagram of a digital receiving device showing an embodiment of the invention of claim (2). Referring to FIG. 1, this digital receiving device includes a receiving antenna 11, a filter 12 for removing unnecessary signal components from a received signal,
a high frequency amplifier 13 connected to the output of the filter 12;
a mixer 14 connected to the output of the amplifier 13 for converting to an intermediate frequency; a filter 16 connected to the output of the mixer 14 for removing high frequency components; and a comparator 17 connected to the output of the filter 16. Comparator 1
7, a filter 21 connected to the output of the delay detector 1 for removing intermediate frequency signal components, a comparator 22 connected to the output of the filter 21, and a comparator 22 connected to the output of the filter 21. and a data conversion circuit 2 connected to the output of 22 for performing delayed detection.

Note that a local oscillator 15 is connected to the mixer 14, and a delay control circuit 20 is connected to the delay detector 1.

FIG. 3 is a timing chart for explaining the operations of the digital transmitter and digital receiver shown in FIGS. 1 and 2. The operation will be described below with reference to FIGS. 1 to 3.

A case where a signal S1 as shown in FIG. 3 is given as the digital signal S1 to be transmitted to the digital transmitter shown in FIG. 2 will be described. In sum converter 3, EX
The output signal of the OR gate 31 is delayed by a time length of 2 bits by the D flip-flop 32 and applied to the other input of the EXOR gate 31. EXOR gate 31 is
A mismatch between the digital signal S1 to be transmitted and the 2-bit delayed signal is detected, and the output signal is sent to the phase modulator 33.
give to

The phase modulator 33 performs phase modulation of the signal S2 based on the signal from the oscillator 34, and provides the modulated signal to the high frequency amplifier 35. The high frequency amplifier 35 amplifies the modulated signal, and the output signal is transmitted to the transmitting antenna 3.
6.

In the receiving apparatus shown in FIG. 1, a signal received by a receiving antenna 11 is amplified by a high frequency amplifier 13 after unnecessary signal components are removed by a filter 12. Mixer 14 converts the amplified signal into an intermediate frequency based on the signal from local oscillator 15. The signal converted to an intermediate frequency is given to a comparator 17 after high frequency components are removed by a filter 16 . The comparator 17 binarizes the signal, and the binarized signal S3 is provided to the delay detector 11. As shown in FIG. 3, the signal S3 has the same waveform as the sum-transformed signal S2 in the transmitter.

In the delay detector 1, the signal S3 and a signal S4 delayed by the time length of one bit of the signal S3 obtained by the shift register 18 are applied to the EXOR gate 19. E
XOR gate 19 detects a mismatch between signals S3 and S4 and provides an output signal to filter 21.

Note that a delay control circuit 20 is connected to the shift register 18 in the delay detector 1. The delay control circuit 20 performs phase detection of the current intermediate frequency signal and the intermediate frequency signal 1 bit before, and controls the delay time of the shift register 18 based on the detection result. As a result, there is an effect of widening the aperture of the eye pattern of the signal.

The intermediate frequency signal component of the output signal of the delay detector 1 is removed by a filter 21, and further, the output signal is binarized by a comparator 22. Binarized signal S51 or S5
2 is applied to the data conversion circuit 2.

When reception is performed accurately, a signal S51 as shown in FIG. 3 is applied from the comparator 22 to the data conversion circuit 2. In the data conversion circuit 2, the signals S51 and D
A signal S61 delayed by the time length of one bit by the flip-flop 23 is applied to the EXOR gate 24. EXOR gate 24 detects mismatch between signals S51 and S61 and outputs signal S71. Therefore, a signal S71 having a waveform similar to that of the transmitted signal S1 is obtained.

On the other hand, when reception is not performed accurately due to variations in carrier frequency or variations in delay time, the comparator 22 outputs a signal S52 as shown in FIG.

This signal S52 has a completely reversed phase compared to the correct signal S51.

However, the signal S52 and the D flip-flop 23
The signal S62 delayed by the time length of 1 bit is applied to the EXOR gate 24, and the EXOR gate 24
When detecting a mismatch between signals S52 and S62, a signal S72 is obtained. Signal S72 has the same waveform as the transmitted digital signal S1. Therefore, even if the signal S52 whose phase is reversed is output from the comparator 22 due to inaccurate reception,
A correct signal S72 is obtained by the data conversion circuit 2.

In addition, in the description of the above embodiment, as an example when the reception is performed inaccurately, the signal S52 whose phase is completely reversed is used.
The case where the phase is not completely reversed, that is, the case where there is no delay sufficient to completely reverse the phase, need not be considered. The reason for this is that the delay control circuit 20 described above is connected to the delay detector 1, and due to the action of this circuit 20, the signal S5 due to correct reception from the comparator 22.
Either S52 of 1 or completely reversed in phase will be output.

[Effects of the Invention] As described above, the invention of claim (1) provides a summation transform that performs summation transform based on a time delay twice the length of one bit of a digital data signal to be transmitted. Now that the means has been provided, the necessary digital transmitting equipment is available for performing accurate digital communications. Moreover, in the invention of claim (2), since the second delay detection means is provided which further performs delay detection on the output signal of the first delay detection means,
A digital receiving device necessary for accurate digital communication has been obtained. Furthermore, in the invention of claim (3), a summation conversion means is provided on the transmitting side to perform summation conversion based on a time delay twice the length of one bit of the digital data signal to be transmitted, and on the receiving side, the summation conversion means is provided. Since the second delay detection means for further performing delay detection on the output signal of the first delay detection means is provided, a digital transmitting device capable of correctly receiving the transmitted data signal is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital receiving device showing an embodiment of the invention of claim (2). Figure 2 shows claim (1)
1 is a block diagram of a digital transmitting device showing an embodiment of the invention; FIG. FIG. 3 is a timing chart for explaining the operations of the digital receiving device and digital transmitting device shown in FIGS. 1 and 2. FIG. 4 is a characteristic diagram showing delayed detection characteristics according to a conventional reception method. In the figure, 1 is a delay detector, 2 is a data conversion circuit, 1
8 is a shift register, 19, 24, and 31 are exclusive OR gates, 20 is a delay control circuit, 23, 32 is a D flip-flop, and 3 is a summing converter.

Claims (3)

[Claims] (1) Receive a digital data signal to be transmitted consisting of a bit string, and
Summation conversion means for performing summation conversion based on a double time delay; Modulation means connected to receive an output signal from the summation conversion means and modulating the output signal of the summation conversion means for transmission. and transmitting means connected to the output of the modulating means for transmitting the signal modulated by the modulating means. (2) receiving means for externally receiving a signal including a digital data signal consisting of a bit string; and delayed detection based on a time delay of one bit length forming the bit string in response to the signal received by the receiving means. A digital receiving device comprising: a first delay detection means for performing the delay detection; and a second delay detection means for further performing the delay detection in response to an output signal from the first delay detection means. (3) The digital transmitter of claim (1) and claim (
2) A digital communication device including the digital receiving device.