JPH02140800A - Sound recording and reproducing device - Google Patents

Abstract

PURPOSE:To easily store encoded data having an arbitrary word length in a memory by making the data word length different between an encoding/ decoding means and a storage means. CONSTITUTION:Data is left justified and stored in a register 5 by the shift operation at each time of encoding, and data is written in a memory 2 and an address 61 of the memory 2 is updated when the register 5 is filled up with 8 bits even on the way of shift of 3 bits. Control signals 33 and 34 are outputted once each time when a shift clock 32 outputted from a control circuit 3 is outputted to registers 4 and 5 eight times. By this operation, 3-bit encoded data is written in the memory 2 without spaces. At the time of decoding, registers 4 and 5 are operated as one ring shift register to perform right shift three times. Thus, the memory is effectively used with encoded data having a bit length of high compression efficiency.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is an audio recording method in which encoded data obtained by digital signal processing of an audio signal is recorded in a semiconductor memory element, and the data is read out and decoded to reproduce an audio signal. The present invention relates to a playback device.

<Prior art> Conventionally, when the data word length of a memory device (the number of data pits assigned to one address) and the audio encoded data word length (the number of bits of encoded and decoded data) are different, Either one encoded data shown in Figure 5 (b) is allocated to one word of the memory device and read/written, or the encoded data is allocated so that the data word length of the memory device is an integral multiple of the encoded data word length. The word length was selected. For example, as shown in FIG. 5(c), when the data word length of the memory device is twice the encoded data word length, two pieces of encoded data are read and written to the memory device.

<Problems to be Solved by the Invention> However, in the method shown in FIG. 5(b), the data area in the shaded area in the figure is not used and is wasted.

Furthermore, in the method shown in FIG. 5(c), the length of encoded data is limited. That is, when the word length of the memory device is 8 bits, there is a problem that only word lengths of 4 bits, 2 bits, and 1 bit are suitable for encoded data.

The present invention was invented to solve the above-mentioned problems, and an object of the present invention is to provide a new audio recording/playback device.

Means for Solving the Problems> In order to achieve the above object, the present invention provides an audio digital recording and reproducing device that includes an encoding/decoding means for encoding and decoding an audio waveform, and an encoding/decoding means for encoding and decoding the encoded audio data. storage means for storing; temporary storage means located between the encoding/decoding means and the storage means for temporarily storing read and write data; address generation means for generating an address for the storage means; The present invention provides an audio digital recording and reproducing device comprising a storage means, the temporary storage means, and a control means for controlling the address generation means, wherein the encoding/decoding means and the storage means have different data word lengths. , thereby achieving the above objective.

Further, it is preferable that the data word lengths of the encoding/decoding means and the storage means are variable.

<Operation> In the audio digital recording and reproducing apparatus configured as described above, the encoded data from the encoding/decoding means is temporarily stored in the temporary storage means, and the word length of the storage means and the data are stored in the temporary storage means. The data written to the storage means and read from the storage means at the timing when the data coincides with each other is decomposed by the data word length of the encoding/decoding means by the temporary storage means, and is input to the encoding/decoding means. Audio data is decoded.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an audio digital recording and reproducing apparatus using the ADPCM encoding method with a code length of 3 bits according to the present invention. In the figure, the symbol 1 is an encoding/decoding circuit; An audio signal 11 that has been A/D converted from an A/D converter is input, and 3-bit encoded data 41 is output. Conversely, 3-bit encoded data 41 is input, and the decoded audio signal 12 is output to the D/A converter.

2 is a read function that stores encoded data in 8-bit units;
This is writable memory. 4 is a shift register having the same bit length (word length) as the encoded data 41, and the data 41 can be written to and read from the encoding/decoding circuit 1 in parallel. 5 is memory 2
It is a shift register having the same data word length as , and can write and read data 51 to and from a designated address of the memory 2 in parallel. Register 4 and register 5 constitute a circular shift register, and in one shift operation, the least significant bit of register 4 is transferred to the most significant bit of register 5, and the least significant bit of register 5 is transferred to the most significant bit of register 4. Connected to move to the bit. 6 is a memory address generation circuit that supplies memory addresses to the memory 2; 3 is a control circuit which receives an input signal 31 from the encoding/decoding circuit 1 and controls registers 4 and 5 . Memory 2. In order to send control signals to the memory address generation circuit, control lines 32° and 33.3 are connected, respectively.
Connected by 4.

The audio digital recording and reproducing apparatus of the present invention is constructed as described above, and its operation will be described below.

The audio signal is input to the encoding/decoding circuit 1 as A/D converted data 11 at regular sampling intervals. The encoding/decoding circuit 1 encodes data 11 every time it is input, and outputs 3-bit encoded data 41 to the register 4. At the same time, the encoding/decoding circuit 1 outputs a signal 31 indicating that data 41 has been output to the control circuit 3.
Output. The control circuit 3 controls the register 4 by the signal 31.
and outputs a clock 32 to the register 5 which is shifted to the right three times. This clock 32 causes registers 4 and 5 to operate as one 11-bit circular shift register, and the entire register is shifted to the right by 3 bits.

As a result, the contents of register 4 are 52+ in FIG. 2(a).
The data is moved to register 5 in a left-aligned manner, and register 4 becomes empty.

(Actually, the unnecessary 3-bit data at the right end of register 5 has been moved.) When data 11 is input in the next cycle, encoding/decoding circuit I performs the second encoding, Operating in the same manner as above, registers 4 and 5 are shifted three times to the right,
As shown at 531 in FIG. 2(b), data is stored in the register 5 in a left-aligned manner.

The previously encoded data 521 has been shifted three bits to the right.

When data 11 is further input in the next cycle, the encoding/decoding circuit I performs the third encoding, and registers 4 and 5 are shifted to the right in the same way as before, but
At the end of the second shift, 8-bit register 5
is filled with code data, and the control circuit 3 writes the 8-pit data of the register 5 into the memory 2 in response to the control signal 33. At this time, the memory address 61 is set by the memory address generation circuit 6 to the address where data is to be written, for example, address 0. When this data write is completed, the memory address generation circuit 6 advances the value of the memory address 6] by one in preparation for the next write. Also, register 4 and register 5 perform one remaining right shift operation, register 4 becomes empty, and register 5 has the second
As shown in Figure (c), one bit of data 541 out of the three bits that were not written to the memory 2 is stored.

Thereafter, each time encoding is performed in the same way, data is stored in register 5 by a shift operation, left-justified, and even in the middle of shifting 3 bits, when register 5 is filled with 8 bits, the data is stored in memory 2. and the address 61 of memory 2 is updated. Control signal 33.3
4 can be realized by outputting the shift clock 32 from the control circuit 3 to the registers 4 and 5 once every eight times.

Through the above operations, 3-bit encoded data is written into the memory 2 without any gaps as shown in FIG. 5(a).

During decoding, a control signal 33 is first output from the control circuit 3 to the memory 2, whereby 8-bit memory data is read into the register 5. At this time, the memory address 61 is set to the address from which data is to be read, for example, address 0. When the control signal 33 is output and memory reading is performed, the control circuit 3 activates the memory address generation circuit 6 to read the next memory data.
The control signal 34 is outputted to the memory address 61 and the memory address 61 is advanced by one. Subsequently, the control circuit 3 outputs the clock 32 to be shifted three times to the registers 4 and 5, and as in the case of encoding, the registers 4 and 5 operate as one circular shift register. Perform a right shift. That is, during decoding, the rightmost three bits of register 5 are moved to register 4 by three shifts, and the leftmost three bits of register 5 become empty as shown in FIG. 3(a). (
In reality, 3 bits of unnecessary data in register 4 will be moved. ) In other words, the code data that was first encoded and written to the memory 2 during encoding is read from the memory 2 by the above operation and is set again in the register 4. The above steps are preparatory operations for playback.

The encoding/decoding circuit 1 includes a register 4 that is set one after another in the following operation at each fixed sampling period.
The original speech waveform can be obtained by reading the encoded data 41 and outputting it to the D/A converter as decoded speech synthesis data 12.

First, the encoding/decoding circuit 1 inputs the encoded data 4 of the register 4.
] After reading out the data, it is decoded and the control circuit 3
A signal 31 indicating that data 41 has been input is outputted. Accordingly, the control circuit 3 controls the register 4. A clock 32 for shifting the register 5 three times is output. As shown in FIG. 3(a), the rightmost 3-bit data 532 of register 5 is moved to register 4 by three shift operations, and register 5 is moved to memory 2 as shown in FIG. 3(b).
More read data 542 remains. This data 542 is 2 bits, and the remaining 1 bit is still stored in memory 2.
has not been read from.

Furthermore, during the next decoding, after the code data 41 set in register 4 is read out, register 4 and register 5 perform three shift operations, but when the second shift operation is completed, the register 5 becomes empty, a control signal 33 is output from the control circuit 3 to the memory 2, and new 8-bit data is read from the memory 2 into the register 5. The remaining 1 bit of data 542 is included at the right end of this data. At this point, the memory address generation circuit 6 advances the memory address 61 by one in response to the control signal 34 for the next reading of memory data.

Following this, the remaining one of the three shifts is performed. Through this operation, the remaining 1 bit of data 542 is sent from the right end of register 5 to register 4, and register 4 now has 3 bits of data 542, which is read out as encoded data 41 by encoding/decoding circuit 1. be able to. Also, register 5 is shown in Figure 3 (
c).

Thereafter, data is shifted from register 5 to register 4 three times at every sampling period when encoder/decoder 1 reads code data 41 from register 4, and each time register 5 becomes empty, data is shifted from register 5 to register 4. Data is read from data 41, and the encoding/decoding circuit 1 is set so as to be able to read data 41 at all times. If the register 5 becomes empty during the third shift, the new 8-bit data is read from the memory 2 at that point, and the shift operation is performed the remaining number of times. In this way, even if the encoded data of 3-pit group I is divided between different addresses in the memory 2 as shown in FIG. Therefore, when the data is sent to the register 4, it is arranged as 3-bit data at the time of encoding. .

Since the register 5 becomes empty every eight shifts, the control signal 33 is used to read the memory data 51 from the memory 2.
The control signal 34 that advances the memory address 61 by one can be realized by outputting it once every eight times the clock 32 is output.

Although the code data length is described as 3 bits, encoding and decoding can be performed with any code data length by making the number of shifts between the pit length of register 4 and the sampling period the same as the code data length. be able to.

Furthermore, although the data word length of the memory 2 is described as 8 bits, by making the data word length of the register 5 the same as that of the register 5, a memory of any word length can be used. In this case, if the data word length of the memory is N, reading and writing between register 5 and memory 2 are performed in register 4.
and once every eight shifts of register 5.

Next, another embodiment according to the present invention is shown in FIG.

The difference from the embodiment shown in FIG. 1 is that the effective data length of the register 4 can be made variable by a control signal 35 from the control circuit 3. In this embodiment, the switching circuit 7 switches between the case where the encoded data 41 is 5 bits and the case where it is 3 bits.

The respective operations are similar to those in the embodiment shown in FIG.

In general, the relationship between the sound quality of speech synthesized by encoding and decoding and the encoded data length is that the longer the encoded data length, the more information there is, so the sound quality is better, but the number of encoded data that can be stored in a certain amount of memory Since there are fewer recording and playback times, the recording and playback time becomes shorter. Conversely, if the code data length is short, the amount of information is small, resulting in poor sound quality, but since the number of code data that can be stored in a given memory capacity is large, the recording/playback time becomes longer. Therefore, in the embodiment of FIG. 4 in which the encoded data length can be specified by the user, it is possible to select whether to give priority to sound quality or recording time. Further, although this embodiment shows an example of switching between 5 bits and 3 bits, it is also possible to switch between codes having other data lengths, and by making the switching circuit 7 multi-input, it is possible to switch between codes having other data lengths.
More than one switching is also possible.

<Effects> Since the present invention is configured as described above, encoded data having an arbitrary word length can be stored in the memory without any waste without being restricted by the data word length of the memory that stores the data. It can be read out as the original code. Therefore, it is possible to effectively utilize memory with bit-length encoded data with high compression efficiency, and to perform recording and playback with good sound quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an audio digital recording/playback device according to the present invention, FIGS. 2 and 3 are diagrams showing states in which data in a register is shifted, and FIG. FIG. 5 is a block diagram showing another embodiment of the audio digital recording/playback device, and is a diagram showing a state in which data is stored in the memory. 1: Encoding/decoding circuit, 2: Memory, 3: Control signal, 4
．． 5: Register, 6: Memory address generation circuit, 7: Switching circuit. Agent Patent attorney Takeshi Sugiyama (and 1 other person) Figure 63 Figure III Figure 4 (a) (C) @Figure 5

Claims (1)

[Scope of Claims] 1. A voice recording and reproducing device comprising: encoding/decoding means for encoding and decoding voice waveforms; storage means for storing encoded voice data; the encoding/decoding means and the memory; temporary storage means for temporarily storing read and write data; address generation means for generating an address for the storage means; controlling the storage means, the temporary storage means, and the address generation means; 1. A voice recording and reproducing apparatus, characterized in that the encoding/decoding means and the storage means have different data word lengths. 2. The audio recording and reproducing apparatus according to claim 1, wherein the encoding/decoding means and the storage means have variable data word lengths.