JPH02135898A - Time division exchange unit - Google Patents

Abstract

PURPOSE:To set the delay time of respective signals shortest by providing private time division exchange memories for respective signals, a signal selection circuit outputting either signal from respective memories and a control circuit outputting a time division exchange address to respective memories and a signal selection/switching signal to the signal selection circuit based on signal identification information. CONSTITUTION:For time-divisionally exchanging respective signals having different transmission speeds, respective signals are exchanged in respectively private time division exchange memories 5A and 5B. Exchange at that time is performed by permitting respective memories 5A and 5B to receive the time division exchange addresses from the control circuit 6. Either one of the signals from respective memories 5A and 5B is outputted from the signal selection circuit 9. At that time, the signal is selected by a signal selection/switching signal based on signal identification information outputted from the control circuit 6. Thus, the delay time of respective signals can be made shortest when the signals having different transmission speeds are time divisionally exchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division exchange unit that exchanges signals having different transmission speeds in a time division manner.

In the currently used time division multiplexing equipment (MUX), for example, signals such as data sent at a transmission rate of 3.2 Kbps (hereinafter referred to as 3.2 system signal), 8K
Signals such as voice sent at a transmission speed of bps (hereinafter referred to as
It is common practice to mix signals with different transmission speeds (such as system signals) and exchange them in a time-division manner.

Here, if the frame structure of the system signal is shown in 3.2, the fifth
As shown in the figure, 8 shows the frame structure of the system signal.
It will look like Figure 6.

First, in 3.2, in the frame structure of the system signal, as shown in FIG. 5, one frame is made up of n time slots TS, and each time slot is made up of 8 bits.

Also, the first bit of each time slot is the frame synchronization bit (X, 50) F, the last bit is the status bit S,
The second to seventh bits are configured as information bits D to DG. Furthermore, these synchronization bits F constitute a multi-frame synchronization detection system in which a plurality of synchronization bits have meaning, and in this case, each of 20 frames has meaning.

Therefore, if the time for one frame is 125 μSeC,
The time for 20 frames is 2.5 m5ec (equivalent to 400 Hz). Note that in the figure, MTSNo means a multi-time slot number, and A means a bus status bit. In addition, in the lower right part of the figure, channel accommodation positions according to speed are described by channel numbers CHi for frames 1 to 20.

Next, in the frame structure of the system signal shown in FIG. 6, one frame is made up of n time slots TS, and each time slot is made up of 8 bits. Note that in each time slot, all bits are information bits I□~
■It is configured as 6. Further, in the lower part of the figure, channel accommodation positions by speed are written as channel numbers CHi.

Therefore, when exchanging time slots, if one frame is, for example, 125 μsec, taking into consideration the write and read times, the system signal will have a maximum of 20 μsec in 3.2.
It is desirable to have a delay of 0 Hz and a maximum delay of 4 KHz for system signals.

[Prior Art] FIG. 4 is a block diagram showing a conventional time division switching unit. In FIG. 4, 200 is a time division switching unit, and this time division switching unit 200 has a unit data memory 64. 1, 2. X50 frame synchronization control circuit 3.
Parallel/serial conversion circuit 4, 3.2 has system data memory 5A, address control memory 6', serial/
It is configured with a parallel conversion circuit 72 and a phase adjustment circuit 8.

Here, the unit data memories 1 and 2 are for selecting data in units of 64 from the time division multiplexed bus 100, and
The 50 frame synchronization control circuit 3 outputs system signals to 3 and 2 to which the X50 frame is added in synchronization with the internal phase of the device, and the parallel/serial conversion circuit 4 converts 8-bit parallel data to serial data. It is something to do.

In addition, the system data memory 5A in 3.2 is a memory for time division exchange that serially inputs signals in units of 3.2 and outputs them randomly according to the required address data from the address control memory 6'. The control memory 6' outputs the address of the system data memory 5A to 3.2.

In addition, the system data memory is used for 3 and 2, where signals are input serially in units of 3.2, if the system data memory is used in 8, where signals are input serially in units of 8. This is because it becomes impossible to exchange system signals in 3 and 2, which requires a delay of about 5200 Hz. On the other hand, even if a 3.2 system data memory is used as a data memory in which signals are input serially in units of 3.2, system signals can be exchanged at 8 with a short delay of 4 KHz.

Further, the serial/parallel conversion circuit 7 converts serial data into 8-bit parallel data, and the phase adjustment circuit 8 has unit data memories 1, 2, 3.2 in 64.
It absorbs the phase difference generated in the system data memory 5A and adjusts it to the phase of the time division multiplexed bus 100.

With this configuration, the system signal (data signal) in 3.2
System signals (audio signals) are also transferred to unit data memory 1.8 and time division multiplex buses 100 to 64. 3. via the X50 frame synchronization control circuit 3 and parallel/serial conversion circuit 4.
2 is time-division exchanged in the system data memory 5A, and then transferred to the serial/parallel conversion circuit 72 phase adjustment circuits 8 and 64 via the unit data memory 2, and again to the time-division multiplex bus 1.
Returned to 00. In other words, both the system signal (data signal) in 5.3.2 and the system signal (audio signal) in 8 are stored in a common data memory (3
, 2 and system data memory 5A), time-division exchange is performed.

[Problems to be Solved by the Invention] However, in such a conventional time division switching unit, as mentioned above, the system signal (data signal) is also
Since the system signals (audio signals) are also time-division exchanged using one data memory (system data memory 5A at 3 and 2), the exchange of the system signals at 8 is also based on the cycle of the system signals (40
This requires a delay of 3°2 for the system signal. Therefore, when these time-division exchange units are connected in multiple stages, problems such as poor transmission and reception and echoes occur due to excessive delay in system signals.

The present invention has been made in view of these problems, and provides a time division exchange unit that can minimize the delay time of each signal when exchanging signals with different transmission speeds in a time division manner. It is intended to.

[Means to solve the problem] FIG. 1 shows a block diagram of the principle of the present invention.

In this figure, 5A and 5B are dedicated time-division exchange memories for each signal having a different transmission speed, and 6 is a memory for each memory 5.
A control circuit that outputs an address for time division exchange to A and 5B and also outputs a signal selection switching signal to the signal selection circuit 9 based on signal identification information, and 9 outputs one of the signals from each memory 5A and 5B. This is a signal selection circuit.

[Operation] With such a configuration, in order to perform time-division exchange for each signal having a different transmission rate, each signal is exchanged in its own time-division exchange memory 5A, 5B. The exchange at this time is performed by each memory 5A, 5B receiving an address for time division exchange from the control circuit 6.

Then, one of the signals from each memory is outputted from the signal selection circuit 9, and the signal selection at this time is performed by a signal selection switching signal based on signal identification information outputted from the control circuit 6.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In this FIG.
,2. X50 frame synchronization control circuit 3. Parallel/serial conversion circuits 4A, 4B, 3.2 and system data memory 5A
, 8, a system data memory 5B, and a control circuit 6. Serial/parallel conversion circuit 72 phase adjustment circuit 8. Data selector (
signal selection circuit)9. It is configured with a signal distribution circuit 10.

Here, unit data memories 1, 2 . The X50 frame synchronization control circuit N3, 3.2, system data memory 5A, serial/parallel conversion circuit 79 and phase adjustment circuit 8 are the same as the conventional one shown in FIG. 4, so their explanation will be omitted. . Note that since both the parallel/serial conversion circuits 4A and 4B have the same function as the parallel/serial conversion circuit 4, a description of these parallel/serial conversion circuits 4A and 4B will also be omitted.

By the way, the system data memory 5B at 8 is a time-division exchange system in which the system data memory 5A serially inputs signals in units of 3.2 and outputs them randomly according to the required address data from the control circuit 6. In contrast to the memory, it is a memory for time division exchange in which signals are serially input in units of 8 and output randomly according to required address data from the control circuit 6. That is, a system data memory 5A is provided at 3.2 for system signals, and a system data memory 5B is provided at 8 for system signals.

Further, the control circuit 6 outputs an address for time division exchange to each memory 5A, 5B, and also outputs a signal selection switching signal to the data selector 9 based on the signal identification information. 6 is address memory 6
-1. Counter 6-2.6-3. Switching circuit 6-4.6-
It has 5.

Here, the address memory 6-1 is a memory (for example, ROM) that stores time-division exchange addresses for exchanging time slots, and the counter 6-2 outputs a 400 Hz counter signal (400 Hz clock). The counter 6-3 outputs an 8KHz counter signal (8KHz clock), and the switching circuit 6-4.6-5 receives the signal from the counter 6-2.6-3 and outputs an address signal every 400 Hz or 8KHz. This is to switch between.

Note that one bit of the address from the address memory 6-1 is output to the data selector 9 as a signal selection switching signal. and.

The timing of issuing this signal selection switching signal is determined in advance by the system.

The data selector 9 receives a signal selection switching signal from the control circuit 6 and outputs one of the signals from each of the memories 5A and 5B.

The signal distribution circuit 10 transfers output data from the unit data memory 1 to 64 and system circuits 3.2 (X50 frame synchronization control circuit 3, parallel/serial conversion circuit 4A, system data memory 5A, etc. to 3.2). and 8 and system circuits (parallel/serial conversion circuit 4B, system data memory 5B, 8, etc.).

With the above configuration, the system signal (data signal) is 6 in 3.2.
4, the signal distribution circuit 10 via the unit data memory 1, and 3.
Distributed to the 2nd system circuit. That is, the system signal at 3°2 is
It is input from the frame synchronization control circuit 3 to the system data memory 5A at 3.2 via the parallel/serial conversion circuit 4A,
In this 3.2 system data memory 5A, the time slots are changed and outputted based on the address information that changes every 400 Hz. As a result, in 3.2, system signals are time-division exchanged with a maximum delay of 200 Hz.

On the other hand, the 8 system signal (audio signal) passes through the unit data memory 1 at 64 and is distributed to the 8 system circuit by the signal distribution circuit 10.

That is, the system signal at 8 is inputted to the system data memory 5B at 8 through the parallel/serial conversion circuit 4B, and in this system data memory 5B at 8, the time slots are switched and outputted based on address information that changes every 8 KHz. . As a result, these 8 system signals are time-division exchanged with a maximum delay of 4 KHz.

Here, the delay range of each signal is shown in FIG. 3. From this figure, we can see in 3.2 that the system signal has a delay of O~5.
It fits within m5ec, and the delay of the system signal is 0 to 250 in 8.
It can be seen that it is within μsec.

After the time slots in each memory 5A, 5B are replaced, the data selector 9 receives the signal selection switching signal output at a predetermined timing, and changes the signal from each memory 5A, 5B. Select one and output.

Furthermore, the signals from this data selector 9 (system signal at 3°2, system signal at 8) are sent to the serial/parallel conversion circuit 72.
After passing through the phase adjustment circuit 8, it is returned to the 1-hour side row weight bus 100 via the unit data memory 2 at 64.

In this way, even when time-division multiplexing is performed in which the system signal at 3.2 and the system signal at 8 are mixed, the delay of the system signal at 3.2 is within 5m5ec (200Hz), and the delay at 8.
Since the system signal is delayed within 250 μsec (4 KHz), problems such as poor transmission and reception and echoes due to excessive delay in the system signal are eliminated, and as a result, this greatly contributes to improving the performance of the time division multiplexing device.

It goes without saying that the present invention can be similarly applied to a time-division exchange unit that time-divisionally exchanges signals having mutually different transmission speeds in combinations other than 3.2 Kbps and 8 Kbps.

[Effects of the Invention] As detailed above, according to the time division exchange unit of the present invention, a dedicated time division exchange memory is provided for each signal having a different transmission speed, and each memory corresponding to each signal is used. Since time-division exchange is performed by time-division, when signals with different transmission speeds are exchanged in time-division, the delay time of each signal can be minimized, which prevents problems such as poor transmission and reception and echoes due to excessive signal delay. This has the advantage that it can greatly contribute to improving the performance of the time division multiplexing device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of an embodiment of the present invention, and Fig. 4 is a conventional example. 5 is a block diagram showing the frame structure of the system signal in 3.2, and FIG. 6 is a diagram showing the frame structure of the system signal in 8. In the figure, 1.2 has a unit data memory in 64, 3 has an X50 frame synchronization control circuit, 4.4A and 4B have a parallel/serial conversion circuit, 5A has a system data memory in 3.2, and 5B has a system in 8. Data memory, 6 is a control circuit, 6-1 is an address memory, and 6-2-6-3 is a counter. 6-4.6-5 is a switching circuit. 7 is a serial/parallel conversion circuit; 8 is a phase Jf squarer circuit; 9 is a data selector (signal selection circuit); and 10 is a signal distribution circuit. 100 is a time division multiplexed bus, and 200 is a time division switching unit. , Book, Invention of Torakuri Pro-Tsuku Diagram 1

Claims (1)

[Claims] A time division exchange unit (200) that exchanges signals having different transmission speeds in a time division manner, comprising time division exchange memories (5A, 5B) dedicated to each signal;
a signal selection circuit (9) that outputs one of the signals from each of the memories (5A, 5B); and a signal selection circuit (9) that outputs an address for time division exchange to each of the memories (5A, 5B), and selects a signal based on the signal identification information. A control circuit (6) that outputs a signal selection switching signal to the signal selection circuit (9).
A time division exchange unit characterized by being provided with.