JPH02132287U - - Google Patents
Info
- Publication number
- JPH02132287U JPH02132287U JP4134089U JP4134089U JPH02132287U JP H02132287 U JPH02132287 U JP H02132287U JP 4134089 U JP4134089 U JP 4134089U JP 4134089 U JP4134089 U JP 4134089U JP H02132287 U JPH02132287 U JP H02132287U
- Authority
- JP
- Japan
- Prior art keywords
- display unit
- substrate
- led display
- circuit pattern
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Multi-Conductor Connections (AREA)
Description
第1図と第2図は本考案実施例の構造を示す斜
視図、第3図はLED表示ユニツトの正面構造を
示す図、第4図は従来例の部分断面構造を示す図
、第5図は従来例の外観斜視構造を示す図である
。
1,6……LED表示ユニツトの基板、2,7
……駆動回路基板、3,8……フレキシブル配線
基板、4,5……コネクタ、9,10……はんだ
付部分。
Figures 1 and 2 are perspective views showing the structure of the embodiment of the present invention, Figure 3 is a front view of the LED display unit, Figure 4 is a partial cross-sectional view of the conventional example, and Figure 5. 1 is a diagram showing an external perspective structure of a conventional example. 1, 6...LED display unit substrate, 2, 7
... Drive circuit board, 3, 8 ... Flexible wiring board, 4, 5 ... Connector, 9, 10 ... Soldering part.
Claims (1)
並設された構造であるLED表示ユニツトにおい
て、上記LEDチツプへ給電するための配線回路
パターンと、この配線回路パターンと外部回路と
を接続するための集中的に配列した端子群とが上
記基板の裏面に形成されてなるLED表示ユニツ
ト。 In an LED display unit having a structure in which LED chips are arranged side by side in a matrix on the surface of a substrate, there is a wiring circuit pattern for supplying power to the LED chips, and a central wiring for connecting this wiring circuit pattern and an external circuit. An LED display unit comprising a group of terminals arranged on the back surface of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4134089U JPH02132287U (en) | 1989-04-07 | 1989-04-07 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4134089U JPH02132287U (en) | 1989-04-07 | 1989-04-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02132287U true JPH02132287U (en) | 1990-11-02 |
Family
ID=31551923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4134089U Pending JPH02132287U (en) | 1989-04-07 | 1989-04-07 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02132287U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632987U (en) * | 1986-06-24 | 1988-01-09 |
-
1989
- 1989-04-07 JP JP4134089U patent/JPH02132287U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632987U (en) * | 1986-06-24 | 1988-01-09 |