JPH0213182A - Channel search circuit - Google Patents

Abstract

PURPOSE:To select one signal source from plural signal sources including a signal source from a broadcast station sequentially and attaining simultaneous display on small patterns being plural divisions of one display pattern by controlling the selection operation of a signal selection source selection means, a storage operation of a storage means and an address generating operation of an address generating means with a control means. CONSTITUTION:The control means 20 controls the selecting operation of the signal source selection means 24 selecting sequentially one signal source from plural signal sources 22, 23 including a signal source from a broadcast station and the storage operation of the storage means 25 storing a signal from the signal sources 22, 23 selected in order by the selection means 24 for at least one field each. Moreover, the control means 20 controls the address generating operation of an address generation means 34 generating an address corresponding to each of small patterns divided into plural from one display pattern in the case of storing each signal into the storage means 25 and extracting each signal from the storage means 25. Thus, one signal source is selected sequentially from plural signal sources including the signal source from the broadcast station to display small patterns being plural divisions of one display pattern simultaneously.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention sequentially selects signals from a broadcasting station or external signals from a video deck, etc., and reduces them simultaneously on one screen of a display device. This invention relates to a channel search circuit for displaying images.

(Prior Art) Generally, a television receiver is a device that can almost simultaneously reproduce video signals from a television camera that converts video into electrical signals at a remote location.

In such a television receiver, a video signal from a television camera is converted into a one-dimensional electrical signal by electrically scanning it from left to right and repeating it sequentially from top to bottom. The accuracy of the reproduced image is determined by the number of times this left-to-right scanning is repeated for one image, and the number of times is called a scanning line.

By the way, in such a television receiver,
For example, a channel search circuit is considered as one of the special functions that utilizes a large-capacity image memory (field memory).

That is, such a channel search circuit displays a plurality of programs being broadcast at once on small screens a to p, as shown in FIG.

As a result, viewers can compare programs currently being broadcast.

FIG. 7 shows such a channel search circuit.

As shown in the figure, the channel search circuit is equipped with a control macroprocessor 1. Connected to the control microprocessor 1 is a Vl(l'/UIIF tuner 2) that detects the RP multiplied signal transmitted from the broadcasting station. A decoder 3 is connected to decode the signal.

The decoder 3 is connected to A/D converters 4, 5.6 that convert signals from the decoder 3 into digital signals. Each A/D converter 4, 5.6 has a field memory (FM) 7.

8.9 is connected. Each field memory 7°8.
9 includes a synchronization separation circuit 10 and a read synchronization generation circuit 11 controlled by the control microprocessor 1.
An address/memory control signal generation circuit 12 is connected to generate address/memory control signals based on signals from the address/memory control signal generation circuit 12.

Further, each field memory 7.8.9 is connected to a D/A converter 13, 14.15 which converts the signals from these field memories 7.8.9 into analog signals. A video signal output circuit 16 that outputs a video signal is connected to each D/A converter 13.14.15.

In the channel search circuit having such a configuration, first, the RF multiplied signal Vl! transmitted from the broadcasting station is detected. P-UIIP tuner 2 is detected. The detected 1?1 signal is converted into a video composite signal and sent to the decoder 3.

Next, the video composite signal is converted into, for example, a luminance signal Y and a color difference signal B-Y by a decoder 3.

After being decoded into R-Y, A/D converter 4゜5
．． 6 is converted into a digital signal and written into the field memory 7.8.9.

At this time, writing in each field memory 7, 8, and 9 is controlled by the control microprocessor 1 and the address/memory control signal generation circuit 12. That is, the signals from the tuner 2, which are switched one after another by the channel up signal (Cut) from the control microprocessor 1, are sequentially written into the field memory 7.8.9.

Reading from field memory 7.8.9 is performed based on a synchronization signal generated by read synchronization generation circuit 11 and according to a read address from address/memory control signal generation circuit 12.

Thereafter, the luminance signal Y and color difference signals B-Y and RY written in each field memory 7.8.9 are converted into analog signals by D/A converters 13 and 14.15, respectively, and output as video signals. The signal is sent to circuit 16.

(Problems to be Solved by the Invention) By the way, in the conventional channel search circuit described above,
After the RP multiplied signal transmitted from the broadcasting station is detected by the VIIP/UIIP tuner 2, it is intended to be displayed on the display screen. For this reason, video decks, video disc players, BS tuners, home computers, teletext tuners, and CATVs have become increasingly used in recent years.
, an external signal source such as the Captain System, or an internal signal source of the built-in television receiver cannot be displayed simultaneously on one display screen.

The present invention was made under these circumstances, and it is possible to sequentially select one signal source from a plurality of signal sources including signal sources from broadcasting stations, and to divide one display screen into one summer number. It is an object of the present invention to provide a channel search circuit that can be displayed simultaneously on a screen.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the channel search circuit of the present invention searches one signal source from a plurality of signal sources including a signal source from a broadcasting station.
signal source selection means for sequentially selecting one signal source; storage means for storing signals from each signal source sequentially selected by the selection means for at least one field; storing each signal in the storage means; Address generation means for generating addresses corresponding to a plurality of small screens obtained by dividing one display screen into a plurality of small screens when taking out each signal from the storage means, address generation operation of this address generation means, and selection of signal source selection means. and control means for controlling the operation.

(Function) In the channel search circuit of the present invention, the control means performs a selection operation of the signal source selection means that sequentially selects one signal source from a plurality of signal sources including signal sources from broadcasting stations; During the storage operation of the storage means for storing signals from each signal source in at least one field, and when each signal is stored in this storage means and each signal is taken out from this storage means, one display screen is stored. It is possible to control the address generation operation of the address generation means that generates addresses corresponding to a plurality of divided small screens.

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

FIG. 1 shows a channel search circuit showing one embodiment of the present invention.

Note that the video signal obtained by the channel search circuit is displayed on a small screen on one display screen for each channel.
It is assumed that the image is divided into 16 parts p and projected. That is, as shown in FIG. 6, V! It is assumed that the signal from the It'.UIIP tuner is displayed on small screens a-n, the signal from the internal signal source is displayed on small screen 0, and the signal from the external signal source is displayed on small screen p.

As shown in the figure, the channel search circuit is equipped with a control microprocessor 20. The control microprocessor 20 receives the home position signal (IIP) or channel up signal (C0) from the control microprocessor 20.
A VIIP-UIIP tuner 21 is connected to detect the R l'-fold signal transmitted from the broadcasting station based on the above.

Vllll'-UIIFchi! -1-211: 1m, based on the (HP) signal or selection switching signal (SC) from the control microprocessor 20, the VIP-U
HF tuner 21, internal signal source 22 and external signal source 2
A video signal selection circuit 24 for selecting signals from 3 is connected.

A decoder 25 for decoding the signal selected by the video signal selection circuit 24 and a synchronization separation circuit 32 are connected to the video signal selection circuit 24 .

The decoder 25 includes an A/D converter 26.27.2 that converts the signal from the decoder 25 into a digital signal.
8 are connected. Each A/D converter 26, 27.
28 has field memory (PM) 29, 30, 31
is connected.

Each field memory 29, 30, 31 contains an (IIP) signal from the control microprocessor 20, an address generation start signal (WS), an address generation permission signal (
WE) and an address/memory control signal generation circuit that generates a write address signal (AD) or a read address signal (YD) based on a signal from the synchronization separation circuit 32 or a read synchronization signal (R8) from the read synchronization generation circuit 33. 34 are connected.

Further, each field memory 29, 30, 31 is connected to a D/A converter 35, 36, 37 that converts the signals from these field memories 29, 30, 31 into analog signals. Each D/A converter 35, 36.37
A video signal output circuit 38 that outputs a video signal is connected to.

Note that (CIE) in the figure indicates field memory 29. 30
After the (AD) signal corresponding to the small screen a in FIG. 6 is output at 31, the address/memory control signal generation circuit 34 outputs the signal source switching permission signal to the control microprocessor 20. .

Also (CF) is field memory (FM) 29, 3
At 031, a channel switching end signal is output from the VIIP-UIIF tuner 21 to the control microprocessor 20 when writing to the field memories 29, 30, and 31 corresponding to small screens a to n in FIG. It is.

Next, the operation of the channel search circuit having such a configuration will be explained using FIGS. 2 and 3.

First, in the normal mode, the channel search mode c-0 is set (step 1).

Next, in step 2, the control microprocessor 20 determines whether the input to the channel search mode key (not shown) is blank or not. If the input of the channel search mode key is H, channel search mode C is determined in (step 3).

At this time, since the channel search mode is set to c-0, the channel search mode is set to c-1 in (step 4). Next, in step 5, the number of occurrences s of the switching signal (SC) output from the control microprocessor 20 to the signal selection circuit 24 is determined.
−[It is taken as 1.

After this, the control microprocessor 20
IIP-0111-' Outputs the (HP) signal (a in HP in FIG. 3) to the tuner 21, video signal selection circuit 24, and address/memory control signal generation circuit 34 (
Step 6).

and VIP-UIIP which received the <IIP) signal
When the tuner 21 selects a channel to be displayed on the small screen a in FIG. 5, the selected signal is converted into a video composite signal and sent to the video signal selection circuit 24.

At this time, the internal signal source 22 and the external signal source 23
The signal from is sent to the video signal selection circuit 24,
Here, first, the video signal selection circuit 24 selects VII['
-Ull! 'It is set so that only the signal from the tuner 21 is selected. Thereafter, the selected video composite signal is transferred to the decoder 25 and the sync separation circuit 32.
sent to.

Next, in step 7, the control microprocessor 20 determines the presence or absence of the (CF) signal (CF a in FIG. 3) from the VIIP-0111' (-UNA 21).

However, since this (CF) signal is a signal generated when writing of the signals corresponding to the small screens a to n in FIG. 6 is completed, it is not generated at this time.

Then, in (step 8) and (step 9), it is determined whether the (SC) signal (a or b in FIG. 3 SC) is the same number of occurrences. However, at this point, it is set to s-0.

After this, in (step 10), the control microprocessor 20 controls the VIIP/old (F tuner 2
The generation of the (WS) signal to the address/memory control signal generation circuit 34 is awaited until the channel No. 1 finishes tuning.

Here, the control microprocessor 20 outputs the (WS) signal (a in FIG. 3 WS) after waiting for a certain period of time, but this waiting time is limited to the (IIP) signal and the (WS
) This is in accordance with the waiting time of the signal. This is V111'-
The time during which the video composite signal from the Ull' tuner 21 and the video composite signal from the internal signal source 23 are displayed on the screen VIIP-UIIP tuner 21
This is to avoid giving an unnatural feeling by synchronizing the channel switching timing.

Thereafter, the video composite signal sent to the decoder 25 includes, for example, a luminance signal Y and a color difference signal B-Y.

After being decoded into R-Y, it is converted into a digital signal by an A/D converter 26°27.28.

Next, in (step 11), the address/memory control signal generation circuit 34 outputs the (AD) signal to each field memory 29, 30.31, and the video composite signal converted into a digital signal is sent to the field memory 29.31. 3031.

At this time, for example, each field memory 29°30.31
Use a memory map type for the water/I hole direction.
If control is performed by dividing the control into 024 samples and 256 samples in the vertical direction, the address A corresponding to the small screen a will be 0 to 255 in the horizontal direction and 0 to 63 in the vertical direction, as shown in FIG.

Thereafter, when writing to each field memory 29, 30, 31 is completed, in (step 12) the address/memory control signal generation circuit 34 sends a (CE) signal (FIG. 3C) to the control microprocessor 20.
B a) Output.

The control microprocessor 20 that has received the (CIE) signal causes the VllF/UllFll-na 21 to select the channel to be displayed on the small mountain face in FIG.
C1, I) signal (a in FIG. 3 C1J) is output (step 1'3).

Thereafter, the process returns to (step 2), and the control microprocessor 2 ( ) again determines whether or not the channel search mode key is pressed manually.

At this point, since the channel search mode key is not manually operated, channel search mode C is determined in (step 14).

At this time, since the channel search mode of the V II P.U II F tuner 21 remains in c-1, the line a is moved to.

The steps up to this point are for displaying the MF multiplied signal from the broadcasting station on the small screen a in FIG.

Through such a procedure, the field memories 293C1,
31, when the writing of the video signals corresponding to the small screens a to n in FIG. 6 is completed, the VIIP-UIIF tuner 21 sends the (CF) signal (
Output a) in Fig. 3 CF.

Thereafter, in step 7, it is determined whether the (CI') signal is present. At this time, the control microprocessor 20 outputs the video signal selection circuit 24.\(SO) signal (a in FIG. 3 SC) (step 15).

Next (step 16), when the number of occurrences of the <SC> signal is set to s-1, the video signal selection circuit 24 selects the signal from the internal signal source 23.

Next, the control microprocessor 20 sends the address/memory control signal generation circuit 34 (WS)
A signal is output (step 17). Next, the address/memory control signal generation circuit 34 receiving the (WS) signal sends (AD) to each field memory 2Q, 30.31.
) outputs a signal.

Here, if the area address by the (AD) signal is Y, then Y specifies the address for displaying on the small screen 0 in FIG. 8/1) The video composite signal from the internal signal source 23 converted into a digital signal by the converter 2627.28 is stored in the field memories 29, 3.
Written in 0.31.

After this, (Step 2), (Step 14).

The process moves to (step 8) via (step 7), and in this (step 8), the number of occurrences of the (SC) signal is determined.

At this point, the number of occurrences of the (SC) signal is set to s=1, so the process moves to (step 15). At this time, the control microprocessor 20 outputs the (SC) signal (FIG. 3 SC b) to the video signal selection circuit 24. Next, in step 16, the number of occurrences of No. 5 is set to s-2 (SO). Then, the video signal selection circuit 24 selects the signal from the external signal source 24.

Thereafter, the control microprocessor 20 sends the address/memory control signal generation circuit 34 (WS
) output a signal (step 17).

Next, the address/memory control signal generation circuit 34 receiving the (WS) signal outputs each field memory 29,
30.Outputs (AD) signal to 31.

Here, if the area address in the (AD) signal is Y, then Y specifies the address corresponding to the small screen p in FIG. The video composite signal from the external signal source 24 converted into a digital signal by the A/D converters 26, 27, 28 is stored in the field memories 29, 30, 31.
written to.

After this, (Step 2), (Step 14).

After (Step 7) and (Step 8), (Step 9)
In step 9, it is determined whether the number of times the (SC) signal has been generated is S.

At this point, the number of occurrences of the (SC) signal is s-2, so in step 19, the number of occurrences of the (SC) signal is set to s-0.

After this, the control microprocessor 20c,
VllF-UIIF tuner 21, video signal selection circuit 2
4 and address/memory control signal generation circuit 3
A (liver) signal (b in FIG. 3, 11P) is output to 4 (step 20).

Then, video signals corresponding to the small screens a to p in FIG. 6 are written into each field memory 29, 30, 31 again.

On the other hand, reading from each field memory 29, 30, 31 is performed by the ()ls) signal from the read synchronization generating circuit 33. That is, the address/memory control signal generation circuit 34 outputs the (WE) signal after receiving the (1?s)(,Ii) from the read synchronization generation circuit 33.

Here, (WE)1. , i, (IIP) signal and (
The time difference with the CU) signal is ■ Liver/UIIP tuner 21
Experimentally, it is necessary to have a vertical opening frequency of at least 1.5 times U (approximately 25 m5ec), although it depends on the performance of the

According to the (YD) signal from the address/memory control signal generation circuit 34, each field memory 29, 30.
The signal read out from each D/A converter 35 .
After being decoded into an analog signal at steps 36 and 37, it is output to the video signal output circuit 38.

As described above, in this embodiment, the control microprocessor 20 can control the selection operation of the video signal selection circuit 24 by the selection switching signal (SC), so that the internal signal source 22, the external signal source 23, and the broadcast The RF multiplied signals transmitted from the station can be displayed simultaneously on the small screens a-p.

FIG. 5 shows another embodiment in which the configuration of the channel search circuit of FIG. 1 is changed.

Note that parts common to those in the channel search circuit of FIG. 1 are given the same reference numerals and redundant explanations will be omitted.

As shown in the figure, the channel search circuit includes a control microprocessor 20a 611 that performs an H function of counting channel up signals (CU). A V-shaped/U-shaped tuner 21 is connected to the control microprocessor 20g.

VIIP-UIIF tuner 21 includes VIIP-U
A video signal selection circuit 24 that selects signals from an IIP tuner 21, an internal signal source 22, and an external signal source 23 is connected.

A decoder 25 and a synchronization separation circuit 32 are connected to the video signal selection circuit 24 .

The decoder 25 includes A/D converters 26, 27, 28
is connected. Each A/D converter 26°27.2
A field memory (PM) 29°30.31 is connected to 8. Each field memory 29, 30.31
includes an address/memory control signal generation circuit 34.
is connected.

In addition, each field memory 29, 30.31 has a D/A
Converters 35, 36, and 37 are connected. Each D/
A video signal output circuit 38 is connected to the A converters 35, 36, and 37.

In a channel search with such a configuration, when the channel search mode is entered, the VIA'-LIIIP tuner 21 is set to a in FIG. 6 by the (HP) signal from the control microprocessor 20a, similar to the channel search circuit in FIG. Select the channels to display. The video signal selection circuit 24 similarly selects the signal from the VIIP-UHP tuner 21, and the address/memory control signal generation circuit 34 similarly generates a write address signal (AD) corresponding to a in FIG. .

Furthermore, channel switching of the VIIP-UIIF tuner 21 is similarly performed by the (CU) signal.

Here, the control microprocessor 20a is
After generating the (IIP) signal, the number of times the (CI) signal is generated is counted, and a predetermined VIIP -
UIIP tuner 2] (a in Figure 6)
- Count 14) up to n. Next, the control microprocessor 20a interrupts the generation of the (ell) signal, and then generates the (SC) signal. After this,
The video (source signal selection circuit 24) performs a switching operation based on the (SC) signal.

Thereafter, when the writing of the image signal corresponding to the small screen a%p in FIG. 6 is completed, each field memory 29, 30.
31 is read from the read synchronization generating circuit 33 (
R3) is performed by a signal. Then, according to the address and the (yo) signal from the memory control signal generation circuit 34, the signals read from each of the two field memories 30.31 are decoded into analog signals by the respective D/A converters 35, 36, and 37. After that, the video signal output circuit 3
8.

Thus, in this embodiment, after the control microprocessor 20a generates the (IIP) signal, the (C
0) Count the number of signal occurrences] 7. Count the predetermined number of channels (14 from a to n in FIG. 6) of the Vlll'-UIIF tuner 21. Next, the control microprocessor 20a interrupts the generation of the (CI) signal, and then generates the (SC) signal. Thereafter, the video signal selection circuit 24 performs a switching operation based on the (SC) signal.

As a result, the I? transmitted from the internal signal source 22, the external signal source 23, and the broadcast station? The signals from the l'' signals can be simultaneously displayed on the small screens a-p.

``Effects of the Invention'' As described above, according to the channel search circuit of the present invention, the control means controls the selection operation of the signal source selection means, the storage operation of the storage means, and the address generation operation of the address generation means. Therefore, it is possible to sequentially select one signal source from a plurality of signal sources including signal sources from broadcasting stations and display them simultaneously on a plurality of small screens on which one display screen is divided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a channel search circuit showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the channel search circuit of FIG. 1, and FIG. 3 is a block diagram of the channel search circuit of FIG. Timing chart, 4th
The figure is a memory map showing the field memory in Figure 1, Figure 5 is a block diagram of a channel search circuit showing another embodiment in which the 1114 configuration of the channel search circuit in Figure 1 is changed, and Figure 6 is a conventional channel search circuit. FIG. 7 is a block diagram showing a conventional channel search circuit. 20...control microprocessor, 21.
... V-shaped IJIIF tuner, 22... Internal signal source, 23... External signal source, 24... Video signal selection circuit, 25... Decoder, 26, 27.23... A/D
Converter, 29.30.31...Field memory, 32...Synchronization separation circuit, 33...Reading synchronization generation circuit, 34...Address/memory control signal generation circuit, 35°36°7... D/A converter, 8... Video signal output circuit.

Claims (1)

[Claims] (1) Signal source selection means for sequentially selecting one signal source from a plurality of signal sources including signal sources from broadcasting stations, and signals from each signal source sequentially selected by the selection means at least for each field. a storage means for storing, and an address for generating an address corresponding to a plurality of small screens obtained by dividing one display screen into a plurality of parts when each of the signals is stored in the storage means and each signal is taken out from the storage means; A channel search circuit comprising: a generating means; and a control means for controlling an address generating operation of the address generating means and a selecting operation of the signal source selecting means.