JPH0213149A - Clock signal detection circuit - Google Patents

Abstract

PURPOSE:To attain fast discrimination of presence of a clock signal and to use the title circuit with no adjustment by providing a delay circuit retarding the clock signal and an OR gate ORing retarded clock signals. CONSTITUTION:Signals D1,D2 being the result of retarding a clock signal CK properly are outputted from a delay circuit 2. The signals D1, D2 are given to an OR gate 3. Thus, when the clock signal CK is inputted, since either of signals given to the OR gate 3 is logic 1, the output of the OR gate 3 goes to logic 1 and the input of the clock signal CK is discriminated. When the input of the clock signal CK is lost, the output signal of the delay circuit 2 goes to logic 0 and then the output of the OR gate 3 goes to logic 0, resulting that the absence of the input of the clock signal CK is discriminated. Thus, the discrimination of the absence of the clock signal is implemented quickly with no adjustment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a clock signal detection circuit used in digital communications and the like.

(Prior art) In digital communication, a clock signal and a clock signal are input, and in order to shape the waveform of the data signal, punched data is transmitted using the clock signal. In this case, the clock signal is input normally. It is necessary to determine whether the clock signal has been turned off and whether the clock signal has been disconnected. For this reason, a lock signal detection circuit as shown in FIG. 4 has conventionally been used.

As shown in the figure, this clock signal detection circuit includes an integrating circuit 9 consisting of a diode 6, a resistor 7, and a capacitor 8, a Nandt gate 10, and a resistor 11.

The diode 6 is connected to the terminal 5, a clock signal CK is input from the terminal 5, and the output side of the diode 6 is connected to the resistor 7 of the integrating circuit 9. One end of the capacitor 8 of the integrating circuit 9 is connected to the terminal 12. This integrating circuit 9 integrates the clock signal CK inputted through the diode 6 and sends the integrated signal S1 to the Nantes gate 10. The Nant gate 10 compares the signal S1 with an internally set threshold voltage vth, and sets the output signal S2 to "1" if the signal S1 exceeds the threshold voltage vth. When the output signal S2 becomes "1", the resistor 11
A voltage of 0 is generated across the .

Next, the operation of the conventional clock signal detection circuit will be explained based on the waveform diagram of FIG.

As shown in FIG. 5, a clock signal CK is inputted to the integrating circuit 9 via a diode.

Integrating circuit 9 integrates this clock signal CK and outputs signal S1 as shown in the figure. When time T1 has elapsed since the clock signal CK was input to the integrating circuit 9, the signal S1 outputted from the integrating circuit 9 becomes larger than the threshold voltage Vth in the Nant's gate 10, so the f-r of the Nand's gate 10 Signal S after delay time Tp has elapsed
2 becomes "1". In this state, a voltage vO is generated across the resistor 11, so by detecting this voltage VO it can be seen that the clock signal CK is being input.

At time t1, when the clock signal CK is no longer input, the signal S1 output from the integrating circuit 9 gradually decreases, and after time T2 has elapsed from time t1, the signal S1 becomes equal to the threshold voltage vth, and further, the delay time Tp As time elapses, the signal S2 becomes rOJ, and the voltage VO across the resistor 1 also becomes "O", indicating that the clock signal CK is no longer input.

However, the conventional clock signal detection circuit uses an integrating circuit 9, and it takes a long time for the capacitor 8 to be charged and for the capacitor 8 to be discharged. The time until it is determined that there is a CK input T ] 10 T p ,
There was a problem in that it took a long time (T2-4-T I) from when the human power for the clock signal CK was exhausted until it was determined that the input of the clock signal CK had disappeared, and the time for making that determination was long. .

Further, when the data bit rate is high and it is necessary to quickly determine the presence or absence of a clock signal, it is necessary to finely adjust the time constant of the integrating circuit 9.

(Problems to be Solved by the Invention) As described above, the conventional clock signal detection circuit has the problem that it takes a long time to determine the presence or absence of a clock signal, and the adjustment thereof is also tedious.

The present invention has been made in view of the above problems, and an object thereof is to provide a clock signal detection circuit that can quickly determine the presence or absence of a clock signal and can be used in one week.

[t57 of the invention] (Means for solving the problem) In order to achieve the above object, the present invention provides a delay circuit that delays a clock signal, and a logical sum of the clock signal delayed by the delay circuit. It is equipped with an or gate.

(Operation) In the present invention, the delay circuit outputs a signal obtained by appropriately delaying the clock signal. These signals are input to the OR gate. Therefore, if the clock signal is manually input, any of the signals input to the OR gate will be "1".
”, so the output of the OR gate becomes “1”, indicating that the clock signal is input manually. When the clock signal is no longer available, the output signal of the delay circuit also becomes rOJ, and accordingly, the output of the OR gate also becomes "0".
It can be seen that the clock signal is no longer input.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing the configuration of a clock signal detection circuit according to an embodiment of the present invention. As shown in the figure, this clock signal detection circuit is composed of a delay circuit 2 and an OR gate 3. As shown in FIG. The delay circuit 2 is connected to a terminal 1 from which a clock signal CK is input. The delay circuit 2 is
Signals D1 and D2 are output by delaying the clock signal CK. The OR gate 3 takes the logical sum of the signal D1 and the signal D2, and outputs an output signal to the terminal 4.

Next, the operation of this embodiment will be explained according to the waveform diagram shown in FIG.
explain.

When the clock signal CK is input to the delay circuit 2, the delay circuit 2 outputs a signal D1 which is the clock signal delayed by a delay time E1, and a signal D2 which is delayed by the delay time E. The OR gate 3 takes the logical sum of the signal D1 and the signal D2, so when the clock signal CK is input, its output signal S3 indicates "1", and the clock signal CK
Indicates that there is an input.

At time t1, when the clock signal CK is no longer input, the signals D1 and D change after time T3 has elapsed from that time t1.
2 are both "0". Therefore, the OR gate 3 sets its output signal S3 to rOJ after the delay time TTp of the OR gate 3 has elapsed. Therefore, it can be seen that the human power for the clock signal CK is no longer available.

Thus, according to this embodiment, when the clock signal CK is input manually, it is determined that the signal has been input after the delay time TTp of the OR gate 3 has elapsed, and the clock signal C
When clock signal K is disconnected, disconnection of clock signal CK is detected after time T3+TTp has elapsed. This time TTp and time T3+TTp are different from the conventional time TI+Tp and time T2+
It is much shorter than Tp. This is because the capacitor 8 is not used as in the conventional case, but only a digital circuit is used. Further, fine adjustment of the time constant of the integrating circuit 9 as in the conventional case is not necessary.

Note that, as shown in FIG. 3, the OR gate 3 may perform 21 detection based on the relationship between the data pit rate and the delay amount of the delay circuit 2. Therefore, the delay circuit 2 is required to have a maximum delay amount EN such that EN>1/2f (f: frequency of clock signal CK).

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a clock signal detection circuit that can quickly determine whether a clock is 1 or 6 and can be used without adjustment.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of a clock signal detection circuit according to an embodiment of the present invention, Fig. 2 is a waveform diagram of signals of various parts in an embodiment of the present invention, and Fig. 3 is a case in which erroneous detection is performed. FIG. 4 is a circuit diagram showing the configuration of a conventional clock signal detection circuit, and FIG. 5 is a waveform diagram of signals of part 8 of the conventional example. 2... Delay circuit, 3... OR gate Clock signal with clock signal disconnected Figure 2 Clock signal with clock signal disconnected Figure 3 Figure 4

Claims (1)

Claims: A clock signal detection circuit comprising: a delay circuit that delays a clock signal; and an OR gate that calculates the logical sum of the clock signals delayed by the delay circuit.