JPH02131030A - Data reception circuit - Google Patents

Data reception circuit

Info

Publication number
JPH02131030A
JPH02131030A JP28370588A JP28370588A JPH02131030A JP H02131030 A JPH02131030 A JP H02131030A JP 28370588 A JP28370588 A JP 28370588A JP 28370588 A JP28370588 A JP 28370588A JP H02131030 A JPH02131030 A JP H02131030A
Authority
JP
Japan
Prior art keywords
reception
level
amplitude limiter
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28370588A
Other languages
Japanese (ja)
Inventor
Sueo Konnai
末男 近内
Shigematsu Nagashima
繁松 長嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Platforms Ltd
NEC Corp
Original Assignee
NEC Corp
NEC AccessTechnica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC AccessTechnica Ltd filed Critical NEC Corp
Priority to JP28370588A priority Critical patent/JPH02131030A/en
Publication of JPH02131030A publication Critical patent/JPH02131030A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress all input signals up to a receptible level by providing an amplitude limiter on a reception side equipment such as a hybrid transformer in a data reception circuit in a data transmission equipment in which the reception side and the transmission side are separated. CONSTITUTION:When a signal received from a reception winding 40r of a hybrid transformer 40 is at a normal transmission level or below, an amplitude limiter 41 gives a reception signal to a reception section 42 without being operated. Moreover, when the reception signal is at a normal transmission level or over, Zener diodes 41a, 41b of the amplitude limiter 41 are operated. Thus, an excess input signal exceeding the reception capability is limited by the reception section 42 and the reception section 42 is always operated in the optimum state. Thus, the data reception circuit 4 of the amplitude limiter 41 of the simple constitution is operated in the optimum state and data transmission is attained in opposition to the data transmission equipment sending a signal with a level exceeding the conventional transmission level.

Description

【発明の詳細な説明】 [産業上の利用分野〕 本発明はデータ伝送装置に係わり、特に入力された受信
信号のレベルを全て受信可能レベルとするデータ受信回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device, and more particularly to a data receiving circuit that makes all input received signals at a receivable level.

〔従来の技術〕[Conventional technology]

従来、この種のデータ伝送装置は、通信回線に接続され
たハイブリッドトランス等により受信側と送信側とが分
離されている構成のものである。
Conventionally, this type of data transmission device has a configuration in which a receiving side and a transmitting side are separated by a hybrid transformer or the like connected to a communication line.

かかるデータ伝送装置は、データ受信回路を有している
。かかるデータ受信回路は、このデータ伝送装置の該浩
するシステムの送信波形レベルにしたがって構成されて
いる。すなわち、従来のデータ伝送装置のデータ受信回
路は、システムの送信波形レベルに基づき線路等化を行
っている。このため、自己の送信波形より大きなレベル
の波形がデータ受信回路の受信部に入力されときに、そ
の受信レベルが異常に大きいき線路等化部の動作範囲を
超え、受信不能となる。
Such a data transmission device has a data receiving circuit. This data receiving circuit is configured according to the transmission waveform level of the extensive system of this data transmission device. That is, the data receiving circuit of the conventional data transmission device performs line equalization based on the transmission waveform level of the system. Therefore, when a waveform with a higher level than its own transmission waveform is input to the reception section of the data reception circuit, the reception level exceeds the operating range of the feeder line equalization section, which is abnormally high, and reception becomes impossible.

さらに、受信部に対する入力波形レベルは、システムの
送信波形で規定されており、従来のデータ伝送装置のデ
ータ受信回路では過大な入力波形は、信号としなくても
良いように動作していた。
Furthermore, the input waveform level to the receiving section is defined by the transmission waveform of the system, and the data receiving circuit of the conventional data transmission device operates so that an excessively large input waveform does not need to be treated as a signal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、最近では、耐雑音性の向上等を求めて、
システムの伝送波形のレベルを従来装置のものより大き
くする必要が生じてきている。このため、現に動作中の
データ伝送装置と送信波形のレベルの大きく取れるデー
タ伝送装置とを接続して使用しようとすることが求めら
れてきている。
However, recently, in pursuit of improved noise resistance,
It has become necessary to increase the level of the transmitted waveform of the system over that of conventional devices. For this reason, there has been a demand for connecting and using a data transmission device that is currently in operation and a data transmission device that can provide a high level of transmitted waveform.

本発明は上述した欠点を解決するためになされたもので
、入力信号を全て受信可能なレベルまで抑えるようにし
たデータ受信回路を提供することを目的とする。
The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a data receiving circuit that suppresses all input signals to a receivable level.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するために、本発明のデータ受信回路
は、通信回線に接続されたハイブリッドトランス等によ
り受信側と送信側とが分離されているデータ伝送装置に
おけるデータ受信回路において、ハイブリッドトランス
等の受信側に振幅制限器を設けたことを特徴とするもの
である。
In order to achieve the above object, the data receiving circuit of the present invention is a data receiving circuit in a data transmission device in which a receiving side and a transmitting side are separated by a hybrid transformer or the like connected to a communication line. The device is characterized in that an amplitude limiter is provided on the receiving side of the signal.

本発明によれば、ハイプリントトランス等の受信側に振
幅制限器を設けているので、従来受信不能であった自己
の受信波形レベルより大きなレベルの波形も受信可能と
なる。
According to the present invention, since an amplitude limiter is provided on the receiving side of a high print transformer or the like, it becomes possible to receive waveforms having a higher level than the own received waveform level, which was conventionally impossible to receive.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明のデータ受信回路の実施例を示す回路図
である。
FIG. 1 is a circuit diagram showing an embodiment of the data receiving circuit of the present invention.

同図において、データ伝送装置2は、データ受信回路4
と、送信部6と、信号処理部8とを備えている。
In the figure, the data transmission device 2 includes a data receiving circuit 4.
, a transmitter 6 , and a signal processor 8 .

データ受信回路4は、ハイプリントトランス40と、ツ
ェナーダイオ−)’418.41b・抵抗41rからな
る振幅制限器41と、受信部42とから構成されている
。ハイブリッドトランス40は、−次巻線40pと、受
信巻線4Orと、送信巻線40tとを備えている。−次
巻線40pは端子Tp、Tmを介してディジクル回線1
0に接続されている。送信巻線40tは、送信部6の出
力α;1:に接続されている。受信巻線40rは、振幅
制限器41に接続されている。振幅制限器41は、抵抗
41rと、ツェナーダイオード41a、41bを逆方向
に直列接続された直列回路とを逆り字状に接続して構成
されている。振幅制限器41のツェナーダイオード41
a、41bの両端は受信部42の入力端に接続されてい
る。受信部42の出力端は、信号処理部8に接続されて
いる。受信部42は、送信信号のレベルから途中線路に
より減衰した微小レベルまで幅広いレベル範囲の入力信
号に対して受信する能力が必要とされている。
The data receiving circuit 4 includes a high print transformer 40, an amplitude limiter 41 consisting of a Zener diode (418.41b) and a resistor 41r, and a receiving section 42. The hybrid transformer 40 includes a negative winding 40p, a receiving winding 4Or, and a transmitting winding 40t. - The next winding 40p is connected to digital line 1 via terminals Tp and Tm.
Connected to 0. The transmitter winding 40t is connected to the output α;1: of the transmitter 6. The receiving winding 40r is connected to an amplitude limiter 41. The amplitude limiter 41 is configured by connecting a resistor 41r and a series circuit in which Zener diodes 41a and 41b are connected in series in opposite directions in an inverted cursor shape. Zener diode 41 of amplitude limiter 41
Both ends of a and 41b are connected to the input end of the receiving section 42. An output end of the receiving section 42 is connected to the signal processing section 8. The receiving section 42 is required to have the ability to receive input signals in a wide range of levels from the level of the transmitted signal to the minute level attenuated by the intermediate line.

このため、受信部42は、受信レベルが低いレベル領域
側に伸ばすようになっており、送信レベル以上の入力信
号に対しては動作を保障していない。
For this reason, the receiving section 42 is designed to extend toward a region where the receiving level is low, and does not guarantee operation for input signals higher than the transmitting level.

また、信号処理部8は、送信部6の入力端に接続されて
いる。信号処理部8には、制御および状態等を伝送する
信号線12が接続されている。
Further, the signal processing section 8 is connected to the input end of the transmitting section 6. A signal line 12 for transmitting control, status, etc. is connected to the signal processing unit 8.

このように構成された実施例の作用を説明する。The operation of the embodiment configured in this way will be explained.

まず、ハイブリッドトランス40の受信巻線40rから
受信された信号が通常の送信レベル以下の場合、振幅制
限器41は、なんら動作することなく受信信号を受信部
42に与える。受信部42は、この受信した信号を所定
の動作で処理し、信号処理部8に与える。
First, when the signal received from the reception winding 40r of the hybrid transformer 40 is below the normal transmission level, the amplitude limiter 41 provides the reception signal to the reception section 42 without any operation. The receiving section 42 processes the received signal in a predetermined operation and provides it to the signal processing section 8.

一方、ハイブリッドトランス40の受信巻線40rから
受信された信号が通常の送信レベル以上の場合であると
、振幅制限器41は、ツェナーダイオード41a、41
bが動作することにより、受信部42に受信能力以上の
過大入力信号を制限することになる。これにより、受信
部42は、常に、最適状態で動作することになる。
On the other hand, if the signal received from the reception winding 40r of the hybrid transformer 40 is higher than the normal transmission level, the amplitude limiter 41 connects the Zener diodes 41a, 41
By operating b, the receiving section 42 is restricted from receiving an excessive input signal that exceeds its reception capability. Thereby, the receiving section 42 always operates in an optimal state.

このように本実施例によれば、簡単な構成の振幅制限器
41で、データ受信回路4を最適状態で動作させること
ができ、かつ通常の送信レベル以上のレベルで送信する
データ伝送装置と対向してデータ伝送を行うことができ
ることになる。
As described above, according to the present embodiment, the data receiving circuit 4 can be operated in an optimal state with the amplitude limiter 41 having a simple configuration, and the data receiving circuit 4 can be operated in an optimal state, and the amplitude limiter 41 can be operated in an optimal state, and the data receiving circuit 4 can be operated in an optimal state. data transmission.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、受信信号のレベルを振幅
制限器で受信可能なレベル以下に全て抑えるようにした
ので、あらゆる型式のデータ伝送装置と対向して通信を
行うことができるという効果がある。
As explained above, the present invention suppresses the level of all received signals below the level that can be received by the amplitude limiter, so it has the advantage of being able to communicate with all types of data transmission devices. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す回路図である。 2・・・・・・データ伝送装置、 4・・・・・・データ受信回路、8・・・・・・信号処
理部、41・・・・・・振幅制限器、 41a、41b・・・・・・ツェナーダイオード、41
r・・・・・・抵抗。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. 2... Data transmission device, 4... Data receiving circuit, 8... Signal processing unit, 41... Amplitude limiter, 41a, 41b... ... Zener diode, 41
r...Resistance.

Claims (1)

【特許請求の範囲】[Claims] 通信回線に接続されたハイブリッドトランス等により受
信側と送信側とが分離されているデータ伝送装置におけ
るデータ受信回路において、前記ハイブリッドトランス
等の受信側に振幅制限器を設けたことを特徴とするデー
タ受信回路。
A data receiving circuit in a data transmission device in which a receiving side and a transmitting side are separated by a hybrid transformer or the like connected to a communication line, characterized in that an amplitude limiter is provided on the receiving side of the hybrid transformer, etc. receiving circuit.
JP28370588A 1988-11-11 1988-11-11 Data reception circuit Pending JPH02131030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28370588A JPH02131030A (en) 1988-11-11 1988-11-11 Data reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28370588A JPH02131030A (en) 1988-11-11 1988-11-11 Data reception circuit

Publications (1)

Publication Number Publication Date
JPH02131030A true JPH02131030A (en) 1990-05-18

Family

ID=17669014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28370588A Pending JPH02131030A (en) 1988-11-11 1988-11-11 Data reception circuit

Country Status (1)

Country Link
JP (1) JPH02131030A (en)

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