JPH02130052A - Packet data control processing system for transmission loop - Google Patents

Abstract

PURPOSE:To detect the presence/absence of the abnormality of a transmission loop by using a memory means using the input/output format of first-in and first-out by a supervisor node and providing a bit state detection means to detect the flag state of the specified bit of a packet to be housed in this memory means. CONSTITUTION:A memory using the input/output format of first-in and first-out is used as a memory means 23 with which a supervisor node 3 is provided. Consequently, a logic circuit to select a conventional RAM chip and a logic circuit to specify an address are eliminated and the frame buffer memory of the supervisor node 3 can be mounted with a simple circuit constitution. Thus, the control processing of packet data which a supervisor node executes can be realized at high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a transmission loop packet data control processing method in a network having a loop configuration, the purpose of this method is to realize packet data control processing with a simple circuit configuration. A supervisor node that is connected to and executes packet data relay processing and transmission loop abnormality detection processing uses first-in, first-out input/output format memory means as a memory means for executing the processing. In addition, by providing a bit state detection means for detecting the flag state of a specified bit of a packet stored in a memory means having this input/output format, a transmission loop that is executed during network initialization processing is provided. The configuration is such that it is possible to detect the presence or absence of an abnormality.

(Industrial Application Field) The present invention relates to a transmission loop packet data control processing method in a network having a loop configuration such as used in a local area network, and in particular, realizes packet data control processing with a simple circuit configuration. The present invention relates to a packet data control processing method for a transmission loop that enables transmission loops to be processed.

In a local area network with a loop configuration, as shown in Figure 4, there is a transmission loop 1 that forms a transmission path using an optical cable, and multiple networks are connected to this transmission loop 1 and send and receive data in packets to each other. A node 2 that executes predetermined processing, and a supervisor node 3 that is connected to this transmission loop 1 and executes packet data control processing related to generation of a reference clock, detection of abnormalities in the transmission path of this transmission loop 1, etc. It will be composed of The packet data control process executed by the supervisor node 3 is configured so that it can be realized with the simplest possible circuit configuration (necessary).

[Conventional technology]

FIG. 5 shows the system configuration of the supervisor node 3. As shown in this figure, the supervisor node 3 includes a receiving repeater 31 that performs optical-to-electrical conversion of received frame data (a set of packet data), and a transmitting A transmission repeater 32 performs electrical-to-optical conversion of frame data to be transmitted and received; a code converter 33 performs code conversion of frame data for transmission and reception; and an off-scillator 34 that generates a clock for transmission and reception processing. It is composed of a receiving circuit 35 for receiving frame data, a timing generating circuit 36 for generating a timing signal for the receiving circuit 35, and a frame buffer memory (FBM) 37 for controlling frame data. .

FIG. 6 shows the circuit configuration of the frame buffer memory 37, in which reference numeral 28 denotes a frame generation circuit section, which is a transmission clock supplied from the oscillator 34 during initialization processing of the network constituted by the transmission loop 1. 23 is a memory means which is notified by the timing generation circuit 36 that the transmission loop 1 has been synchronized. 27 is a transmission selector switch unit that sequentially writes frame data received in synchronization with the reception clock supplied from the code conversion unit 33; A control circuit section 29 processes one of the frame data written in the memory means 23 so as to send it to the transmission loop 1, and controls the process of writing frame data to the memory means 23 and transmits the frame data. Controlling the selection process of the selector switch unit 27;
Frame generation circuit unit 28 that executes control of successive output processing of frame data from frame generation circuit unit 28 or memory means 23 and circulates through transmission loop 1
By checking the transmission frame data of
The processing is performed to detect the presence or absence of an abnormality.

The supervisor node 3 configured in this manner sets the transmission selector switch unit 27 to the frame generation circuit side during network initialization processing, and sends frame data for transmission loop check to the transmission loop 1. When it is confirmed that this frame data, which will be written into the memory means 23 by returning via the transmission loop 1, is the same as that sent out, it is determined that the transmission loop 1 is normal. Then, the transmission selector switch section 27 is set to the memory means 23 side.

Through this setting process, the frame data sent via the transmission loop 1 is sequentially stored in the memory means 23 and is processed so as to be sent to the transmission loop 1 according to the storage order, so that the data is transferred between nodes. Transmission and reception will be executed.

The memory means 23 of this frame buffer memory 37 is
Conventionally, it has been configured with RAM chips prepared according to the number of bits of packet data.

Then, the packet data writing process is performed by sequentially selecting these RAM chips in synchronization with the reception of packet data, and writing the selected RA chips according to the address information specified by a separately prepared address counter.
It was executed by writing bit information to the M chip. In addition, the successive packet data processing is performed by sequentially selecting these RAM chips in synchronization with the transmission of packet data, and reading bit information from the selected RAM chips according to the address information indicated by the address counter. was being executed. Further, the process of detecting the presence or absence of an abnormality in the transmission loop l has been executed by determining whether or not the read packet data is the same as that sent out during the packet data successive output process.

(Problem to be Solved by the Invention) However, in the configuration of such a conventional technology, it is necessary to prepare a plurality of RAM chips, and various logic circuits (for example, , a write counter and a read counter for selecting a RAM chip, an address counter for instructing the address of a RAM chip, etc.) In the conventional technology, the circuit configuration of the frame buffer memory 37 is complicated. There was a problem with becoming.

Since the circuit configuration becomes complicated, the memory means 2
Therefore, there was a problem in that the access speed to 3 was slow, which hindered the realization of a local area network that required high-speed processing.

The present invention has been made in view of the above circumstances, and is a transmission loop that enables a frame buffer memory to be implemented with a simple circuit configuration and enables high-speed control processing of packet data executed by a supervisor node. The purpose is to provide a packet data control processing method.

Means to solve CRIJi] FIG. 1 is a diagram showing the basic configuration of the present invention.

As explained in FIG. 4, 1 in the figure is a transmission loop, 2 is a node, and 3 is a supervisor node.

This supervisor node 3 includes a receiving circuit section 21, a write control circuit section 22, a memory means 23, and a bit state detecting means 2.
4, a succession control circuit section 25, a transmission circuit section 2G, a transmission selector switch section 27, and a frame generation circuit section 2.

The receiving circuit section 21 receives the frame data sent via the transmission loop 1 and processes the received signal to notify the write control circuit section 22. When the receiver receives the received frame data, it sends a write pulse to the memory means 23 to write the received frame data to the memory means 23, and the memory means 23 performs a first-in/first-out input/output format. The control circuit unit 25 stores frame data in packet units, and reads an available signal when the stored data reaches a predetermined amount.
The focus state detection means 24 performs processing to detect the flag state of the designated bit of the packet stored in the memory means 23, and the successive control circuit section 25 performs processing to notify the following:
When the available signal is received, the oldest packet stored in the memory means 23 is read out by sending a series of pulses to the memory means 23, and a predetermined packet is set according to the detection result of the bit state detection means 24 during this series of processing. process to detect that the packet has returned,
The transmitting circuit unit 26 processes the read packet to send it to the transmission loop 1 when the memory is used, and the transmitting selector switch unit 27 selects the transmitting circuit unit 26 according to the detection result of the successive control circuit unit 25. The frame generating circuit unit 2
8 generates and transmits a packet with a flag set in a specific designated bit when the network is initialized.

[Effect]

In the present invention, since a memory having a first-in/first-out input/output format is used as the memory means 23 provided in the supervisor node 3, there is no need to specify address information (the received packets are simply Then, transmission loop 1
If it is confirmed that there is no abnormality, the transmission selector switch section 27 is set to the transmission circuit section 26 side, and the oldest packet is automatically read out from the memory means 23 in order. It will be sent to loop 1. Further, since the bit state detection means 24 detects the flag state of the specified bit of the packet stored in the memory means 23, the return of the packet during the initialization process is detected, so that an abnormality in the transmission loop 1 can also be detected. This can be accomplished directly and easily.

As described above, in the present invention, since a memory having a first-in/first-out input/output format is used as the memory means 23, a logic circuit for selecting a RAM chip and a logic circuit for addressing a conventional RAM chip are used. No logic circuit is required, and the frame buffer memory 37 of the supervisor node 3 can be implemented with a simple circuit configuration. From now on, it will be possible to implement high-speed packet data control processing executed by supervisor nodes.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

In FIG. 2 showing a configuration diagram of an embodiment of the present invention, the same parts as those explained in FIG. 1 are indicated by the same symbols. 21a is a first circuit corresponding to the receiving circuit section 21 in FIG.
a group of flip-flop circuits which convert frame data received in serial format into parallel format packet by packet and store it in the memory means 23;
Reference numeral 25a denotes a continuation control section constituting the continuation control circuit section 25 in FIG. 25b is a transmission control unit that also constitutes the continuous output control circuit unit 25 in FIG. Depending on the result, processing is performed to switch the selection mode of the transmission selector switch unit 27.

Reference numeral 26a designates a second flip-flop circuit group constituting the transmitting circuit section 26 in FIG. The third flip-flop circuit group that constitutes the transmitting circuit section 26 in FIG. 26c is a first flip-flop circuit that also constitutes the transmission circuit section 26 in FIG. 28b is a frame counter constituting the frame generation circuit section 28 in FIG. 1, which defines the frame length of frame data to be generated;
A frame generation circuit constituting the frame generation circuit section 28 in the figure, which processes to generate a packet with a flag set in a specific designated bit used for detecting the presence or absence of an abnormality in the transmission loop l; 28c is also the first
This is a second flip-flop circuit that constitutes the frame generation circuit section 28 in the figure, and processes the frames generated by the frame generation circuit 28b so as to transmit them in serial format.

As explained in FIG. 1, the memory means 23 of the present invention is constituted by a memory having a first-in, first-out input/output format. Therefore, there is no need for a conventional logic circuit for selecting a RAM chip or for specifying an address.

Next, the processing contents of the present invention configured as described above will be explained.

During network initialization processing, the transmission control n section 25b sets the transmission selector switch section 27 to the second flip-flop circuit 28c. Through this selection process, the frame data for checking the transmission loop 1 generated by the frame generation circuit 28b (a flag is set in the specified bit of the first packet) is
The signal is sent to the transmission loop l via the flip-flop circuit 26c. If the transmission loop 1 is normal, the check frame data sent out in this manner will go around the transmission loop 1 and return, and will be received by the first flip-flop circuit group 21a.

When the first flip-flop circuit group 21a receives the returned check frame data, it notifies the write control circuit section 22 of a reception signal (a in the figure). Upon receiving this notification, the write control circuit section 22 generates a write pulse (
By generating b) in the figure, the received check frame data is processed to be stored in the memory means 23 in units of packets. At this time, the memory means 23
Since it is composed of memory that takes a first-in, first-out input/output format, there is no need to specify an address, and the packets are simply stored in a format in which the packets are converted to parallel format and packed in order. become.

In this way, when the amount of packets stored in the memory means 23 reaches a predetermined amount (for example, the maximum amount that can be stored), the memory means 23 continuously outputs an available pull signal (C in the figure). The control unit 25a is notified. Upon receiving this notification, the succession control section 25a reads out the oldest packet stored in the memory means 23 by generating a succession pulse (d in the figure), and sends it to the second flip-flop circuit group 26a. It will be processed to latch. Since the memory means 23 is constituted by a memory having a first-in, first-out input/output format, this process of successively processing the oldest packet is executed simply by reading it. Then, the successive control section 25
When a has finished reading l packets, it transmits a latch signal (e in the figure) to transfer the packet latched by the second flip-flop circuit group 26a to the third flip-flop circuit group 26b. .

Furthermore, the continuation control unit 25a reads the detection result of the bit state detection means 24 in synchronization with this continuation processing, and
The reading result is processed to be notified to the transmission control unit 25b (f in the figure). By the process of reading the detection result of the bit state detection means 24 executed by the successive control section 25a, the transmission control section 25b determines that the packet read from the memory means 23 is a check packet generated by the frame 5grDilsb. You will be able to judge whether it is there or not.

From now on, when the transmission control unit 25b determines that the packet read from the memory means 23 is a check packet generated by the frame generation circuit 28b, it determines that the transmission loop l is normal, and transmits the packet. The selector switch section 27 is connected to the third flip-flop circuit group 26.
Processing is performed to switch to side b. In this way, when it is determined that the transmission loop 1 is normal through the network initialization process, the memory means 23 stores the packets in the order of the packets flowing through the transmission loop 1 according to the first-in, first-out input/output format. Frame data will be transmitted and received along the same lines.

In order to clarify the difference between the circuit configuration of the frame batzer memory of the supervisor node 3 according to the present invention and that of the prior art, FIG.
Components corresponding to those described in FIG. 2 are indicated by the same symbols.

As explained in the [Problems to be Solved by the Invention] section above, in the prior art, when accessing the memory means 23, a write counter, a read counter, and an address counter were required, so the circuit configuration was It was extremely complex.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need for a conventional logic circuit for accessing the memory means, so that the frame buffer memory of the supervisor node can be implemented with a simple circuit configuration. . From now on, it will be possible to access memory means at high speed, reliability will be improved, and there will be advantages in terms of cost.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle configuration of the present invention. Figure 2 is a diagram of an embodiment of the invention. Figure 3 is a diagram of the prior art. Figure 4 is a system configuration diagram of a local area network. Figure 5 is a supervisor diagram. FIG. 6 is a diagram showing the system configuration of the node. FIG. 6 is a diagram showing the circuit configuration of the frame buffer memory. In the figure, 1 is a transmission loop, 2 is a node, 3 is a supervisor node, 21 is a receiving circuit section, 22 is a write control circuit section, 2
3 is a memory means, 24 is a bit state detection means, 25 is a continuous control circuit section, 26 is a transmission circuit section, 27 is a transmission selector switch section, and 2 is a frame generation circuit section.

Claims (1)

[Claims] A transmission loop (1) that forms a transmission path with a loop configuration, and a plurality of nodes that are connected to the transmission loop (1) and execute predetermined processing by mutually transmitting and receiving data in packets. (2), and a supervisor node (1) connected to the transmission loop (1) to detect abnormalities in the transmission loop (1).
3), and the supervisor node (3) includes a memory means (23) for sequentially storing received packets, and sequentially transmits the packets stored in the memory means (23). The configuration is configured to realize the transmission and reception of packets between the nodes (2), and the supervisor node (3) sets a flag for identification in a specific designated bit and sends the packet during network initialization processing. processing to transmit, and processing to determine the presence or absence of a flag in a designated bit of the packet that is to be returned via the transmission loop (1) and stored in the memory means (23); In the transmission loop packet data control processing method for detecting the presence or absence of an abnormality in the transmission loop (1), the supervisor node (3) serves as the memory means (23) for first-in/first-out input. In addition to using memory means that takes an output format, it also includes bit state detection means (24) for detecting the flag state of a designated bit of a packet to be stored in the memory means (23) that takes an input/output format. A transmission loop packet data control processing method characterized by comprising: