JPH02129754A - Common memory access system - Google Patents

Abstract

PURPOSE:To easily detect a holding state or an in-loop state by allowing a timing circuit to monitor the interruption of a counter value change detecting signal for a prescribed time or more and allowing an abnormality processing selecting circuit to select simple alarm processing or the setting of a CPU normal flag. CONSTITUTION:In a multi-CPU system, each of CPUs 1, 2 is provided with a counter output function, a counter value change detecting device 2i and a timing circuit 2t for inputting a counter value change detecting signal. Since the operating state of each CPU 1 or 2 is outputted as a counter signal, a change in the counter value can be detected by the device 2i and the holding state or in-loop state of the transmission side CPU can be easily detected by the timing circuit 2t for inputting the detecting signal after turning on the CPU normal flag.

Description

[Detailed description of the invention] [Industrial application field]

This invention utilizes a plurality of central processing units (hereinafter referred to as C
Related to a common memory access method for a common storage device in a multi-CPU system in which CPUs (referred to as PUs) are organically coupled and have a common input/output signal device and storage device in addition to the input/output signal device and storage device unique to each CPU. It is.

[Conventional technology]

Fig. 2 is a block diagram showing an example of a general multi-CPU system, and Fig. 3 is a block diagram showing a common memory access method in the multi-CPU system shown in Fig. 2, which is described in Japanese Patent Application No. 59-239430. It is. Second
In the figure, l is the first CPU system and 2 is the second CPU system.
This is the U system. The first CPU system 1 includes a first CPU 1a, a storage device 1b provided exclusively for the first CPU1a, and an input/output signal device IC provided exclusively for the first CPU1a. Further, the second CPU system 2 has a second CPU system 2.
It is composed of a PU 2a, a memory bag W2b provided exclusively for the second CPU 2a, and an input/output signal device 2c provided exclusively for the second CPU 2a. 3a is the first CP provided in the first cPU system l.
U1a and the second CPU provided in the second CPU system 2.
Multipath controllers 3b and 3c that perform control to organically connect the CPU 2a are a common storage device and a common input/output device that operate under the control of the multipath controller 3a. Next, the operation will be explained. The common storage device 3b is the 1st C
It is a storage device that is commonly used by the PU1a and the second CPU2a, and is used for information transmission between the first CPU1a and the second CPU2a. The block diagram shown in FIG. 3 shows information transmission from the first CPU system 1 to the second CPU system 2. 1
Information can be transmitted to the CPU system 1 in exactly the same way. Here, the operation of the block diagram shown in FIG. 3 will be explained. First, the first CPU system 1 on the sending side supplies information to be transmitted to the second CPU system 2 to the common storage device 3b by executing a program. Further, the counter output program provided at the end of the program transfers the counter signal 3bc to a specific area in the common storage device 3b. On the other hand, the second CPU system 2 on the receiving side stores the value of the current memory 2e in the previous memory 2f and stores the counter signal 3bc in the current memory 2f every time it executes one scan of the program.
Store in e. Next, the counter value change detection device 21
A change in the counter value is detected by comparing the contents of the current memory 2e and the previous memory 2f. Next, the H/W in the first CPU system 1 on the sending side
(Hardware) When the normal signal 1d is turned on and the counter value change detection device 21 detects a change in the counter value, the CPU normal flag 2h on the sending side is turned on, and on this condition, the data is transferred from the first CPU system 1 to the common memory. Device 3
The data transferred to and stored in B is read out. Here, turning off the CPU normal flag 2h on the sending side means the H/W normal signal 1d in the first CPU system 1 on the sending side.
The condition is that it is turned off. In other words, if there is an H/W error in the first CPU system l and the power is turned off, the CPU normal flag 2h will be turned off. Also, at the time of recovery, the H/W normal signal 1d will be turned off immediately. However, since the counter signal 3bc does not change until the first CPU system 1 scans the program once, the erroneous data (old data) is not read out by the above procedure.

[Problem to be solved by the invention]

Since the conventional common memory access method is configured as described above, once the CPU normal flag 2h is turned on, it will not be turned off until the H/W normal signal 1d falls, and along with this, the CPU normality flag 2h is turned on. There was a problem that the flag 2h remained on. This invention was made to solve the above-mentioned problems, and includes a common memory that can detect a hold state or an in-loop state other than an abnormality of H/W for the CPU on the sending side, as well as a CPU normal flag. The purpose is to obtain an access method.

[Means to solve the problem]

The common memory access method according to the present invention is a multi-C
In the PU system, each CPU has a counter output function,
By providing a counter value change detection device and a time limit circuit that receives the counter value change detection signal as input, the transmission side CPU
This is to detect the hold state and in-loop state.

[Effect]

The common memory access method in this invention is based on the CPU
Since the operating status of is output as a counter signal,
A change in the counter value is detected by a counter value change detection device, and a time limit circuit that receives this detection signal as input can easily detect the hold state or in-loop state of the transmitting CPU after the CPU normal flag is turned on. become.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is the first CPU system, 2 is the second CPU system
3b is a common storage device, and 3bc is a counter signal stored in a specific area in the common storage device 3b. Further, in the second CPU system 2, 2e is a current memory, 2f is a previous memory, 21 is a counter value change detection device, and 2h is a CPU normal flag, and these structures are the same as in FIG. 2p is counter value change detection device 2
1 is a pulse cut circuit which receives the detection signal as input, 2t is a time limit circuit which receives the output of pulse cut circuit 2p as input, 2s
is an abnormality processing selection circuit which receives the output of the time limit circuit 2t as an input. The difference from FIG. 3 is that a pulse cut circuit 2p, a time limit circuit 2, and an abnormality processing selection circuit 2s are added. The operation of the block diagram shown in FIG. 1 will be explained below. First, the first CPU system 1 on the sending side supplies information to be transmitted to the second CPU system 2 to the common storage device 3b by executing a program. Further, the counter output program provided at the end of the program transfers the counter signal 3bc to a specific area in the common storage device 3b. On the other hand, every time the second CPU system 2 on the receiving side executes one scan of the program, the value of the current memory 2e is stored in the previous memory 2r, and the counter signal 3bc is stored in the current memory 2r.
Store it. Next, the counter value change detection device 21
A change in the counter value is detected by comparing the contents of the current memory 2e and the previous memory 2f.・Next, the H/W in the first CPU system l on the sending side
The normal signal 1d is turned on, and the counter value change detection device W2
1 detects a change in the counter value, the CPU normal flag 2h on the sending side turns on, and with this as a condition, the 1st C
Data transferred from the PU system 1 to the common storage device 3b and stored therein is read out. Here, C on the sending side
The condition for turning off the PU normal flag 2h is that the H/W normal signal 1d in the first CPU system 1 on the transmitting side is turned off. That is, if there is an H/W abnormality in the first CPU system 1 and the power is turned off, the CPU normality flag 2h will be turned off. Moreover, at the time of recovery, the H/W normal signal 1d turns on immediately, but the counter signal 3bc
Because the first CPU system 1 does not change the program until it scans the program once, incorrect data (
old data) will not be read. Next, the change detection signal output from the counter value change detection [i2i is converted into a counter value change detection signal in the pulse cut circuit 2P, and is supplied to the time limit circuit 2t. The timer circuit 2L operates as follows every time the manually input signal is turned on.
It starts after being reset, but if the supply of input signals is interrupted for a certain period of time, the output turns on due to timeout. The output signal of the time limit circuit 2t is input to the abnormality processing selection circuit 2s, and a case where the signal is simply treated as an alarm or a case where the signal is input to the reset terminal of the CPU normal flag 2h is selected. This results in
The first CPU provided in the first CPU system 1 on the sending side
The H/W normal signal 1d generated from the CPU does not drop,
A hold or in-loop state is detected by software, and in that case, the abnormality processing selection circuit 2S selects whether to treat it as an alarm or to drop the CPU normal flag 2h. Therefore, in this configuration, since the counter value change detection signal is monitored by the timer circuit, it is easily detected that the CPU on the transmitting side is in the hold state or in-loop state. . In addition, in the above embodiment, in order to simplify the explanation, only the case where it is applied to a multi-system composed of two CPUs is shown, but even in a multi-system using three or more CPUs, each CPU By providing one counter output function for each CPU and a special circuit for the counter value detection circuit 1 of the other CPU, the same effects as in the above embodiment can be obtained.

【Effect of the invention】

As described above, according to the present invention, the time limit circuit monitors when the supply of the counter value change detection signal is interrupted for a predetermined period of time or more, and determines whether to simply treat it as an alarm or to drop the CPU normal flag. is selected by the abnormality processing selection circuit, so even if the CPU on the transmitting side does not become H/W abnormal, it can be easily detected that the CPU is in the hold state or in-loop state.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional multi-CPtJ system, and FIG. 3 is a block diagram showing a conventional common memory access system. ■ is the first CPU system, 2 is the second CPU system,
2e is a current memory, 2f is a target memory, 21 is a counter value change detection device, 2p is a pulse cut circuit, 2t is a time limit circuit, 2s is an abnormality processing selection circuit, and 3b is a common storage device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (2 others)

Claims (1)

[Claims] Multiple CPU systems are organically combined, and each CPU
Multi-CPU access between system-specific storage and common storage shared by each CPU system
In the common memory access method of the system, each of the CPU systems outputs a counter value indicating that its own CPU is in a run state, and is equipped with a counter value change detection device, and the counter output of the other CPU system is output to the common memory. The count value stored in this memory area is read every time the other CPU system scans the program, and the counter value change detection device detects the change in the counter value between the previous time and this time. Based on this detection result, the signal output from the common storage device is determined to be normal, and when the supply of the counter value change detection signal is interrupted for a certain period of time, a time limit circuit determines that the signal output from the common storage device is normal. A common memory access method characterized by outputting an alarm signal in response to a signal.