JPH02128577A - Vertical deflecting circuit - Google Patents

Abstract

PURPOSE:To eliminate the DC shifting of a sigmoid distortion correcting voltage and to obtain accurate interlacing without having a pairing, etc., by superimposing a correcting signal upon a vertical deflecting signal while a shift is occurred. CONSTITUTION:Vertical deflecting signals are supplied to an input terminal 1 which is connected with one input terminals 2a of a comparator 2 and the comparator 2 is connected with a vertical deflecting coil 4 through an amplifier 3. An S-shaped correction circuit 7 is connected between the coil 4 and earth, and is connected with the other input terminal 2b of the comparator 2 through a feedback circuit 8. Therefore, the DC shift of a sigmoid distortion correcting voltage can be corrected by superimposing a correcting signal of the level corresponding to a shifting quantity upon period signals for sigmoid distortion correction or vertical deflecting signals in synchronism with the vertical deflecting period in which the shift is occurred, and interlacing of a pairing, etc., can be prevented from being deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical deflection circuit for controlling the scanning line drive of a cathode ray tube of, for example, a television receiver.

[Summary of the invention]

The present invention relates to a vertical deflection circuit for controlling the vertical deflection of a cathode ray tube of a television receiver, for example, and is suitable for use in a system in which the length of the deflection period is different for each vertical deflection period. The DC shift of the S-shaped correction signal in a system where the length of the deflection period differs for each deflection period is corrected by superimposing a correction signal synchronized with the vertical deflection period in which this DC shift occurs on the feedback signal, thereby improving interlace. It is measured by

[Conventional technology]

Among the current color television systems, the vertical deflection frequency of the PAL system is as low as 50 Hz, so that so-called surface flicker, in which the entire screen flickers when high-brightness signals are reproduced, has become noticeable.

Therefore, as a method to improve the above-mentioned surface flicker, the vertical deflection frequency is doubled to 100Hz.
There is a free system.

This flicker-free system stores the image signal for F-field once in a storage means, doubles the reading speed of this stored content, and writes the same field twice on the screen. One frame was made up of one image, but now one frame is made up of four images. In this system, each set of two images is interlaced (the two images in set C1 trace the same location), so the number of horizontal deflections within the vertical deflection is 4 sets of images. Each one is different.

The scanning order of this flicker-free system will be explained using FIG.

Figure 3 shows that the length of the vertical deflection period of the image is 312.0H (H
is horizontal period), 312.5H313,0H312,5H
4 shows four sets of scan lines of the system varying with .

In the figure, the solid line indicates the length of the vertical deflection period of 313. OH and 3
12.5H set, dotted line is 312. OH and 312.5H
It shows the set of The set of scanning lines indicated by the solid line and the set of scanning lines indicated by the dotted line are interlaced with each other, and if the first vertical scan is 313.0 H, the scanning line starts from point A and ends at point B.

The next 312.5H starts at point A and ends at point 0 like the previous 313.0. The next set of one vertical scan scans along the dotted line from point D, 312. It ends at point E after OH.

The last vertical scan starts from point D again at 312.5H.
It ends at the later point F. Then, the scanning of 313.0H starts from point A again and the above-mentioned scanning is repeated.

[Problem to be solved by the invention]

However, the above-mentioned flicker-free system does not scan 312.5H per frame like normal interlacing, but scans 312.5H, 313, OH in order.

312.5H, 312, 0) (because the length of the deflection period differs for each vertical deflection period, for example, if scanning ends at point 0 shown in Fig. 3, scanning must be started from point D next time. As shown in the waveform diagram of FIG. 2 (a) vertical deflection signal, [b) vertical synchronization signal, and (c) S-curve correction voltage, 0.
There is a vertical deflection period during which a 5H shift occurs. For this reason, the S-curve correction voltage shifts in a DC manner in the frame where the above deviation occurs, causing two scanning lines to scan the same location at the same time, so-called bearing, etc., resulting in deterioration of interlacing. Ta.

In the specification and drawings of Japanese Patent Application No. 62-223852, the present applicant previously disclosed that the above-mentioned three-character correction capacitor is constructed by clamping the connection point between the vertical deflection coil and the three-character correction capacitor to a predetermined voltage by a clamping means. We are proposing a vertical deflection circuit that can always obtain an ideal parabolic waveform and perform appropriate three-character correction.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a vertical deflection circuit that can improve the deterioration of interlace caused by DC shift.

[Means to solve the problem]

In order to solve the above-mentioned problem, the cathode ray tube circuit according to the present invention has a vertical deflection circuit in which an S-shaped correction circuit is connected in series to a vertical deflection coil to perform vertical three-character correction. The vertical deflection coil is driven by a vertical deflection drive signal including a vertical deflection period having a deviation from the vertical deflection period, and while the vertical deflection period has the deviation, a correction signal having a level corresponding to the deviation amount. It is characterized in that it is superimposed on the feedback signal for three-character correction of the vertical deflection circuit or the vertical deflection sawtooth wave signal.

[For production]

The vertical deflection circuit according to the present invention can be used in a deflection system such as a flicker-free system in which the length of the vertical deflection period changes and deviations may occur, while the above-mentioned deviation is occurring, or when the deviation is occurring. By synchronizing with the deflection period and superimposing a correction signal with a level corresponding to the amount of deviation on the feedback signal for 3-character correction or the vertical deflection signal, the DC shift of the S-character correction voltage is eliminated, and an accurate correction signal without bearings etc. Interlace can be realized.

[Embodiments] Hereinafter, embodiments of the vertical deflection circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic circuit diagram of a vertical deflection circuit according to an embodiment of the present invention.

In the vertical deflection circuit shown in FIG. 1, a vertical deflection signal having a sawtooth waveform is supplied to an input terminal 1 via, for example, a vertical oscillation circuit, a vertical drive circuit, or the like. This input terminal 1 is connected to one input terminal 2a of a comparator 2. This comparator 2 is connected to a vertical deflection coil 4 via an amplifier 3, and this vertical deflection coil 4 is formed by connecting a three-figure correction capacitor 5 and a feedback resistor 6 in series between the ground and the ground. It is connected to the S-shaped correction circuit 7. Connection point 5a between the vertical deflection coil 4 and the capacitor 5
and connection point 5b between capacitor 5 and feedback resistor 6
are connected to the feedback circuit 8, respectively. A series connection circuit consisting of an interlace correction signal input terminal 9, a resistor 10, and a capacitor 11 is connected to this feedback circuit 8, and the interlace correction signal is supplied to the terminal 9. and,
The output terminal of this feedback circuit 8 is connected to the other input terminal 2b of the comparator 2.

Note that the feedback circuit 8 may have a specific configuration as shown in FIG. 1, for example.

In the feedback circuit 8 of FIG. 1, the output from the connection point 5a is connected to the resistor 12. Capacitor 13. The output from the connection point 5b is fed back to the other input terminal 2b of the comparator 2 via a circuit consisting of a variable resistor 14 and a resistor 15, and the output from the connection point 5b is fed back to the variable resistor 16. It is superimposed on the feedback signal via a circuit consisting of resistors 17 and 18 and a capacitor 19. Further, the interlace correction signal inputted to the terminal 9 is transmitted to the resistor 10. capacitor 1
1 to the connection point of the resistor 12.15.

Next, the operation will be explained.

A vertical deflection signal having a sawtooth waveform as shown in FIG. are input with signals from systems whose deflection period lengths are different, and the length of each deflection period is 3 in turn.
12.5H (H is horizontal period), 313. ,OH,312
, 5H1312, OH... This signal is amplified by the amplifier 3 and turned into a current signal and supplied to the vertical deflection coil 4, thereby driving the vertical deflection of the electron beam. Here the second
Figure (b) shows the vertical synchronization signal.

The sawtooth waveform current signal flowing through the vertical deflection coil 4 is integrated by the capacitor 5 of the S-shape correction circuit 7, thereby producing a parabolic S-shape correction voltage as shown in FIG. 2(c). . The feedback circuit 8 superimposes the voltage at the connection terminal 5b on the output voltage at the connection terminal 5a at a predetermined ratio and feeds back the superimposed voltage. For example, in a system where the length of each vertical deflection period is different, such as the above-mentioned flicker-free system, for a vertical deflection period of a constant period (312.5H period) as a reference, as shown in FIG. , the vertical deflection periods t3 to t, and t4 to t5 are all shifted by 0.5H, so that a DC shift occurs in the S-curve correction voltage as shown in FIG. As a result, interlacing deteriorates due to misalignment of scanning lines, bearings, etc.

Therefore, the vertical deflection period t3 to t4 during which the above deviation occurs
and t4 to t, respectively, and the deviation amount is 0.5H.
By superimposing an interlace correction signal (FIG. 2(d)) at a level L 6.5H corresponding to the feedback signal on the feedback signal, the DC shift is suppressed and the interlace is corrected.

Furthermore, as a result of the prototype experiment of the vertical deflection circuit according to this example,
Before using this vertical deflection circuit, the scanning lines were in a bearing state, but with this circuit, the interlace ratio was improved to 1:1.

As is clear from the above description, the vertical deflection circuit according to this embodiment is capable of superimposing an interlace correction signal that corrects the DC shift on the feedback signal and returns it only when the S-shaped correction signal undergoes a DC shift. This makes it possible to improve the deterioration of interlacing in bearings, etc. caused by the DC shift.

Further, in the above embodiment, the interlace correction signal is superimposed on the feedback signal to be fed back, but it goes without saying that it may be superimposed on the vertical deflection signal inputted to one input terminal 2a of the comparator 2.

Further, the vertical deflection circuit of the present invention may be applied to a vertical deflection circuit with S-shaped correction without feedback means, in which case the interlace correction signal is superimposed on the input vertical deflection signal.

〔Effect of the invention〕

The vertical deflection circuit according to the present invention synchronizes with a vertical deflection period in which a deviation has occurred with respect to a vertical deflection period of a constant period serving as a reference, and outputs a correction signal at a level corresponding to the amount of deviation for character-8 correction. The DC shift of the S-curve correction voltage can be corrected by superimposing it on the period signal or the vertical deflection signal.
It is possible to improve the deterioration of interlacing in bearings, etc. caused by C shift.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram showing a vertical deflection circuit as an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the vertical deflection circuit of a flicker-free system. FIG. 3 is a plan view showing scanning lines for explaining the flicker-free system. Input terminal Comparator Amplifier 3-character correction coil 8-character capacitor S-character correction circuit Feedback circuit Interlaced correction signal Input terminal

Claims (1)

[Claims] In a vertical deflection circuit that performs vertical S-shaped correction by connecting an S-shaped correction circuit in series to a vertical deflection coil, the vertical deflection has a deviation from a vertical deflection period of a constant period as a reference. The vertical deflection coil is driven by a vertical deflection drive signal including a period, and while the vertical deflection period causes the deviation, a correction signal of a level corresponding to the deviation amount is fed back to the vertical deflection circuit for S-shaped correction. A vertical deflection circuit characterized in that it is superimposed on a signal or a vertical deflection sawtooth signal.