JPH02128483U

JPH02128483U -

Info

Publication number: JPH02128483U
Application number: JP3719089U
Authority: JP
Priority date: 1989-03-30
Filing date: 1989-03-30
Publication date: 1990-10-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例による静止画伝送装
置を示すブロツク図、第２図はその全体構成を示
す斜視図、第３図はその画像メモリ回路を示すブ
ロツク図、第４図は従来の静止画伝送装置を示す
ブロツク図である。１，１０……静止画伝送装置、１８……制御回
路、７，４０……画像メモリ回路、４１……表示
用アドレスデータ発生回路、４１Ａ……垂直ライ
ンカウンタ回路、４１Ｂ……書込用初期値レジス
タ回路、４１Ｃ……読出用初期値レジスタ回路、
４１Ｄ……水平ドツトカウンタ回路、４５，４６
，５５……ラツチ回路、４３……フレームメモリ
回路、５７……データ圧縮用アドレスデータ発生
回路。 FIG. 1 is a block diagram showing a still image transmission device according to an embodiment of the present invention, FIG. 2 is a perspective view showing its overall configuration, FIG. 3 is a block diagram showing its image memory circuit, and FIG. 4 is a conventional device. 1 is a block diagram showing a still image transmission device of FIG. 1, 10...Still image transmission device, 18...Control circuit, 7, 40...Image memory circuit, 41...Display address data generation circuit, 41A...Vertical line counter circuit, 41B...Writing initial stage Value register circuit, 41C...Initial value register circuit for reading,
41D...Horizontal dot counter circuit, 45, 46
, 55... Latch circuit, 43... Frame memory circuit, 57... Address data generation circuit for data compression.

Claims

[Claims for Utility Model Registration] A memory circuit that sequentially stores image data and sequentially outputs the stored image data according to address data; and an address data creation circuit that sequentially creates address data of the memory circuit. An image processing apparatus comprising: an address data setting circuit that sets an initial value for starting reading and/or writing the address data.