JPH02128478A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To protect the insulating film of a transistor from breakdown by a method wherein write is execute by charging a floating gate with hot electrons in a similar manner when an EEPROM is used in the case that P-type is selected to be one conductivity type and erasure is executed by injecting holes generated when a P-channel or a MOS is pinched off. CONSTITUTION:An N-type Si layer 2 and an N-type diffusion layer 3 are formed on a P-type Si substrate 1, and N-type diffusion layers 4 and 5 thinner than the layer 3 are formed on the layer 3. A U-groove in contact with all the layers 2, 3, 4, and 5 is made and the inner faces of the groove is covered with an insulating film 7, a polycrystalline Si 6 is filled into the groove, a floating gate 7 of polycrystalline Si is fitted to a part of the surface of the Si 6 as being in contact with the layer 4, and a control gate 11 of polycrystalline Si is formed thereon through the intermediary of ann insulating film 10. A memory device of this design is constituted as mentioned above, where a write positive voltage is applied onto the gate 11 on write, and the layers 4 and 5 are made electrically open and an erasure negative voltage is applied to the gate 11 and the substrate 1 on erasure.

Description

[Detailed Description of the Invention] (Summary) Among MOS type and Bi-CMOS type semiconductor memories, the reliability of the batch erase type EEFROM that can be electrically written and erased and that erases all contents at one time. The purpose is to provide a high-density, high-density, bulk erasure type EEPROM.A first semiconductor layer (1) of one conductivity type is provided with a second semiconductor layer (2) of an opposite conductivity type and a second semiconductor layer (2) of one conductivity type. 3 semiconductor layers (3) in sequence, and an opposite conductivity type layer (4) shallower than the third semiconductor layer (3).
, 5) are provided in the third semiconductor layer (3) at positions on both sides of the floating gate and the control gate, and the first semiconductor layer (
1) A groove is formed so as to be in contact with all of the second semiconductor layer (2), third semiconductor layer (3), and diffusion layers (4, 5), and the inner surface of the groove is covered with an insulating layer M (7). Conductive material inside (
6), and place a conductive material (9) that is directly connected to the conductive material (6) in the trench and serves as a floating gate on the insulating film (8), and further floating via the insulating film (10). A conductive material (11) covering the gate is provided as a control gate, and a contact window (31) is provided for connecting the metal wiring layer (12) to either of the shallow opposite conductive layers (4, 5). Configure.

(Industrial Application Field) The present invention relates to a batch erasing type EEPROM which can be electrically written and erased among MOS type and B1-CMOS type semiconductor memories and erases all contents at one time.

With the recent advances in semiconductor memory, electrically programmable and erasable EEPROMs have been released as products, but their complicated circuit configurations and cell sizes have prevented their integration from increasing, and the market has not expanded. On the other hand, the bulk erasing type EEFROM, which has been announced many times since 1980,
The market is expected to expand due to its high degree of integration.

(Prior Art) The earliest patent for a conventional batch erase type EEPROM is JP-A-55-89989, and the latest is JP-A-62-154786.

These can be roughly divided into three types shown in FIGS. 2 to 4 based on the cell writing and erasing methods. In the figure, 21
is a metal wiring, 22 is a control gate, 23 is a floating gate, 2
4 is an erase gate, 25 is a tunnel oxide film, 26 is a p-type substrate, 27 is a source, 28 is a drain, 29 is a surface protection film, and 30 is a gate layer. All three types of writing are EP
This is done by accumulating charges in the floating gate by hot electron injection, which is used in ROM. There are different erasure methods, and the one shown in FIG.
In this method, the charges accumulated in the memory are extracted to the erase gate 24 and erased. What is shown in Figure 3 is the source 27
Erasing is performed by the tunnel effect between the N type diffusion region and the floating gate 23.

In the case shown in FIG. 4, erasing is performed by the tunnel effect between the N type diffusion region which becomes the drain 28 and the floating gate.

(Problems to be Solved by the Invention) Therefore, all conventional batch erasing type EEPROMs use the tunnel effect under some condition, and it is necessary to apply a strong electric field to a part of the insulating film.

Furthermore, in the case shown in FIGS. 3 and 4, the tunnel oxide film 25 that causes the tunnel effect is connected to the sense transistor during data reading.
In other words, it was necessary to apply a strong electric field to the gate oxide film during erasing.

However, in order to create a tunnel effect, it is generally necessary to apply a fairly strong electric field to the insulating film, which is known to damage the insulating film and cause reliability problems. In many cases, the limit on the number of rewrites is low. In the method shown in Figure 2, the erase-only gate 2
4, and the tunnel oxide film 25 and gate oxide film have different configurations, so stable erasing is possible, but three gate insulating film layers 30a, 30b, and 30C are required. The problem is that it is difficult to incorporate these elements.

In addition, in all conventional methods, the high electric field during erasing is
All of them have a high breakdown voltage MOS-Tr on the surface, and this becomes a bottleneck in increasing the degree of integration, such as increasing the gate length.

The present invention solves these two problems and is highly reliable.
The purpose of the present invention is to provide a highly integrated batch erase type EEPROM.

(Means for Solving the Problem) A semiconductor memory device according to the present invention includes a first semiconductor layer of one conductivity type, a second semiconductor layer of an opposite conductivity type, and a third semiconductor layer of one conductivity type.
Semiconductor layers are sequentially provided, and layers of opposite conductivity type shallower than the third semiconductor layer are provided in the third semiconductor layer at positions on both sides of the floating gate and the control gate, and the first semiconductor layer, the second semiconductor layer, and the third A groove is formed so as to be in contact with all of the semiconductor layer and the diffusion layer, the inner surface of the groove is covered with an insulating film, and the inside of the groove is filled with a conductive material, so that it is directly connected to the conductive material in the trench, and the floating material on the insulating film is A conductive material to serve as a gate is arranged, a conductive material covering the floating gate via an insulating film is provided as a control gate, and a contact window is provided to connect the metal wiring layer to any of the shallow opposite conductive layers. It is characterized by having

(Function) In the present invention, when the P type is set to one conductivity type, writing is performed in EE mode.
Charge storage in the floating gate is performed by hot electron injection, which is the same method used in PROMs. Erase is P
This is done by pinching on the channel or MOS and injecting a pole generated by avalanche breakdown. Therefore, tunnel effect is not used. Furthermore, since writing and erasing is performed on the trench wall in the bulk, the insulating film of the sense Tr that operates during data reading is not damaged at all.

(Example) Hereinafter, the structure of the present invention will be explained in detail using an example. FIG. 1 is a diagram showing the elements of the semiconductor memory device of the present invention, FIG. 5 is a planar arrangement diagram of each part, and FIGS. 6 and 7 are A--A in FIG.
8 is an equivalent circuit diagram of the present invention.

In the embodiments shown in these drawings, a Si substrate is used as the first semiconductor layer of one conductivity type, and the second semiconductor layer of the opposite conductivity type and the third semiconductor layer of one conductivity type are formed by epitaxial growth. The opposite conductivity type layer is formed by diffusion, the layer is U-shaped, the conductive material inside the groove is polycrystalline Si,
The conductive material serving as the floating gate and the conductive material covering the floating gate are also polycrystalline Si.

That is, in this embodiment, on the P-type Si substrate 1, the N-type S
An i-layer 2 and a P-type Si diffusion layer 3 are provided, and the P-type Si diffusion layer 3 is
A shallower N type diffusion layer 4.5 is provided in a part of the P type diffusion layer. Further, a U-groove is formed in contact with all of the N-type Si layer 2, P-type Si diffusion layer 3, and N-type diffusion layer 4.5. N-type diffusion layer 4.
5 are formed on both sides of the control gate and floating gate. Furthermore, the inner surface of the U-groove is covered with an insulating film 7, and polycrystalline Si is placed inside the insulating film 7.
6 filled with polycrystalline Si6 disposed through an insulating film 8.
is provided directly connected to the polycrystalline Si9 which becomes the floating gate. Furthermore, a floating gate (polycrystalline Si layer 9) is formed via an insulating film 10.
A polycrystalline Si layer 11 covering the N-type diffusion layer 4.5 is provided as a control gate, and is further configured to have a contact window for connecting the metal wiring layer 12 and either of the N-type diffusion layers 4.5.

In FIG. 8 showing the equivalent circuit, 35 is composed of a P-type Si substrate 1, an N-type Si layer 2 and a P-type Si diffusion layer 3,
In the P-channel Tr used for erasing, its gate oxide film is the insulating film 7 in the U trench, and its gate is polycrystalline Si6. 36 is an N-channel Tr that is composed of an N-type Si layer 2, a P-type Si diffusion layer 3, and an N-type diffusion layer 5, and is used for writing, and its gate oxide film is the insulating film 7 in the U groove. , the gate is polycrystalline Si6. The source side is bi
Two t-lines are connected on one line.

37 and 38 are transistors used for readout, with the floating gate 11, the control gate 11, the polycrystalline 5ill in the portion not overlapping the floating gates serving as gates, and the insulating film 8 below, and the gate insulating films 8 and 10 serving as gate insulating films. (See Figure 7). Such a Tr can be used in a conventional EPROM (for example, the third
(Fig.) is also used. Note that the source of these Tr is the N-type diffusion layer 4, and the drain thereof is the N-type diffusion layer 5. Reading is performed using the Tr 37, but during erasing, the pole may enter the Tr too much and cause leakage, so the Tr 38 is used to suppress this.

FIG. 9 is a diagram for explaining the write operation of the present invention. N-type diffusion layer 5 (which becomes the source side during writing)
(not visible in FIG. 9) makes all cells electrically open. +■PP (positive voltage for writing) is applied to the polycrystalline Si layer 11 serving as the control gate of the selected row, -vpp or no bias is applied to the control gate polycrystalline Si layer 11 of the non-selected row, and the bit line of the selected column is applied. -VPP is applied to the 1st line 2, that is, the N-type diffusion layer 5, or no bias is applied, and +VPP is applied to the bit line 1 of the non-selected cell column, that is, the N-type diffusion layer 5.
+VPP is applied to the N-type Epitaxia 1 layer 2. In the selected cell, the N-type diffusion layer 5 and the N-type Epitaxia
A bias is applied between layer 1 and layer 2, and the potentials of floating gate 9 and polycrystalline Si 6 are determined by the capacitance relationship between control gate 11, its region, and the floating gate. As a result, the MO8 effect occurs in the P-type diffusion region 3 in contact with the U-side, and avalanche breakdown occurs due to the high bias. The hot electrons 13 generated by this are injected into the polycrystalline Si6 inside the U groove by the electric field 16, and this
This becomes an accumulated charge in the floating gate 9 which is directly connected to the floating gate 9, and changes the threshold voltage of the sense Tr 37 (the principle is the same as hot electron injection in a general EPROM, except that the hot electron is generated in the bulk). In non-selected cells, the potential of the N-type diffusion layer 5 is 10PP or a low voltage is applied to the control gate, so no hot electrons or electric field 16 is generated.

10th U;! U is a diagram for explaining the operation during erasing of the present invention. During erasing, both the N-type diffusion layer 4 and the N-type diffusion layer 5 are electrically released. All control gates 11
-vpp is applied to the p-type diffusion layer 3, -VPP (positive voltage for erasing) is applied to the p-type Si substrate 1 common to each cell. In all cells, a P-type diffusion layer 3 and a P-type Si substrate 1
A bias is applied between the floating gate 6.9 and the floating gate 6.9 due to the capacitance relationship between the control gate 11, other regions, and the floating gate 6.9.
The potential of is determined. As a result, the N-type Epi that touches the U-shaped
MO8 effect occurs in taxial waste 2, and avalanche breakdown occurs due to high bias. Holes 15 generated by this are injected into the polycrystalline Si 6 inside the U-groove by the electric field effect, and are injected into the floating gate 6.
9 is neutralized, and the threshold voltage of the sense Tr 37 is changed.

FIG. 11 is a configuration diagram of an embodiment of the present invention. 11°,
11'' are word lines 1 and 2, respectively. Also, 12'
, 12', and 12'' are bit lines 1, 2.3, respectively. The control gates 11 of the present invention form the word lines of the memory array, and the metal wiring layers 12 form the bit lines. 3
2 is the outer edge line of the N-type diffusion layer, and inside 32 is the polycrystalline 5.
There is an N-type diffusion layer 33 except for the area below i11, as indicated by the hatched area rising to the right. The N-type diffusion layer 4 serving as a source is common to all cells, and the level is reinforced by a metal wiring layer 33 for every other bit. 31 is a contact window. (Effects of the Invention) As explained above, by using the present invention, it is possible to clearly improve the reliability of the bulk erase type EEPROM, and since writing and erasing are performed in the bulk, it is possible to achieve a high degree of integration. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the constituent elements of the memory device of the present invention, FIGS. 2 to 4 are basic cell structure diagrams of a conventional batch erasing type EEPROM, and FIG. 5 is a front view of the memory device of the present invention. Figures 6 and 7 are cross-sectional views taken along lines AA' and BB'' in Figure 5, Figure 8 is an equivalent circuit diagram of the present invention, and Figures 9 and 10 are cross-sectional views of the present invention. FIG. 11 is a diagram illustrating the operation of the storage device, and is a planar arrangement diagram of an embodiment of the present invention. In the figure, 1-P type Si substrate, 2-N type Si layer, 3-P type S
i diffusion layer, 4,5-shallow N-type diffusion layer, 6-polycrystalline Si,
7-insulating film, 8-insulating film, 9 polycrystalline Si (floating goo))
=10-insulating film, 11 polycrystalline Si layer (control gate), 1
2-metal wiring layer, 21-metal wiring, 22-control gate,
23 floating gate, 24- erase gate, 25- tunnel oxide film, 26- p type substrate, 27- source, 28 drain,
2 - surface protection film, 30 - gate insulating film, 32 - N type diffusion outer edge.

Claims (1)

[Claims] 1. On a first semiconductor layer (1) of one conductivity type, a second semiconductor layer (2) of an opposite conductivity type and a third semiconductor layer (3) of one conductivity type.
and opposite conductivity type layers (4, 5) shallower than the third semiconductor layer (3) are provided in the third semiconductor layer (3) at positions on both sides of the floating gate and the control gate, and A groove is formed so as to be in contact with all of the layer (1), the second semiconductor layer (2), the third semiconductor layer (3), and the diffusion layers (4, 5), and the inner surface of the groove is covered with an insulating film (7). , the inside of which is filled with a conductive substance (6) and directly connected to the conductive substance (6) in the groove;
A conductive material (9) serving as a floating gate is placed on an insulating film (8), a conductive material (11) is provided as a control gate to cover the floating gate via an insulating film (10), and a metal wiring layer is further provided. (12) as the shallow opposite conductive layer (4, 5)
A semiconductor memory device characterized by having a contact window (31) for connection to any one of the semiconductor memory devices.