JPH02128418U - - Google Patents
Info
- Publication number
- JPH02128418U JPH02128418U JP3766689U JP3766689U JPH02128418U JP H02128418 U JPH02128418 U JP H02128418U JP 3766689 U JP3766689 U JP 3766689U JP 3766689 U JP3766689 U JP 3766689U JP H02128418 U JPH02128418 U JP H02128418U
- Authority
- JP
- Japan
- Prior art keywords
- gain amplifier
- programmable gain
- input
- current
- cancel circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図、第３図は本考案の他の実施例を示す
構成ブロツク図、第４図は本考案の動作説明図、
第５図は入力電流キヤンセル回路の詳細構成例を
示す回路図、第６図はＰＧＡを用いたＡ／Ｄ変換
システムの一般的な構成を示すブロツク図、第７
図はＰＧＡの従来構成例を示す回路図、第８図は
オフセツト電圧発生の説明図、第９図はバイアス
電流キヤンセル回路例を示す図である。
１０……入力電流キヤンセル回路、１１……プ
ログラマブル・ゲインアンプ、Ｒ１，３１Ｒ１…
…抵抗。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing other embodiments of the present invention, and FIG. 4 is an explanatory diagram of the operation of the present invention.
FIG. 5 is a circuit diagram showing a detailed configuration example of an input current cancel circuit, FIG. 6 is a block diagram showing a general configuration of an A/D conversion system using PGA, and FIG.
FIG. 8 is a circuit diagram showing an example of a conventional configuration of a PGA, FIG. 8 is an explanatory diagram of offset voltage generation, and FIG. 9 is a diagram showing an example of a bias current cancel circuit. 10...Input current cancel circuit, 11...Programmable gain amplifier, R1, 31R1...
…resistance.
Claims (1)
を内蔵し、外部切換え信号によりそのうちの何れ
か一方をセレクトするようにしたプログラマブル
・ゲインアンプにおいて、その入力段に入力バイ
アス電流をキヤンセルするための入力電流キヤン
セル回路を設けたことを特徴とする高精度プログ
ラマブル・ゲインアンプ。 (2) 前記入力電流キヤンセル回路としてカレン
トミラー回路を用いたことを特徴とする請求項１
記載の高精度プログラマブル・ゲインアンプ。[Claims for Utility Model Registration] (1) In a programmable gain amplifier that has at least two sets of gain amplifiers built-in and one of them is selected by an external switching signal, the input stage is input to the input stage of the programmable gain amplifier. A high-precision programmable gain amplifier characterized by having an input current cancel circuit for canceling bias current. (2) Claim 1 characterized in that a current mirror circuit is used as the input current cancel circuit.
Precision programmable gain amplifier as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3766689U JPH02128418U (en) | 1989-03-31 | 1989-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3766689U JPH02128418U (en) | 1989-03-31 | 1989-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02128418U true JPH02128418U (en) | 1990-10-23 |
Family
ID=31544987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3766689U Pending JPH02128418U (en) | 1989-03-31 | 1989-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02128418U (en) |
-
1989
- 1989-03-31 JP JP3766689U patent/JPH02128418U/ja active Pending
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