JPH0212795U - - Google Patents
Info
- Publication number
- JPH0212795U JPH0212795U JP1988089851U JP8985188U JPH0212795U JP H0212795 U JPH0212795 U JP H0212795U JP 1988089851 U JP1988089851 U JP 1988089851U JP 8985188 U JP8985188 U JP 8985188U JP H0212795 U JPH0212795 U JP H0212795U
- Authority
- JP
- Japan
- Prior art keywords
- input
- terminals
- switch
- double
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
第１図は本考案の実施例における基本回路構成
を示す回路図、第２図Ａ及びＢは第１図に示した
基本回路を有する多系統入出力回路を２組クロス
接続した状態を示す略線図、第３図は第２図の接
続からなる入出力回路を備えた２組のマトリツク
ススイツチヤーを示す略図である。
１……入力ライン、２……増幅器、３……メイ
ン入力、４……サブ入力、５……プロセツサ、６
……第１の入出力回路、７……第２の入出力回路
。
Fig. 1 is a circuit diagram showing the basic circuit configuration in an embodiment of the present invention, and Figs. 2 A and B are schematic diagrams showing two sets of cross-connected multi-system input/output circuits having the basic circuit shown in Fig. 1. The diagram, FIG. 3, is a schematic diagram showing two sets of matrix switchers with input/output circuits consisting of the connections of FIG. 1...Input line, 2...Amplifier, 3...Main input, 4...Sub input, 5...Processor, 6
...First input/output circuit, 7...Second input/output circuit.
Claims (1)
入力ラインＡ，Ｂ，Ｃ…にそれぞれ１入力選択用
の双投スイツチＳＷＡ，ＳＷＢ，ＳＷＣ…の各出
力側接点を接続するとともに、各双投スイツチの
第１の入力側接点ａ１，ｂ１，ｃ１…を各入力ラ
インのためのメイン入力端子Ａ１，Ｂ１，Ｃ１…
の各々及びスルー端子ＡＴ，ＢＴ，ＣＴ…の各々
にそれぞれ接続し、さらに前記各双投スイツチの
第２の入力側接点ａ２，ｂ２，ｃ２…を各入力ラ
インのためのサブ入力端子Ａ２，Ｂ２，Ｃ２…の
各々に接続するとともに、各スルー端子ＡＴ，Ｂ
Ｔ，ＣＴ…と接地電位との間にはそれぞれオン−
オフスイツチ手段を介して終端整合用抵抗器ＲＴ
１を挿入し、前記サブ入力端子Ａ２，Ｂ２，Ｃ２
…と接地電位との間にはそれぞれ終端整合用抵抗
器ＲＴ２を直接挿入したことを特徴とするＡＶ機
器用入出力回路。 (2) 前記抵抗器ＲＴ１を挿入するためのオン−
オフスイツチ手段が対応するスルー端子ＡＴ，Ｂ
Ｔ，ＣＴ…に挿入可能なダミープラグからなるこ
とを特徴とする請求項(1)に記載のスイツチ回路
。[Scope of Claim for Utility Model Registration] (1) Each output side contact of double-throw switches SWA, SWB, SWC, etc. for selecting one input is connected to a plurality of input lines A, B, C, etc., which respectively lead to input terminals of an amplifier. At the same time, the first input side contacts a 1 , b 1 , c 1 . . . of each double-throw switch are connected to the main input terminals A 1 , B 1 , C 1 . . . for each input line.
and each of the through terminals AT, BT, CT, etc., and further connect the second input side contacts a 2 , b 2 , c 2 . A 2 , B 2 , C 2 ... and each through terminal AT, B
There is an on-
Termination matching resistor RT via off switch means
1 , and the sub input terminals A 2 , B 2 , C 2
An input/output circuit for AV equipment, characterized in that a termination matching resistor RT2 is directly inserted between ... and ground potential. (2) Turn on to insert the resistor RT1 .
Through terminals AT, B corresponding to off switch means
2. The switch circuit according to claim 1, comprising a dummy plug that can be inserted into T, CT, . . . .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988089851U JPH0756542Y2 (en) | 1988-07-06 | 1988-07-06 | Input / output circuit for AV equipment with insertion and circuit expansion functions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988089851U JPH0756542Y2 (en) | 1988-07-06 | 1988-07-06 | Input / output circuit for AV equipment with insertion and circuit expansion functions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0212795U true JPH0212795U (en) | 1990-01-26 |
| JPH0756542Y2 JPH0756542Y2 (en) | 1995-12-25 |
Family
ID=31314385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988089851U Expired - Lifetime JPH0756542Y2 (en) | 1988-07-06 | 1988-07-06 | Input / output circuit for AV equipment with insertion and circuit expansion functions |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0756542Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101429515B1 (en) * | 2010-03-30 | 2014-08-12 | 삼성테크윈 주식회사 | A matrix system |
-
1988
- 1988-07-06 JP JP1988089851U patent/JPH0756542Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0756542Y2 (en) | 1995-12-25 |
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