JPH02125483A - Selectively growing method for semiconductor - Google Patents

Selectively growing method for semiconductor

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Publication number
JPH02125483A
JPH02125483A JP27847388A JP27847388A JPH02125483A JP H02125483 A JPH02125483 A JP H02125483A JP 27847388 A JP27847388 A JP 27847388A JP 27847388 A JP27847388 A JP 27847388A JP H02125483 A JPH02125483 A JP H02125483A
Authority
JP
Japan
Prior art keywords
layer
integrated circuit
crystal layer
insulating film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27847388A
Other languages
Japanese (ja)
Inventor
Kenichi Koike
賢一 小池
Goro Sasaki
吾朗 佐々木
Nobuchika Kuwata
桑田 展周
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP27847388A priority Critical patent/JPH02125483A/en
Publication of JPH02125483A publication Critical patent/JPH02125483A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent an insulating film from cracking or peeling by selectively removing a crystalline layer and a thin film, forming the insulating film, and selectively crystal-growing a second crystalline layer for an electronic integrated circuit in a removed part. CONSTITUTION:A second crystalline layer 5 formed with an electronic integrated circuit such as FET, etc., is selectively epitaxially grown on a semiconductor substrate 1 in which a first crystalline layer 2 and a thin film 3 are removed by an organic metal vapor epitaxial method. After the growing, the integrated circuit is formed on the layer 5. In this case, since the layer 2 and the film 3 are masked with an insulating film 4, the layer 5 for the integrated circuit is not formed thereon. Since the film 3 made of InP and the film 4 made of SiN has satisfactory adhesive properties, the film 4 is not cracked, or peeled, and there is no growth of the crystal of the layer 5 erroneously on the layer 2.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 本発明は半導体選択成長方法に関し、特に光集積回路が
形成される結晶層と電子集積回路が形成される結晶層と
を選択的に成長させる成長方法に関するものである。 〔従来の技術〕 従来、この種の一般的な光電子集積回路の選択成長方法
としては、例えば、応用物理学会の発行する「応用電子
物性分科会研究報告No、423Jに示されるものがあ
る。 また、光電子集積回路においては、発光または受光素子
等が構成される光集積回路用の結晶層と、電界効果トラ
ンジスタ(FET)を初めとする電子集積回路用の結晶
層とは一般的に異なる。このため、最も単純な選択成長
方法としては、エツチングの際に選択性のある薄いエッ
チ停止層を介し、半絶縁性半導体基板上に電子集積回路
が形成される第1の結晶層と光集積回路が形成される第
2の結晶層とを連、続的にエピタキシャル成長させるも
のがある。そして、第1の結晶層のうち電子集積回路が
形成される領域は露出させる必要があるため、この電子
集積回路形成領域上に位置する第2の結晶層およびエッ
チ停止層自体を化学エッチ等により選択的に除去するこ
とにより電子集積回路層の露出を実現させている。 しかし、この化学エッチにおいて、1μm以上のエツチ
ングを行おうとする場合には、十分大きな選択比を持つ
エッチ停止層を形成させても、形成される層に数百へ以
上のバラツキが生じてしまう。このため1.電子集積回
路層について1μm以上のエツチングを行い、ヘテロ界
面を流れる2次元電子ガスを利用したFETを形成させ
ると、このFETの特性は不安定なものとなってしまう
。 これを解消するためには次のような方法がある。 つまり、半絶縁性半導体基板上に光集積回路が形成され
る第1の結晶層をエピタキシャル成長させた後、この第
1の結晶層のうち不要な部分を化学エッチ等により除去
し、除去後に残った第1の結晶層を絶縁膜で覆う。そし
て、この絶縁膜の被覆後に、電子集積回路が形成される
第2の結晶層を除去部に選択的にエピタキシャル成長さ
せる。この選択成長方法においては均一な厚さの電子集
積回路用の結晶層が得られる。 〔発明が解決しようとする課題〕 しかしながら、この従来の選択成長方法において、例え
ばSiN (窒化ケイ素)から成る絶縁膜の(2)下に
形成される光集積回路用結晶層が例えばGa’1nAs
(ガリウム・インジウム・砒素)である場合には、絶縁
膜と結晶層との密着性が悪いため、絶縁膜に亀裂や膜は
がれ等が生じてしまう。 このため、従来の選択成長方法は、この後の製造プロセ
スである電子集積回路用結晶層のエピタキシャル成長プ
ロセスにおいて、絶縁膜の亀裂や膜はがれ等を介して光
集積回路用の結晶層に電子集積回路用の結晶が成長され
てしまうという課題を有していた。 〔課題を解決するための手段〕 本発明はこのような課題を解消するためになされたもの
で、光集積回路用の第1の結晶層上に絶縁膜と密着性の
良い薄膜を形成した後、これら結晶層および薄膜を選択
的に除去し、除去後に残った結晶層および薄膜上に前記
の絶縁膜を形成させ、除去部に電子集積回路用の第2の
結晶層を選択的に結晶成長させるようにしたものである
。 〔作用〕 絶縁膜は薄膜と密着して剥がれ難(なる。 〔実施例〕 次に本発明について図面を参照して以下に詳述する。 図(a)〜(d)は本発明の一実施例の製造プロセスを
表す断面図である。 同図(a)に示されるように、InPから成る半絶縁性
半導体基板1上には、有機金属気相エピタキシャル法(
Organi Metallic Vapor Pha
seEpitaxy)により、発光または受光素子等の
光集積回路が形成される第1の結晶層2が形成され、さ
らに、この第1の結晶層2上にはInPから成る薄膜3
が形成される。 同図(b)に示されるように、第1の結晶層2およびこ
の第1の結晶層2よに形成された薄膜3のうち、後述す
る電子集積回路が形成される領域に相当する部分は化学
エッチ等により選択的に除去される。 同図(C)に示されるように、除去後に残った第1の結
晶層2および薄膜3上にはSiNから成る絶縁膜4が堆
積されて被覆され、この後の製造プロセスである電子集
積回路用結晶層の成長の際のマスクとされる。 同図(d)に示されるように、第1の結晶層2および薄
膜3の除去された半導体基板1上に、有機金属気相エピ
タキシャル法により、FET等の電子集積回路が形成さ
れる第2の結晶層5が選択的にエピタキシャル成長され
る。そして、この成長後に結晶層5にFET等の電子集
積回路が形成される。 なお、この際、光集積回路用の第1の結晶層2および薄
膜3は上述したように絶縁膜4によってマスクされてい
るため、これらの上には電子集積回路用の結晶層5は形
成されない。また、InPから成る薄膜3とSiN、Q
sら成る絶縁膜4とは密着性が良いため、従来のように
絶縁膜4に亀裂や膜はがれ等は発生せず、光集積回路用
の第1の結晶層2に誤って電子集積回路用結晶層5の結
晶が成長されてしまうといったことは無い。 同図(e)に示されるように、第2の結晶層5に電子集
積回路が形成された後、絶縁膜4および薄膜3は化学エ
ッチ等により除去され、光集積回路用の第1の結晶層2
が露出される。そして、この第1の結晶層2に発光また
は受光素子等の光集積回路が形成され、一連の光電子集
積回路の製造プロセスは終了する。 なお、上記実施例において、薄膜3はInPから成り、
絶縁膜4はSiNから成るものとして説明したがこれら
に限定されることは無く、薄膜3および絶縁膜4の各組
成成分は相互に密着性の良い成分から成るものであれば
良く、上記実施例と同様な効果を奏する。 〔発明の効果〕 以上説明したように本発明は、光集積回路用の第1の結
晶層上に絶縁膜と密着性の良い薄膜を形成した後、これ
ら結晶層および薄膜を選択的に除去し、除去後に残った
結晶層および薄膜上に前記の絶縁膜を形成させ、除去部
に電子集積回路用の第2の結晶層を選択的に結晶成長さ
せるようにしたことにより、絶縁膜は薄膜と密着して剥
がれ難くなる。 このため、従来のように、例えばGa I nAsから
成る光集積回路用の結晶層上に絶縁膜が形成されること
によって発生する絶縁膜の亀裂や膜はがれ等は生じなく
なり、光集積回路用の結晶層に電子集積回路用結晶層の
結晶が成長されてしまうといった課題は解消されるとい
う効果を有する。
[Industrial Application Field] The present invention relates to a semiconductor selective growth method, and more particularly to a growth method for selectively growing a crystal layer in which an optical integrated circuit is formed and a crystal layer in which an electronic integrated circuit is formed. [Prior Art] Conventionally, as a general selective growth method of this type of optoelectronic integrated circuit, there is, for example, the one shown in "Applied Electronic Materials Subcommittee Research Report No. 423J" published by the Japan Society of Applied Physics. In optoelectronic integrated circuits, the crystal layer for optoelectronic integrated circuits in which light-emitting or light-receiving elements are formed is generally different from the crystal layer for electronic integrated circuits such as field-effect transistors (FETs). Therefore, in the simplest selective growth method, the first crystal layer on which the electronic integrated circuit is formed and the optical integrated circuit are separated on the semi-insulating semiconductor substrate through a selective thin etch stop layer during etching. There is a method in which the second crystal layer to be formed is epitaxially grown continuously.The region of the first crystal layer where the electronic integrated circuit is to be formed needs to be exposed. The electronic integrated circuit layer is exposed by selectively removing the second crystal layer and the etch stop layer itself located on the formation region by chemical etching, etc. However, in this chemical etching, When etching is attempted, even if an etch stop layer with a sufficiently large selection ratio is formed, the formed layer will vary by several hundred or more.For this reason, 1. 1 μm for the electronic integrated circuit layer. If the above etching is performed to form an FET that uses two-dimensional electron gas flowing through the hetero interface, the characteristics of this FET will become unstable.The following methods can be used to resolve this problem. In other words, after epitaxially growing a first crystal layer on which an optical integrated circuit is formed on a semi-insulating semiconductor substrate, unnecessary portions of this first crystal layer are removed by chemical etching, etc. The remaining first crystal layer is covered with an insulating film. Then, after covering with this insulating film, a second crystal layer on which an electronic integrated circuit will be formed is selectively epitaxially grown on the removed portion. In this selective growth method, A crystal layer for electronic integrated circuits having a uniform thickness can be obtained. [Problem to be solved by the invention] However, in this conventional selective growth method, for example, the layer (2) under the insulating film made of SiN (silicon nitride) For example, the crystal layer for optical integrated circuits formed in
(Gallium, Indium, Arsenic), the adhesion between the insulating film and the crystal layer is poor, resulting in cracks and peeling of the insulating film. For this reason, in the conventional selective growth method, in the epitaxial growth process of the crystal layer for electronic integrated circuits, which is the subsequent manufacturing process, the crystal layer for optical integrated circuits is grown through cracks or peeling of the insulating film. However, the problem was that the crystals used for this purpose were grown. [Means for Solving the Problems] The present invention has been made to solve the above problems. , these crystal layers and thin films are selectively removed, the above-mentioned insulating film is formed on the crystal layers and thin films that remain after removal, and a second crystal layer for an electronic integrated circuit is selectively grown in the removed portion. It was designed so that [Function] The insulating film adheres closely to the thin film and is difficult to peel off. [Example] Next, the present invention will be described in detail below with reference to the drawings. Figures (a) to (d) show one embodiment of the present invention. 1 is a cross-sectional view showing an example manufacturing process. As shown in FIG.
Organi Metallic Vapor Pha
A first crystal layer 2 on which an optical integrated circuit such as a light emitting or light receiving element is formed is formed by a thin film 3 made of InP on this first crystal layer 2.
is formed. As shown in FIG. 2B, a portion of the first crystal layer 2 and the thin film 3 formed on the first crystal layer 2 corresponds to a region where an electronic integrated circuit, which will be described later, is formed. It is selectively removed by chemical etching or the like. As shown in FIG. 2C, an insulating film 4 made of SiN is deposited and coated on the first crystal layer 2 and thin film 3 remaining after the removal, and the electronic integrated circuit which is the subsequent manufacturing process is formed. It is used as a mask during the growth of crystalline layers. As shown in FIG. 3(d), an electronic integrated circuit such as an FET is formed on the semiconductor substrate 1 from which the first crystal layer 2 and the thin film 3 have been removed by the organometallic vapor phase epitaxial method. crystal layer 5 is selectively epitaxially grown. After this growth, an electronic integrated circuit such as an FET is formed on the crystal layer 5. Note that at this time, since the first crystal layer 2 and thin film 3 for the optical integrated circuit are masked by the insulating film 4 as described above, the crystal layer 5 for the electronic integrated circuit is not formed on them. . In addition, the thin film 3 made of InP and SiN, Q
Since it has good adhesion to the insulating film 4 made of There is no possibility that the crystal of the crystal layer 5 will be grown. As shown in FIG. 6(e), after the electronic integrated circuit is formed on the second crystal layer 5, the insulating film 4 and the thin film 3 are removed by chemical etching or the like, and the first crystal for the optical integrated circuit is formed. layer 2
is exposed. Then, an optical integrated circuit such as a light emitting or light receiving element is formed on this first crystal layer 2, and the series of manufacturing processes for the optoelectronic integrated circuit is completed. Note that in the above embodiment, the thin film 3 is made of InP,
Although the insulating film 4 has been described as being made of SiN, it is not limited thereto, and each composition of the thin film 3 and the insulating film 4 may be made of components that have good adhesion to each other. It has the same effect. [Effects of the Invention] As explained above, the present invention forms a thin film with good adhesion to an insulating film on a first crystal layer for an optical integrated circuit, and then selectively removes the crystal layer and thin film. The insulating film is formed on the crystal layer and thin film remaining after removal, and the second crystal layer for an electronic integrated circuit is selectively grown in the removed portion, so that the insulating film becomes a thin film. It sticks tightly and becomes difficult to peel off. For this reason, cracks and peeling of the insulating film, which occur when an insulating film is formed on a crystal layer for optical integrated circuits made of GaInAs, do not occur as in the past. This has the effect of solving the problem that the crystal of the crystal layer for electronic integrated circuits is grown on the crystal layer.

【図面の簡単な説明】[Brief explanation of the drawing]

図(a)〜(e)は、本発明の一実施例による製造プロ
セスを表す断面図である。 1・・・半絶縁性半導体基板、2・・・光集積回路が形
成される第1の結晶層、3・・・InPから成る薄膜、
4・・・SiNから成る絶縁膜、5・・・電子集積回路
が形成される第2の結晶層。 特許出願人  住友電気工業株式会社 代理人弁理士   長谷用  芳  樹手続補正書(放
) 昭和63年 特許願 第278473号 半導体選択成長方法 住友電気工業株式会社 代 理 人 (郵便番号 101 ) 東京都千代田区岩本町三丁目5番地2号フォアサイトビ
ル4階 5 補正命令の日付 平成 1年 2月13日 (発送臼 平成1年3月7日) 補正の対象 明細書の「発明の詳細な説明」 の各欄及び図面
Figures (a) to (e) are cross-sectional views showing a manufacturing process according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semi-insulating semiconductor substrate, 2... First crystal layer on which an optical integrated circuit is formed, 3... Thin film made of InP,
4... An insulating film made of SiN, 5... A second crystal layer on which an electronic integrated circuit is formed. Patent Applicant: Yoshiki Hase, Patent Attorney, Sumitomo Electric Industries, Ltd. Procedural Amendment (Released) Patent Application No. 278473, 1988 Semiconductor selective growth method, Agent, Sumitomo Electric Industries, Ltd. (Postal code 101) Chiyoda-ku, Tokyo 4th floor 5, Foresight Building, 3-5-2 Iwamotocho Date of amendment order: February 13, 1999 (Delivery date: March 7, 1999) "Detailed description of the invention" in the specification subject to amendment Each column and drawing

【図面の簡単な説明】[Brief explanation of the drawing]

7 補正の内容 (1)  明細書第5頁第6行目の「図(a)〜(d)
は」を「第1図は」に補正する。 (2)  明細書第8頁第11行目の「図(a)〜(e
)は」を「第1図は」に補正する。 (3)  図面を別紙の通り補正する。 以  上
7 Contents of amendment (1) “Figures (a) to (d)” on page 5, line 6 of the specification
"is" is corrected to "Figure 1 is". (2) “Figures (a) to (e)” on page 8, line 11 of the specification
) is corrected to ``Figure 1 is''. (3) Amend the drawing as shown in the attached sheet. that's all

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に光集積回路が形成される第1の層を結晶
成長させ、この第1の層上に絶縁膜と密着性が良い薄膜
を形成させた後、これら第1の層および薄膜を選択的に
除去し、除去後に残った第1の層および薄膜上に前記絶
縁膜を形成させ、除去部に電子集積回路が形成される第
2の層を選択的に結晶成長させる半導体選択成長方法。
After crystal-growing a first layer on which an optical integrated circuit is formed on a semiconductor substrate and forming a thin film with good adhesion to an insulating film on this first layer, these first layers and thin films are selected. a semiconductor selective growth method, the insulating film is formed on the first layer and the thin film remaining after the removal, and the second layer in which an electronic integrated circuit is formed in the removed portion is selectively grown as a crystal.
JP27847388A 1988-11-02 1988-11-02 Selectively growing method for semiconductor Pending JPH02125483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27847388A JPH02125483A (en) 1988-11-02 1988-11-02 Selectively growing method for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27847388A JPH02125483A (en) 1988-11-02 1988-11-02 Selectively growing method for semiconductor

Publications (1)

Publication Number Publication Date
JPH02125483A true JPH02125483A (en) 1990-05-14

Family

ID=17597821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27847388A Pending JPH02125483A (en) 1988-11-02 1988-11-02 Selectively growing method for semiconductor

Country Status (1)

Country Link
JP (1) JPH02125483A (en)

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