JPH02125355A - Data transferring method - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a peripheral device by waiting for the ready state of a data transmission/reception circuit while executing another processing at the time of data transfer from the peripheral device to a host computer. CONSTITUTION:When a ready signal is inputted from a data transmission/ reception circuit 5, one byte of transmission data is sent to the data transmission/reception circuit 5. Thereafter, the command processing, the processing of a key switch 7, the operation processing of a motor 8, or the like is executed until the next ready signal is inputted. Thus, the processing efficiency of a peripheral device is improved in comparison with a conventional method where the device 1 waits for the ready state without executing operations at all, and the throughput is improved.

Description

[Detailed Description of the Invention] (Summary) Regarding a data transfer method from a peripheral device to a host computer that operates according to instructions from a host computer, the present invention aims to improve processing efficiency of the peripheral device and responds to data transfer requests from the host computer. In a data transfer method in which a peripheral device transmits data stored in its output buffer to the host computer based on the data transfer method, a data transmitting/receiving circuit in the peripheral device is capable of transmitting data during normal processing by a central processing unit in the peripheral device. It is determined whether or not a ready signal has been input, and when the ready signal is input, an interrupt process is entered and a predetermined unit bit of the transmission data is transmitted to the host computer, and then the data to be transmitted is It is determined whether or not the data to be transmitted is exhausted from the output buffer, and if the data to be transmitted still remains, the routine for exiting from the interrupter processing routine is returned to the original normal processing. The configuration is such that data transfer is performed repeatedly every time the ready signal is input.

(Industrial Application Field) The present invention relates to a data transfer method, and more particularly to a data transfer method from a peripheral device that operates according to instructions from a host computer to a host computer.

Peripheral devices that operate according to commands from the host computer transmit data to the host computer based on data transfer requests from the host computer as necessary. During this data transfer, since the processing speed of the central processing unit I (CPU) inside the peripheral device is considerably faster than the data transfer speed, it is necessary to improve the processing efficiency and throughput of the CPU.

[Conventional technology]

FIG. 4 shows a flowchart for explaining the operation of an example of a conventional data transfer method. This flowchart shows each processing step by the central processing unit t (CPtJ) in the peripheral device. First, based on a data transfer request from the host computer, transmission data is stored in the output buffer in the peripheral device (step 531). Next, the transmitting circuit in the peripheral device is ready to transmit I! (Step 532: Determine whether the status is ready or not. If the status is ready, take out, for example, 1 byte of transmission data from the output buffer (Step 533), and send it to the transmission circuit (Step 534).
).

The transmitter circuit is in a busy state while receiving and transmitting data to the host computer, and becomes ready when the transmission of one byte of transmit data is completed.

Next, the CPU determines whether the output buffer is empty (step 535), and if it is not empty (that is, there is still data to be sent), the CPU determines whether it is ready again (step 531), and returns to the ready state. Then step S above! The processing operations from 3 to 835 are repeated again. In this way, all the transmission data stored in the output buffer is transmitted one byte at a time, and the output buffer? becomes empty and the data transfer ends (step 83B).

[Problem to be solved by the invention]

However, in the conventional data transfer method described above, it is determined in step 832 whether or not the data transmission circuit is in the ready state, and one byte of data is taken out from the output buffer only after the data transmission circuit is in the ready state. Since the data transfer rate between the peripheral device and the host computer is much slower than the processing speed of the CPU within the peripheral device, there is always a waiting time until the ready state is reached in step 832.

In the conventional data transfer method, the CPU in the peripheral device is exclusively used for processing steps 531-8311 during data transfer, so the waiting time until the transmission circuit becomes ready in step S32 is limited to the CPU. This resulted in nothing being done, resulting in wasted time and poor processing efficiency.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data transfer method that can improve the efficiency of peripheral device processing.

(Means for Solving the Problems) FIG. 1 shows a flowchart illustrating the principle of the data transfer method according to the present invention. In the method of the present invention, the central processing unit in the peripheral device performs normal processing (step S1), and at that time, a ready signal is supplied from the data transmitting/receiving circuit based on a data transfer request from the host computer. It is determined whether or not (step S2).

When a ready signal is input, interrupt processing begins.
Data transmission is performed for a predetermined unit bit of transmission data (
Step S3), it is determined whether all the transmission data is gone from the output buffer (Step 84).

If there is still data to be sent in the output buffer,
The interrupt processing routine is exited and normal processing resumes (step SI), and it is monitored whether a ready signal is input (step 82). If the ready signal is input during normal processing, the data is transmitted again (step S3) and the presence or absence of transmission data is checked (step 84).
).

In this way, if all the sent data is gone in the output buffer (if all the sent data has been sent)
Then, the transmission ends (step Ss).

Therefore, according to the present invention, when a ready signal is input, the transmission data is transmitted for a predetermined unit bit, and then the normal processing is immediately resumed without having a ready state, and during the normal processing, the ready signal is input again. Then, the next predetermined unit bit of transmission data can be transmitted.

(Embodiment) FIG. 2 shows a configuration diagram of a system to which an embodiment of the present invention can be applied. In the figure, 1 is a peripheral device, 2 is a host computer, and data is transferred between them. Peripheral device 1
is the central processing unit (CPLJ) 3, random access
Memory (RAM) 4° data transmission/reception circuit 5. Read-only memory (ROM)6. It consists of a key switch 7 and a motor 8.

RAM4 is an output buffer that temporarily stores transmitted and received data. The data transmitting/receiving circuit 5 receives data from the host computer 2 and sends the data to the host computer 2 from the CPU 1.
This is a circuit that transmits data from. Furthermore, when the data transmitting/receiving circuit 5 becomes ready for transmission, it generates a ready signal.
This is supplied to the interrupt request (IRQ) port of CPU3. The ROM 6 stores CPL 13 operating programs.

Here, the peripheral device 1 is, for example, a plotter, and based on data from the host computer 2, the CPLJ 3 controls the rotation of the motor 8 to drive the Benn carriage roller to draw a commanded image.

On the other hand, host computer 2 is a peripheral! In some cases, the host computer 2 requests the peripheral device 11 to transfer data.

Based on this data transfer request, in this embodiment, the CPU 3
performs data transfer based on a flowchart as shown in FIG.

The peripheral device af1 is performing normal processing shown in the 70-chart in FIG. Then, it is determined whether data output is being executed (step 5L2). Since the transmission data has not yet been output in the morning, data output has not been executed, and in this case, the data to be transmitted (transmission data) is stored in the output buffer (RAM4 shown in FIG. 2) (step So). .

Next, CPLJ3 sends the interrupt request (IRQ)
) is opened (step SN), command processing, key switch 7 processing, motor 8 operation processing, etc. are performed (step S+s). After the operation processing, the process returns to step Sn of checking the data to be transmitted.

In this way, based on the data transfer request from the host computer 2 described above, the CPU 3 in the peripheral device 1 performs normal processing to create an output buffer for sending data. After storing the data, command processing, key switch 7 processing, and motor 8 operation processing are performed.

Here, the CPU 3 opens the normally closed IRQ port in step SH, so when a ready signal is input from the data transmitting/receiving circuit 5 after this, it enters the interrupt process described later, but the IRQ port is not open. Even if a ready signal is not input, interrupt processing is not performed.

The ready signal is the command processing of step S+s,
Since the input is made during the processing period in which the key switch 7 processing and the motor 8 operation processing are being performed, the input of this ready signal causes the CPU 3 to interrupt the normal processing operation and interrupt the normal processing operation as shown in FIG.
The interrupt process shown in B) is automatically entered (steps S). The above corresponds to the processing of step S+, 82 in FIG.

Then, one byte of the transmission data is extracted from the output buffer (RAM4) (step 82+), and the extracted transmission data is sent to the data transmission/reception circuit 5 (step 522).
). This corresponds to the process of step S3 in FIG. As a result, one byte of transmission data starts to be transmitted from the data transmitting/receiving circuit 5 to the host computer 2.

Following the processing in step 822, the CPLI 3 determines whether the output buffer F (RAM 4) is empty (step 523), and determines whether there is still transmitted data in the output buffer. If the IRQ remains open, the interrupt handling routine is exited (step 52), leaving the IRQ port open.
Returning to step S5 of the command processing, key switch 7 processing, and motor 8 operation processing during the normal processing shown in FIG. 3(A), the processing is resumed from the processing operation immediately after the interruption. This corresponds to the processing of steps $4 and Sl in FIG.

Until the transmission of the 1-byte transmission data described above is completed, the normal processing shown in the flowchart of FIG. Send the ready signal again to CPU3
Input to RQ boat.

As a result, CPLJ3 performs step Ss in FIG. 3(A).
During the processing operation, the normal processing is interrupted by the input of the above-mentioned ready signal, and the interrupt processing shown in FIG. 7 and sends it to the data transmitting/receiving circuit 5, and checks whether the output buffer is empty. If it is not empty, the interrupt processing is exited and normal processing is resumed (steps 321 to S21.525).

Below, the same operation as above is repeated, and the output buffer (
If you take out all the transmission data from RAM4),
Close the IRQ port of CPU3 (step 824),
The interrupt process ends (step Sδ) and returns to the processing operation immediately after the interruption of step S+s of the normal process. , this corresponds to step S5 in FIG. By closing the IRQ port, no interrupt processing is performed even if a ready signal is subsequently input to the fRQ port.

Incidentally, during the normal processing operation shown in FIG. 3(A), when there is no data to be transmitted, and when the transmission data is being output, the processing in steps S11 and Sat is not performed, and the process moves to step S+s.

As described above, according to this embodiment, after one byte of transmission data is sent to the data transmitting/receiving circuit by inputting the ready signal from the data transmitting/receiving circuit 5, the period until the next ready signal is input is as follows. Command processing, key switch 7
processing, motor 8 operation processing, etc.
Compared to the conventional method of waiting for the next ready state without performing any operation, processing of the peripheral H1 can be made more efficient and throughput can be improved.

Note that the present invention is not limited to the above-described embodiments, but is applicable to all peripheral devices 1 that operate according to instructions from the host computer 2.

〔Effect of the invention〕

As described above, according to the present invention, when data is transferred from a peripheral device to a host computer, the ready state of the data transmitting/receiving circuit can be maintained while other processing is being executed, thereby increasing the efficiency of processing of the peripheral device. It is also possible to improve throughput.

[Brief explanation of the drawing]

Fig. 1 is a flowchart for explaining the principle of the present invention, Fig. 2 is a configuration diagram of a system to which an embodiment of the present invention can be applied, Fig. 3 is a flowchart for explaining the operation of an embodiment of the present invention, Fig. 4 is a flowchart for explaining the operation of a conventional example. In the figure, 81 to Ss are steps, 1 is a peripheral device, 2 is a host computer, 3 is a central processing unit (CPU), 4 is a random access memory, and 5 is a data transmission/reception circuit. (RAM)

Claims (1)

[Claims] In the data transfer method, the peripheral device (1) transmits data stored in its output buffer (4) to the host computer (2) based on a data transfer request from the host computer (2), wherein the peripheral device (1) The central processing unit (3) in the peripheral device (1) determines whether a ready signal indicating that the data transmission/reception circuit (5) in the peripheral device (1) is ready for transmission is input during normal processing (S_1, S_2). ),
When the ready signal is input, an interrupt process is entered and a predetermined unit bit of the transmission data is transmitted to the host computer (2) (S_3), and the data to be transmitted after that is no longer in the output buffer (4). If the data to be transmitted still remains, the interrupter processing routine is exited and the process returns to the original normal processing (S_4). A data transfer method characterized by repeatedly transferring data each time a signal is input.