JPH02125328A - Differential barrel shifter - Google Patents

Abstract

PURPOSE:To simplify a mechanism by detecting which exponent part in two numbers to be subjected to, e.g., justification is larger and whether the value of the difference between them exceeds the limit of data shift or not and divisionally calculating high-order bits and low-order bits of a mantissa parts. CONSTITUTION:An underflow detecting means 13 generates an underflow signal when detecting that the difference between control signals is negative in accordance with digit borrow signals generated by a first subtractor (lower bits) 10 and a second subtractor (upper bits) 11 and the difference output of the second subtractor 11, and a data shifting means 12 shifts all bits of input data (corresponding to the mantissa part data of two numbers expressed with floating-point numbers) in one direction by the value of the difference output of the first subtractor 10 and outputs results. An overshift detecting means 14 generates an overshift signal in the case of detecting that the difference between control inputs exceeds the shift limit of the data shifting means 12 in accordance with signals similar to respective signals inputted to the underflow detecting means 13. Thus, the constitution is simplified and the justification speed is increased.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a differential barrel shifter that operates based on the difference between two control signals, and in particular to digit alignment of floating point data input to an ALU. It is used.

(Prior Art) Floating point data can generally be represented by a mantissa (fixed point) and an exponent. To add or subtract two numbers expressed as floating point numbers, first compare them to make their exponent parts the same, and then change the mantissa part of the one with the smaller exponent part by the difference in the size of the exponent parts of the two numbers. Shift right (arithmetic shift). After this, addition or subtraction of the mantissa parts is performed, and the result is combined with the larger exponent part of the previously compared exponent parts. The operation of performing η before executing this calculation is called digit alignment (normalization before calculation).

The circuit conventionally used for digit alignment is replaced by a third circuit.
Shown in Figure 2. Now, let the two numbers whose digits are to be aligned be A and B respectively.
and each exponent part is A E .

The BE1 mantissa is represented by A and B. Bit M of 2 numbers
Assume that the number of blades is equal, the exponent part is N bits, and the mantissa part L bits, and when representing each bit, AE (N-1) to AEo
and AM(L-1) ~ AMo (exponent and mantissa part of one number "E(N-1) ~ BEO and" M(L-1)
~8M0 (the exponent part and the mantissa part of the other number).

In FIG. 32, 1 is a subtracter, 2 is a sign inverter, and 3 is an overshift detection circuit (detects whether or not a shiftable range has been exceeded within the barrel shifter). First, two exponent parts A and B are input to the subtracter 1, and the difference E (difference output of the exponent parts) d-A E -B E ...[11] is calculated. When d≧0, one mantissa part BM.

When d<O, the other mantissa part AM may be shifted.

The sign of d can be determined based on whether the borrow signal C of the subtracter 1 has become valid (active).

The shift amount of BM is bit f (DK-1D
, K-1og 2L) can be obtained by inverting the sign of f. Figure 32-2
is the sign inverter for that purpose. The output f' of the sign inverter 2 and the lower bit f of the output d of the subtracter 1 are supplied as control signals to a barrel shifter for shifting A and B, respectively.

By the way, when -L<d<L...[2], the above mechanism works normally, but when the absolute value of d becomes greater than or equal to the number of bits in the mantissa, f and f' cannot be shifted correctly. It no longer expresses quantity. This state will be referred to as overshift here. 3 in FIG. 32 is a detection circuit for detecting this. The overshift detection circuit 3 detects that d≦
-L ... [3] and d≧L ... [4] are discriminated, and when each state occurs, outputs g and g' are activated to notify the outside. Output g
and g', the upper bit e of the difference output d of subtractor 1 is
(D = D), N-I K and the borrow output C are required. When g' is active (valid), some operation is required on the output of the shifter that shifts AM or the control signal f' (for example, setting all bits of the shifter output to 0, or fixing f' to the maximum value). become. When g is valid, a similar operation is required for the BH shift result or control signal f.

(Problem to be Solved by the Invention) The subtracter 1 in FIG.
(Carry 1ook ahead) type is required. This is because when an N-bit subtracter is configured with a 1-bit subtracter of the borrow ripple type to which the borrow signal C is propagated,
The difference output is from the lower bit to the 0th bit D 1 1st bit D
1, and finally the entire borrow signal C (as an N-bit subtracter) is output, so the shift mf,
AM after f' is determined.

This is because it is necessary to wait until the subtraction for rN-KJ stages is completed until C, which determines which part of BM to shift, is obtained. Here, K = log 2 L
...[5]. This also applies to overshift detection.

The circuit shown in Figure 32 itself is not very large-scale, but
When supplying an output signal line to the mantissa shifter, it is necessary to cross many signal lines, so the area on the chip is consumed by wiring. To prevent this, considerable layout measures are required.

It is an object of the present invention to provide an actuated barrel shifter that operates on the difference between two control signals to simplify floating point alignment mechanisms.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention calculates the difference between the lower bits of two input control signals (corresponding to two number indicator data expressed in floating point numbers). a first subtracter that calculates the difference between the remaining upper bits of the control signal and generates a borrow signal; a second subtracter that calculates the difference between the remaining upper bits of the control signal and generates the difference and a borrow signal; underflow detection means for detecting that the difference between the control signals has become negative from the borrow signals generated by the first and second subtracters and the difference output of the second subtracter and generating an underflow signal; , a data shifting means for shifting all bits of the input data (corresponding to the mantissa data of two floating-point numbers) in one direction by the value of the difference output of the first subtracter, and outputting the resultant data; It is characterized by comprising overshift detection means for generating an overshift signal for detecting that the difference in control input exceeds the limit that can be shifted by the data shift means from a signal similar to each signal input to the flow detection means. It is a differential barrel shifter.

That is, the present invention can detect, for example, which of the two numbers to be digit-aligned has a larger exponent part, and whether or not the value of the difference exceeds the data shift limit. By being able to calculate (subtract) the lower bits separately, the above-mentioned conventional problems are eliminated.

(Example) FIG. 1 shows an example of the present invention. here 10 and 11
12 is a barrel shifter, 13 is an underflow detection circuit, and 14 is an overshift detection circuit. This circuit has one data input (the mantissa part of one number whose digits are to be matched) (L bits) p, and two control inputs (the exponent parts of the numbers A and B whose digits are to be matched) (N bits) a, b, and , one data output (mantissa after shift) (L bit) q, and two status signal outputs (underflow, overshift) u+v. Now, assume that one of the two control inputs is a1 and the other is b. The subtracter 10 receives the bit at at the lower end of a and the bit b1 at the lower end of b. A difference signal dl-bl-bl [6] and a borrow signal (Borrow 1 ) are output. The output d1 of the subtracter 10 is supplied as a shift amount to the barrel shifter 12 of the mantissa part p to be shifted, and the barrel shifter 12 receives this and outputs the input data p shifted to the right by d1 bits (arithmetic shift). Generate data q. Here, K and L are the [5]
It is assumed that the relationship of Eq.

On the other hand, the subtracter 11 has bits a and b in the upper N- of a.
The bit b2 is inputted to the upper N- of , and a difference signal a 2 = a 2 - b 2 [g] and a borrow signal are output. The above d, c and the borrow signal c1 of the subtracter 10 are input to an underflow detection circuit 13, and an underflow signal U (a detection signal indicating that q is incorrect because the difference between the two numbers has become negative) is generated. Ru. In addition, these input signals C, C.

d2 is also input to the overshift detection circuit 14, and an overshift signal (a detection signal indicating whether or not the shiftable range within the barrel shifter has been exceeded) is generated. The barrel shifter output q may be correct or incorrect depending on the values of U and V, and in this latter case it is necessary to notify the outside.

The above U is generated as follows. Each bit forming d2 is D (MSB), DN,.

D , ..., D , D (different from D - D in Figure 32) and N-I
It becomes K.

The overshift signal V is generated by the following equation.

[D +D +D ''=c2 N-I N-2N-3+D
+(D −C)] ...[11]K+
IK! In formula [10] and formula [111], "+" is a logical sum,
"・" represents logical product.

Components 10.11 and 13. for N-8 and L-32.
14 specific examples are shown in FIG. 2 to Ts6. FIG. 2 shows a specific example of the first subtracter 10 in FIG. Third
The figure shows a specific example of the second subtracter 11 in the same figure. The circuits of FIGS. 2 and 3 each have a 1-bit subtracter 20.
~24 and 25~27. An example of the 1-bit subtracter is shown in FIG. This logical formula is as follows.

D ■A i■BIO+C, -[121C-(A (
E)B)-C+A @B0 11
ill...[13] The truth table of this equation is shown in FIG. Here, e is exclusive or, and 0 is exclusive nor.

FIG. 5 shows the underflow detection circuit 13 in FIG.
FIG. 6 shows a specific example of the overshift detection circuit 14 (N-8
, L-32). In FIG. 5, when the borrow signal Borrov2 of the above bit is "1" (when the subtraction result is negative), the underflow detection signal U is unconditionally "al",
It becomes active (valid) and notifies the outside that data q is incorrect.

Furthermore, when the borrow signal Borrovl of the lower bit is 1m (when the subtraction result is negative), when D5 to D7 are “0#”, U
is active, but otherwise there is no problem. Furthermore, in FIG. 6, when Borrov2 is "0", there is a possibility of overshifting (■ is active). D, D
If any of the outputs of the Noah gate 51 is “1°, there is a possibility of overshifting.
If orrowl is "1", the detection condition is not met.

In the previous example, the formula [5] % was established between the number of bits of the mantissa and the number of bits of the control input to the barrel shifter 12. In actual applications, K > log 2 L ... [1
4] is also possible. An example in this case is shown in FIG.

In FIG. 8, 60.61 is a subtracter, 62 is a barrel shifter, and 63 is an underflow detection circuit.
These are the same as 10.11 and 12.13 in the figure. However, the bit width of the input/output signal of the barrel shifter 62 may be L≦2K...[15]. In other words, the number of bits of the barrel shifter 62 and the number of bits of the subtracter 60 do not correspond, for example, when the number of bits of the barrel shifter is small.

In FIG. 8, the overshift detection circuit 1 of FIG.
In addition to C1 and C2゜d in the circuit 64 corresponding to 4, some or all bits d of the difference output d1 of the subtractor 60
is input, and this is also set as a detection condition.

FIG. 9 shows an embodiment of the overshift detection circuit 64.

In this figure, 70 is a decoder, 71 to 73 are inverters,
74 to 76 are NAND gates, and 77 is a logic circuit that has the same function as the overshift detection circuit 14 of FIG. 1 and satisfies the logical formula [11]. The decoder 70 detects from one or all bits d of dl that the output of the subtracter 60 exceeds L-1 (L is the bit width of the input data p).

Now, L is expressed as a binary number of bits, and each bit is L (MSB), L , ・, L
, L.

Represented by K-I K-21 (LSB). Similarly, each bit of di is D
(MSB), D, ..., D, DK-I
When expressed as K-210 (LSB), the output of the decoder 70 is expressed by the following recurrence formula.

h −D −L +L ...[
16]hj −(D, ・h, > ΦL.

J J-I J + (D, +h, )-L, ... [17] J
J-I J However, j-1, 2,... hgreen hK-1... [18] Figure 10 shows an example when L-25-11001 (BIN). To design this, first use equation [16]. Calculate and substitute j-1 into equation [17] to get D
Determine the logical formula for and h (A N D, ・or OR1+O). Similarly, by sequentially determining the logical expressions for j-2, 3, and 4, the circuit shown in FIG. 10 is obtained. In the same figure,
80.81 is an OR gate, and 82.83 is an AND gate. If this circuit is configured using a large number of cadences,
The combination of OR gate 90 and AND gate 91° of FIG. 11 is obtained.

In the decoder circuit obtained from formulas [181 to [18],
The bit of dl corresponding to the part where 0 continues from the least significant bit (LSB) of L does not care, that is, it can be set to "1" or "0°. L-24 = 11000
FIG. 12 shows an example of a decoder circuit for (B+N), and FIG. 13 shows a simplified circuit. In some cases, as shown in this figure, it is sufficient to input a part of dl as d, and in other cases, it is necessary to input d - dl as in the examples of FIGS. 10 and 11. In Figures 12 and 13, 1
00, 101 are OR gates, and 102°, 103, and 110 are AND gates.

Using the above, the overshift detection circuit (Fig. 8 64)
) output V' is v' mc (D +D +...+DK
+12 N-I N-2 + (D ・c) + [h・(D + o 1) Month K
I K ...[19] It can be expressed as follows.

FIG. 14 shows an example of an overshift detection circuit in the case of N-8, L-24, and -5. In the figure, 120 to 122 are inverters, 123 to 124 are NAND gates, and 125 is a composite gate AND-NOR (125a is AND, 125b
is the NOR part), and 126 to 128 are NOR gates.

When using the operating barrel shifter of the present invention to align floating point data, in the previous two examples, an external circuit must select whether to use the output of the barrel shifter or to use the input before shifting as is. .

FIG. 15 shows that when the underflow signal U becomes valid, the input p instead of the output q of the barrel shifter is
This is an example in which the output of this circuit can always be used in the external circuit during the digit alignment operation by outputting . Reference numeral 135 is a selector for this purpose, but its output `` is not subjected to data shifting when the input p is obtained as is. 130 and 131 in FIG. 15 are subtracters;
32 is a barrel shifter, 133 is an underflow detection circuit, and 134 is an overshift detection circuit, which operate in the same manner as 60 to 64 shown in FIG.

135 is a selector for switching the output.

The logical expression representing the operation of the above selector is as follows.

r ■p ・ u+q ・ U ・
... [20] In the above formula, p-u is the q of each bit of p and U
``u'' represents the logical product of each bit of q and U, and means that the logical sum is performed between the corresponding bits of pu and q''u. The first example of the selector 135 is
It is shown in Figure 6. In this figure, 140.141 is the inverter, 1
42 is a 2-input, 1-output (selects Q or P) selector shown in FIG. FIG. 17 shows the unit circuit 142 of FIG.
This is an example. 150 to 152 in the figure are NAND gates. In Figure 16, P -P, Q -Q
, R,1 to L-1OL-10 Ro represent each bit constituting the mantissa data 1 shifter output q1 selector output r.

When the overshift signal V becomes valid, the shift amount d
Since l does not indicate a correct value, the value of the output q of the barrel shifter is of no use.

FIG. 18 is an example of the differential barrel shifter of the present invention in which all bits of output data become "0" when overshift occurs. If the shifter outputs are all "0", it can be considered that all the data has been shifted. 160 and 161 in FIG. 18 are subtracters, 162 are barrel shifters, and 16
3 is an underflow detection circuit, 164 is an overshift detection circuit, and 165 is a selector, each of which operates in the same way as 130 to 135 in the example shown in FIG. 166 is a zero output circuit.

The operation of the zero output circuit 166 is expressed by the following logical formula.

W■r"v...[21] The logical product "." in the above equation has the same meaning as in equation [20]. An example of a zero output circuit is shown in FIG.

In the same figure, 170 and 171 are inverters, and 172 is NAN.
This is the D gate. Further, W −W represents each bit of W.

When an overshift occurs and shifter output q becomes unavailable, it outputs zero in the previous example. In the overshift state, zero is considered to be the most useful output data, but there may be cases where data other than zero is required. FIG. 20 shows a differential barrel shifter of the present invention that outputs arbitrary data φ input from the outside when an overshift occurs. For example, when the zero output circuit 166 in FIG. 18 is replaced with the selector 186 and overshift is performed, data φ is output to the output W'.

In FIG. 20, 180 and 181 are subtracters, 182 is a barrel shifter, 183 is an underflow detection circuit, 184 is an overshift detection circuit, and 185 is for switching the output q of the barrel shifter and the input data p according to the underflow signal U. The first selectors of FIG. In this example, the first
A second selector 186 replaces the zero circuit 166 in FIG.
is connected to select the output signal W' as either r or φ.

The operation of the second selector 186 is expressed by the following logical expression.

W' − "・V' +φ ・V' ・・・
[22] The meaning of the logical product “・” and the logical sum “+” in the above formula is
This is the same as that of equation [20]. Second selector 18
6 is the same as the first selector 185, for example, the 16th selector
17 can be used.

When an external circuit calculates the data after the digit alignment is completed, only the larger exponent part of the two numbers whose digits have been aligned is used as the exponent part. In the examples shown so far, it is necessary to select the exponent part using an external circuit using an underflow signal.

FIG. 21 shows a differential barrel shifter of the present invention incorporating the above exponent selection function. In this figure 21 it is 190.19
1 is a subtracter, 192 is a barrel shifter, 193 is an underflow detection circuit, 194 is an overshift detection circuit, 1
95 is a first selector for underflow processing, 1
96 is a zero output circuit for overshift processing, each of which operates in the same way as each section 160 to 166 in FIG. 18. 197 is a second selector that selects and outputs either control signal a or b. For example, if there is an underflow, issue b (B), otherwise, issue a (A).
issue.

The second selector 197 performs the operation expressed by the following logical formula.

zswa * u+b a u...423]
Here, 2 is the output of the selector 197. In the above formula, the meaning of the logical product “・” and the logical sum “+” symbol is the [2nd
0] is equivalent to that in Eq. This selector can also be configured as shown in FIG. 16 using the unit circuit shown in FIG. 17. However, the number of unit circuits 142 used may be N.

When using the differential barrel shifter of the present invention as an individual component, it is convenient to be able to externally specify the value of dl to be overshifted, that is, the number of bits of the mantissa. FIG. 22 shows an example in which this can be done.

In FIG. 22, 200° 201 is a subtracter, 202 is a barrel shifter, and 203 is an underflow detection circuit.
The same operations as 190 to 193 in the figure are performed. However, the number of input/output bits of the barrel shifter 202 is not L but 2K (≧L) because the mantissa bit width is variable. 20
4 is an overshift detection circuit.

205 is a first selector for underflow processing;
206 is a zero output circuit for overshift processing, 2
Reference numeral 07 represents a second selector for selecting a control signal, and each operates in the same manner as 195 to 197 in FIG. However, the number of input/output bits of the first selector 205 and the zero output circuit 206 is equal to that of the barrel shifter 202. The overshift detection circuit 204 also includes outputs C, d, c, d of the subtracters 200 and 201,
l 1 2 2 Determine the shift limit (exceeding this will result in overshifting)
An external input S is supplied and an overshift signal V' is output. In other words, a warning is issued to the outside.

An example of the overshift detection circuit 204 is shown in FIG. 210 in FIG. 23 is a magnitude comparator, 211 to 213 are inverters, and 214 to 216 are N
The AND gate 217 is the same circuit as the overshift detection circuit 14 of FIG. 1 that satisfies the formula [11], and S is the bit number input.

Assume now that the bit number input S is 5-L-1...[24]. At this time, the output h' of the magnitude comparator becomes. S is expressed as S (M
SB), S,..., 5SK-I
It can be expressed as K-21' 0 (LS B). Using this, the logical formula for generating h' is a, -D-OS,, j -0,1,...=, K
-1...42B] J here + aEl.

-1 to °°°＋α α Red D “K-2°DK-3.

・α °“K-2K-3 ・S.

S +... ...[27] becomes. The bit width of the mantissa that can be specified by the input S is 1≦L≦2 and 0≦S≦2−1) [28]. Using the above h', the logical formula for the output V' of the entire circuit is expressed as follows.

V −C・(D +D +...2
N-I N-2 +D + (D or C)K+l
K 1 + [h' ・(DK+C1)]) ... [29] In Fig. 24, a 5-bit magnitude comparator 21 is shown.
An example of 0 is shown. In Fig. 24, 220 to 224 are inverters, 225 to 234 are NAND gates, and 235 is a NOR gate.
Gates 236-239 are composite gates 0R-NAND
(236a to 239a are OR parts, 236b to 239
b is a NAND partial piece.

Figure 25 shows N-8, -5, 1≦L≦32 (0≦S≦3
An example of the overshift detection circuit of 1) is shown below.

In this figure, 240 is the 5-bit magnitude comparator shown in FIG. 24, 241 to 243 are inverters, 244 to 246 are NOR gates, and 247 to 249 are NOR gates.
It is an AND gate.

Two differential barrel shifters of the present invention are required for digit alignment of floating point data. In the above example, one shifter requires the control input connections to be reversed from the other shifter. That is, for data A, set B to a%AE
input as b, and for data B, input A asBB
is input as b. FIG. 26 shows a differential barrel shifter of the present invention in which the order of subtraction of control inputs can be switched between a-b and ba. Figure 26-2
50 to 251 are subtracters to which a switching input t in the direction of subtraction can be supplied. 252 is a barrel shifter, 253 is an underflow detection circuit, 254 is an overshift detection circuit, 2
55 is a first selector for underflow processing, 2
56 is a zero output circuit for overshift processing, 257 is a second selector for control input selection;
It operates in the same way as each section 202 to 207 in FIG.

The output d1 of the first subtractor 250 is determined by the switching input t as follows. In the second subtractor 251, the following is true.

FIGS. 27 and 28 show examples of the subtracter when the number of exponent bits is N-8 and the number of shifter control input bits is -5. 260 to 267 in these figures are 1-bit subtracters with a subtraction direction switching input.

FIG. 29 shows an example of the above-mentioned 1-bit subtracter with a subtraction direction switching input. 270 in this figure is an inverter, 271 to 27
5 is a NAND gate, 276 to 278 are honorable gates 0R
-NAND (276a to 278a are OR, 276b
~278b is the NAND part).

The logical formula of the above subtracter is expressed by the following formula.

D-A1■B1■C1...[32] C-(AlOBl)・C1 ...[33] The truth table for this circuit is shown in FIG.

According to the present invention, digit alignment of floating point data can be performed using only two differential barrel shifters. FIG. 31 shows the connection method with the ALU. 280 to 281 in this figure are differential barrel shifters of the present invention, an example of which is shown in FIG. 21.

282 is an ALU. As shown in the diagram, each block 280~
The wiring in the region 283 between the wirings 282 and 282 is simple, and there are extremely few crossings between the wirings. Further, as a subtracter which is a component of the machine, a simple type of borrow signal propagation type (borrow ripple type) as shown in FIGS. 2 and 3 can be used. In FIG. 1, the signal controlling the barrel shifter 12 is the output of the subtracter 10, which is Do from the 0th digit to the 11th digit.

The order is determined as D , . . . , D . Barrel holder
By arranging the shift stages of the K-1 lid in this order from input to output, it is possible to offset the control signal generation time and the delay time of the barrel shifter, and this also applies to the prior art. However, in the conventional configuration (FIG. 32), the signals from the 1st digit to the N-1st digit are replaced by the signal D at the 11th digit.
−1 is generated later. Since signals of these digits are necessary for detecting the underflow and overshift described above, it is necessary to wait for the signal of -N-1 digits to be completed after the shift is completed in order to perform the processing. Therefore, in the past, attempts were made to increase the speed by using a CLA type subtracter. In the method of the invention, the signal is Since the control signal l K+1 of the barrel shifter and the signal for exception handling are generated simultaneously in the order of D and D, and D and D,
Problems like the conventional example do not occur.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, the application of the present invention is not limited to digit alignment during addition and subtraction. Further, the configuration of the present invention can be a combination of the first embodiment and the main parts of the second to eighth embodiments.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a differential barrel shifter that has a simple configuration, a high-speed digit alignment operation, and is suitable for integration into an integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of the first embodiment of the present invention, FIGS. 2 to 6 are partial circuit diagrams of the same configuration, FIG. 7 is a diagram showing its operation, and FIG. 8 is a diagram of the second embodiment of the present invention. The configuration diagram of the embodiment, FIGS. 9 to 14 are partial circuit diagrams of the same configuration, FIG. 15 is a configuration diagram of the third embodiment of the present invention, and FIGS. 16 and 17 are part of the same configuration. The circuit diagram, FIG. 18 is a configuration diagram of the fourth embodiment of the present invention, FIG. 19 is a partial circuit diagram of the same configuration, and FIG. 20 is a diagram of the fifth embodiment of the present invention.
FIG. 21 is a configuration diagram of the sixth embodiment of the present invention, FIG. 22 is a configuration diagram of the seventh embodiment of the present invention, and FIG.
Figures 25 to 25 are partial circuit diagrams of the same configuration, Figure 26 is a configuration diagram of the eighth embodiment of the present invention, Figures 27 to 29 are partial circuit diagrams of the same configuration, and Figure 30 is the same configuration. FIG. 31 is a diagram showing the overall configuration when digit alignment of floating point data is performed using the above embodiment, and FIG. 32 is a diagram showing the configuration of a conventional device. 10.11,60,61,130,131゜160.1
61,180,181,190゜191.200,20
1,250.251...Subtractor, 12.62,132
, 162, 182° 192.202, 252...Barrel shifter, 13° 63.133. 163,183,
193゜203.253... Underflow detection circuit, 14゜64.134, 164, 184, 194, 25
4... Overshift detection circuit, 135, 165°1
85.186,195,197,205°207.25
5,257...Selector, 166°196.206.
256...Zero output circuit, 280°281...Differential barrel shifter. Applicant's agent Patent attorney Takehiko Suzue One mantissa Fig. Fig. Fig. Fig. Fig. 10 Fig. Fig. 12 ver Fig. 14 Fig. 16 Fig. 23 Fig. 24rg Fig. 25 Fig. 27 Fig. 29 For example, 260 Figure 30

Claims (8)

[Claims] (1) A first subtracter that calculates the difference between the lower bits of two input control signals (corresponding to exponent data of two numbers displayed in floating point) and generates the difference and a borrow signal; , a second subtracter that calculates a difference between the remaining upper bits of the control signal and generates the difference and a borrow signal; and a borrow signal generated by the first and second subtracters and the second subtracter. an underflow detection means for generating an underflow signal by detecting that the difference between the control signal and the difference output of the first subtractor has become negative; data shifting means for shifting all bits in one direction (corresponding to the mantissa data of two decimal numbers) and outputting the same; A differential barrel shifter comprising: overshift detection means for generating an overshift signal for detecting that the difference exceeds a limit that can be shifted by the data shift means. (2) In addition to the signal input to the underflow detection means, part or all of the difference output of the first subtracter is also input to the overshift detection means to perform overshift detection. The differential barrel shifter according to claim 1. (3) The differential differential according to claim 1, further comprising output data switching means for outputting the input data instead of the output of the data shifting means when the underflow signal becomes valid. barrel shifter. (4) The device further comprises a zero output circuit that sets all bits of the output of the data shift means or the output of the output data switching means to 0 when the overshift signal becomes valid. or the differential barrel shifter described in 3. (5) A data selector is provided in place of the zero output circuit, and means is provided for outputting an external input signal different from the input data when the overshift signal becomes valid via the selector. The differential barrel shifter according to claim 1 or 4, characterized in that: (6) When the underflow signal is in a valid state,
Claim 1, further comprising control signal selection means for selecting and outputting one of the two control signals.
Differential barrel shifter as described in . (7) The overshift detection means is provided with a shift amount upper limit setting means that is provided with an input terminal for inputting a shift amount limit from the outside, thereby making it possible to set an upper limit of the shift amount. The differential barrel shifter according to item 1. (8) For the first and second subtracters, the order of the two numbers to be subtracted can be set, so that the two control input functions (switching the number to be subtracted and the number to be subtracted)
2. The differential barrel shifter according to claim 1, further comprising means for making the barrel replaceable.