JPH02123593A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To minimize the peak current of an amplifier circuit without lowering an operating speed by causing to flow a low peak current to the circuit when the operation of a sense amplifier starts and causing to flow another current to make the operating speed into a high speed to the circuit immediately before the operation completes. CONSTITUTION:The circuit is composed so that a switching circuit SW1 can change from an OFF state to an ON state, and a switching circuit SW2 can change from the ON state to the OFF state when a control terminal, which is not shown in a figure, is changed to 'H'. Thus, a constant current from a constant current source I1 is caused to flow to a capacitor C1, and both- terminal voltage of the capacitor C1 gradually increases. On the other hand, since the both-terminal voltage of the capacitor C1 is impressed between the gate and the source of a MOS transistor M10 and between a control terminal T1 and a voltage input terminal VDD, the drain current of the transistor M10 is specified, and a sense amplifier circuit 2 operates with the minimum through flow current at a slow speed when its operation starts, and the operating speed becomes higher with lapse of time. Consequently, the through flow current of a bit line is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a method suitable for achieving high-speed and low peak current operation of a semiconductor memory device.
This invention relates to a sense amplifier control circuit.

[Conventional technology]

FIG. 7 shows a circuit diagram of an example of a conventional semiconductor memory device. In FIG. 7, 1 is a sense amplifier control circuit, 2 is a sense amplifier circuit, 3 is a precharge circuit, and 4 is a memory cell circuit. Also, Ml.

M2. M3 is a PMOS transistor (hereinafter referred to as a transistor), MA, M5. MB, M7. MB, MA, M
B is an NMOS transistor (hereinafter referred to as a transistor), CA and CB are capacitors, INV is an inverter circuit, and VD
D, VPC are voltage input terminals, SA, PC, WA, WB,
Tl and I2 are control terminals, and BL and BLB are bit lines.

FIG. 8 is a time chart showing the operation of the conventional circuit shown in FIG. In the figure, the horizontal axis indicates time. Further, PC, WA, WB, and SA are control terminals PC, WA, and WB of FIG. 7, respectively.

Indicates the voltage of SA. Furthermore, BL and BLB indicate the voltages of the bit lines BL and BLB in FIG. Furthermore, ISA indicates the drain current of the transistor M1 in FIG. 7, that is, the current consumption of the sense amplifier circuit 2. Below, Figures 7 and 8
The operation of this conventional circuit will be explained using figures. Below, to simplify the explanation of the operation, the voltage input terminals VDD and v
It is assumed that voltage sources of 5v and 2.5v are connected to the PCs, respectively.

Time t. , the voltage of the control terminal PC is Qv (hereinafter 1
1 L I+) to 5v (hereinafter referred to as ``'H'')
change to As a result, both transistors M7°MB are turned on, and the voltages on the bit lines BL and BLB are both 2.
It becomes 5v.

Next, at time t, the control terminal PC is changed to 'L', and furthermore, at time t2, the control terminal WA is changed to 'HD'. As a result, transistor M7. Both M8 are in the off state, transistor MA is in the on state, and the electric charge stored in the capacitor CA changes the potential of the bit line BL, so that the data stored in the capacitor CA selected by the control terminal WA is read out to the bit line BL. . However, as is well known, the change in the potential of the bit line BL at this time is small, on the order of several hundred mV. Therefore, it is necessary to amplify this read signal.

Therefore, at time t, the control terminal SA is set to 11H.
Change it to 11. As a result, the gate voltage of the transistor M6 changes to 1'HII, the gate voltage of the transistor M1 changes to u L pr by the operation of the inverter circuit INV, and both transistors M1 and M6 are turned on.

Here, the transistor M2 . M4. Transistor M3. As is well known, M5 each constitute a CMOS inverter circuit, and the input and output of the two inverter circuits are connected to each other to provide positive feedback. Therefore, at time t3, transistors M1 and M6 are turned on, so that current is supplied to the inverter circuit pair and bit 4*BL.

It operates to compare the potentials of BLB and amplify this differential voltage. Note that due to the above amplification operation, the bit lines BL, BL
When the potential of B approaches 5V and Ov, respectively, the transistor M
3. The source-drain voltage of M4 decreases, and eventually transistor M3. 'M4 is turned off, and the operating current ISA of the sense amplifier circuit 2 decreases to zero. after that,
At time t41t, control terminals WA and SA are set to II L
II, from time t, to time t. Repeat the steps from.

Note that related devices of this type include, for example, 1
Nikkei Electronics February 11, 1985, No. 246
Discussed on pages 249-249.

Now, considering the operating speed of the sense amplifier circuit 2, as is well known, the operating speed of the transistors M1 to M6 is
It is determined by the gate width/gate length ratio (hereinafter referred to as W/L). Generally, the sense amplifier circuit 2 is required to operate at high speed, and for this reason, the transistors M1 to M6
The desired operating speed is obtained by setting a large W/L.

However, in this case, as is well known, the peak current value becomes large, resulting in problems such as increased power consumption and noise generation due to power supply impedance.

[Problem to be solved by the invention]

Now, let us consider reducing the peak value of the current supplied during the operation of the sense amplifier circuit 2 in the prior art. As is clear from the explanation of FIGS. 7 and 8, this peak current value is
3. It is determined by the through current of the inverter circuit pair consisting of M5.

Therefore, in order to reduce the peak current, the transistor M
It is clear that the gate width/gate length ratio of 1 to M6 can be reduced. As a result, the peak current is reduced as shown by the broken line in FIG. 8 SA. However, in this case, the operating speed of the sense amplifier decreases as shown by broken lines in BL and BLB in FIG. 8, resulting in malfunction.

That is, an object of the present invention is to provide a semiconductor memory device including a sense amplifier control circuit that can reduce peak current without reducing the operating speed of the sense amplifier.

[Means to solve the problem]

The above object is achieved by configuring the sense amplifier control circuit by constant current source means, constant current switch means, capacitance, and voltage generation means.

[Effect]

The constant current means generates a constant current. The constant current switch means operates to cause the constant current to be turned on and off by external control to flow through the capacitor.

The voltage generating means receives the potential difference between the electrodes at both ends of the capacitor, and this potential difference is applied to the control transistor (transistor Ml in FIG. 7) of the sense amplifier.

The voltage is applied between the gate and source of M6).

As a result, the control transistor of the sense amplifier operates as a weak constant current source when the sense amplifier starts operating, and the peak current of the sense amplifier does not exceed this current. Further, immediately before the sense amplifier operation ends, the control transistor operates as a strong constant current source, and the sense amplifier operates at high speed. That is, since the peak current can be reduced without reducing the operating speed of the sense amplifier, malfunctions will not occur.

〔Example〕

Examples of the present invention will be described below. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Components that are the same as the conventional circuit shown in FIG. 7 or have the same functions are given the same reference numerals, and a detailed explanation thereof will be given. is omitted.

In Fig. 1, C1 is a capacitor, 11 is a constant current source, and SWI
, SW2 is a switch circuit, Mlo is a PMOS transistor (hereinafter referred to as a transistor), and M11 is an NMo5 transistor (hereinafter referred to as a transistor). Furthermore, 2 is a sense amplifier circuit whose internal configuration is exactly the same as the circuit shown in FIG.

FIG. 2 is a time chart showing the operation of this embodiment, and the same terminal voltages and times are given the same symbols as in the operation time chart of the conventional circuit shown in FIG. Explanation will be omitted. In Figure 2, SWI, SW
2 indicates the on/off state of the switch circuits SWI and SW2, respectively, and VC indicates the voltage across the capacitor C1.

The operation of this embodiment will be described below with reference to FIGS. 1 and 2. Note that time t is used to simplify the explanation of the operation. From t3
and from time t4 to time t.

Although the explanation of the operation up to this point will be omitted, the operation during the above period is exactly the same as the operation of the conventional circuit described above.

Now, at time t3, control terminal SA (not shown) is set to #H.
If it is changed to I+, as a result, the switch circuit S
The state of WI changes from off to on, and the state of switch circuit SW2 changes from on to off. This results in
A constant current supplied by the constant current source 1 flows through C1, and the voltage vC across the capacitor C1 gradually increases as shown in the following equation.

Here, 11 is the current value of constant current source 1, C1 is the capacitance C1
The capacitance value, T, is the elapsed time from time t3.

On the other hand, the relationship between the gate-source voltage and drain current of a MOS transistor is expressed by the following equation.

rD=p-(Vas-Vzb)"-(2)
Here, ID is a train current, β is a constant, Vas is a gate-source voltage, and (2) is a threshold voltage of a transistor. In FIG. 1, the gate of transistor M10
A voltage VC across the capacitor C1 is applied between the sources and between the control terminal T1 and the voltage input terminal VDD. Therefore,
A drain current expressed by the following equation flows through the transistor M10.

Here, ID. is the drain current of transistor M10, β□. is a constant.

According to the above explanation, the transistors M1 and M6 of the sense amplifier circuit 2 operate so that a current having a change over time similar to that shown in equation (3) flows.

As a result, the sense amplifier circuit 2 operates at a low speed with little through-current immediately after time t3, and operates at a faster operation speed after time has elapsed. Note that it is clear that when the operating speed becomes faster, the potentials of the bit lines BL and BLB are amplified to some extent, and the through current may be small.

That is, this embodiment has the effect that the peak current can be reduced without reducing the operating speed of the sense amplifier.

Note that in this embodiment, the circuit for applying the voltage across the capacitor C1 to the control terminal 'r2 does not need to be a circuit using the transistors M10 and M11 shown in FIG.
It is clear that circuits that perform similar operations may be used.

Next, other embodiments according to the present invention will be explained sequentially from FIG. 3 onwards.
Components that are the same or have the same functions as those shown in FIGS. 1 and 2 are given the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 3, M12 is a PMOS transistor (hereinafter referred to as a transistor). Moreover, FIG. 4 is a time chart showing the operation of the embodiment shown in FIG. The operation of this embodiment will be described below with reference to FIGS. 3 and 4.

In FIG. 3, a voltage equal to the sum of the voltage across the capacitor C1 and the voltage drop across the transistor M12 is applied between the gate and source of the transistor M10. Here, time t,
When the switch SWI is turned off and the switch SW2 is turned on, the constant current supplied by the current source 11 is transferred to the capacitor C1.
The current flows through a circuit connected in series with the transistor M12 and the transistor M12. Therefore, the gate-source voltage VCR of the transistor M10 when time T has elapsed from time t3 is the sum of the above-described equation (1) and the gate-source voltage of the transistor M12, and is expressed by the following equation.

Here, β and 2 are constants. Further, the voltage VCH causes the transistor M10 to operate so as to flow a drain current expressed by the following formula.

That is, in this embodiment as well, the sense amplifier circuit 2 is
It is clear that the device operates at a low peak current immediately after the start of operation and at high speed just before the end of operation, and has the same effect as the embodiment shown in FIG.

In this example, the element connected in series with the capacitor C1 was the PMOS transistor M12, but this
It is obvious that impedance means such as an OS transistor or a resistor may be used.

Next, another embodiment of the present invention shown in FIG. 5 will be described. In FIG. 5, M21 is a PMOS transistor (hereinafter referred to as a transistor), M22. M23. M
24. M23 is a MOS transistor (hereinafter referred to as a transistor), 12 is a constant current source, and VRI and VH2 are voltage sources, respectively.

Further, FIG. 6 is a time chart showing the operation of the embodiment shown in FIG. In FIG. 6, VRI.

VH2 indicates the voltages of voltage sources VRI and VR2, respectively. The operation of this embodiment will be described below with reference to FIGS. 5 and 6. Note that to simplify the explanation of the operation, the voltage sources VRI, V
It is assumed that the voltages of R2 are both 2V.

II L II at the control terminal SA before time t3
is applied. As a result, transistor M22 is turned off, transistor M23 is turned on, and capacitor C1
No current flows through. Further, the transistor M21 is turned on, and the voltage across the capacitor C1 becomes zero. Furthermore, the gate of the transistor M25 is at the same potential as the voltage input terminal VDD, and as a result, the transistor M24 is in an off state and the transistor M25 is in an on state.

Next, at time t, the control terminal SA changes to 1'H#. As a result, transistor M21 is turned off. Furthermore, the transistor M23 is in an off state, and the transistor M2
2 is turned on, and a constant current supplied by the constant current source 11 begins to flow through the capacitor C1. That is, the voltage VC across the capacitor C1 gradually increases from time t as shown by the following equation.

Next, consider a case where the voltage VC across the capacitor C1 becomes equal to or higher than the voltage of the voltage source VR2, that is, equal to or higher than 2V at time tax. At this time, the transistor M24 changes from off to on, and the transistor M25 changes from on to off. As a result, a current equal to the sum of the current of the current source 11 and the current of the current source 12 flows through the capacitor C1, and the voltage V across the capacitor C1 flows.
C rapidly increases from time t to t as shown in the following equation.

Here, 12 is the current value of the current source 12, and T2 is the elapsed time from time t31.

That is, based on the above explanation of the change in the voltage across the capacitor C1, the sense amplifier circuit 2 operates at a low peak current immediately after the start of operation, at high speed just before the end of the operation, and at high speed, similar to the other embodiments already described. It is clear that this embodiment has the same effect as the embodiment shown in FIG.

〔Effect of the invention〕

According to the present invention, since it is possible to control the operation of the sense amplifier as a circuit with a low peak current at the start of operation and as a circuit with high operation speed immediately before the end of operation, the sense amplifier circuit can peak current can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is an operation time chart of the embodiment shown in FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. FIG. 3 is an operation time chart of the embodiment shown in FIG. 5, FIG. 5 is a circuit diagram of still another embodiment of the present invention, FIG. 6 is an operation time chart of the embodiment shown in FIG. A circuit diagram showing a conventional example, Fig. 8 is the 7th
An operation time chart of the conventional example shown in the figure is shown. C1... Capacity, It, I2... Constant current source, 2...
sense amplifier circuit. Fig. 1 Award color Δ column (1) Fig. Minoru Takaya #'1 (1) Operation time + mart t. t+ tz t+tstt t+tst t+tstt t+ttt t+ttt t+ttt t+ttt t+tt for t+ttt. t+ tz tB? 4 ta t6 Waiting room diagram collection 6 Diagram refreshing solution 11 (3) Moving inlet immuch V-to i3+ t415 Time collection diagram collection 8 Figure Conventional circuit operation time chart rtz dst6 Question

Claims (1)

[Claims] 1. First control terminal (T1) for controlling amplification operation
and a second control terminal (T2), and a first voltage source (VDD
), a first transistor (M1) whose source electrode is connected to the first voltage source (VDD) and whose gate electrode is connected to the first control terminal (T1), and a second voltage source (ground ), a second transistor (M2) whose source electrode is connected to the second voltage source (earth) and whose gate electrode is connected to the second control terminal (T2), and the first transistor (M1). ) and a signal amplifying means (M2 to M5) connected between the drain electrode of the second transistor (M2) and the second transistor (M2) for amplifying and outputting a signal. , a capacitor (C1), a constant current supply means for supplying a constant current to the capacitor (C1) via a first on/off means (SW1), and a constant current supply means connected between both ends of the capacitor (C1). In addition to comprising a second on/off means (SW2), the capacitor (
A voltage applying means (M10) that applies a voltage related to the voltage across the voltage source (C1) between the first voltage source (VDD) and the first control terminal (T1), or a voltage applying means (M10) that applies a voltage related to the voltage across the voltage source (C1); 1. A semiconductor memory device comprising one or both of voltage applying means (M11) applied between a ground) and a second control terminal (T2). 2. First control terminal (T1) for controlling amplification operation
and a second control terminal (T2), and a first voltage source (VDD
), a first transistor (M1) whose source electrode is connected to the first voltage source (VDD) and whose gate electrode is connected to the first control terminal (T1), and a second voltage source (ground ), a second transistor (M2) whose source electrode is connected to the second voltage source (earth) and whose gate electrode is connected to the second control terminal (T2), and the first transistor (M1). ) and a signal amplifying means (M2 to M5) connected between the drain electrode of the second transistor (M2) and the second transistor (M2) for amplifying and outputting a signal. a capacitor (C1) having one electrode connected to the first voltage source (VDD); and a first switch circuit (SW1) having one side connected to the other electrode of the capacitor (C1). , a current source means (I1) connected to the other side of the first switch circuit (SW1), a second switch circuit (SW2) connected between both electrodes of the capacitor (C1), and the capacitor. (C1) and the first switch circuit (SW1), and the first control terminal (T1), the second control terminal (T2), or both. Capacitance (C1) and first switch circuit (SW1)
The voltage applied between the connection point with the first voltage source (VDD) and the first voltage source (VDD), or the voltage that increases or decreases in the same way as the voltage, is applied between the first voltage source (VDD) and the first control terminal. (T1
), or between the second voltage source (earth) and the second control terminal (T2), or output means (M10, M11) for outputting between the second voltage source (ground) and the second control terminal (T2), or both. A semiconductor memory device characterized by: 3. The semiconductor memory device according to claim 2, wherein an impedance is provided between the electrode of the capacitor (C1) on the side connected to the first voltage source (VDD) and the first voltage source (VDD). A semiconductor memory device characterized in that a means (not shown) is connected thereto. 4. The semiconductor memory device according to claim 2, wherein the first switch circuit (SW1) and the current source means (11
) and the first voltage source (VDD), a third switch circuit (M23) is provided. 5. First control terminal (T1) for controlling amplification operation
and a second control terminal (T2), and a first voltage source (VDD
), a first transistor (M1) whose source electrode is connected to the first voltage source (VDD) and whose gate electrode is connected to the first control terminal (T1), and a second voltage source (ground ), a second transistor (M2) whose source electrode is connected to the second voltage source (earth) and whose gate electrode is connected to the second control terminal (T2), and the first transistor (M1). ) and a signal amplifying means (M2 to M5) connected between the drain electrode of the second transistor (M2) and the second transistor (M2) for amplifying and outputting the signal. In the device, a third voltage source (VR1), a third control terminal (SA), a capacitor (C1) having one electrode connected to the first voltage source (VDD), and the capacitor (C1 ), the drain electrode is connected to the other electrode of the third transistor (M22), the gate electrode is connected to the third control terminal (SA), and the source electrode is that of the third transistor (M22). a fourth transistor (M23) connected in common, with a drain electrode connected to the first voltage source (VDD) and a gate electrode connected to the third voltage source (VR1);
, current source means (I1) connected between the mutually connected source electrodes of the third and fourth transistors and the second voltage source (ground), and the capacitor (C1).
a fifth transistor (M21) whose drain electrode is connected to a connection point between the drain electrode of the third transistor (M22) and the third control terminal (SA), and whose gate electrode is connected to the third control terminal (SA); (C1) and the third transistor (M22)
and the connection point between the drain electrode and the first control terminal (T
1) or the second control terminal (T2), or the voltage between the capacitor (C1) and the first voltage source (VDD), or the voltage connected to the second control terminal (T2), or both control terminals; The first voltage source (VDD)
and the first control terminal (T1), or between the second voltage source (earth) and the second control terminal (T2), or both. ,
A semiconductor memory device comprising: M11). 6. The semiconductor memory device according to claim 5, wherein a first switch circuit (M
24), and a second switch connected between the other side of the first switch circuit (M24) and the first voltage source (VDD).
a second switch circuit (M25) connected between the connection point of the first switch circuit (M24) and the second switch circuit (M25) and the second voltage source (ground).
A semiconductor memory device comprising current source means (I2). 7. In the semiconductor memory device according to claim 5, the fourth
A drain electrode is connected to a connection point between the voltage source (VR2), the capacitor (C1), and the drain electrode of the third transistor (M22), and a gate electrode is connected to the fourth voltage source (VR2). The sixth transistor (M24)
, the source electrode is commonly connected to that of the sixth transistor (M24), the drain electrode is connected to the first voltage source (VDD), and the gate electrode is connected to the drain electrode of the sixth transistor (M24). a seventh transistor (M25) connected to the source electrodes of the sixth and seventh transistors connected in common to the second voltage source (M25);
second current source means (12) connected between
A semiconductor memory device comprising: