JPH02118893A - Logarithmic converting circuit - Google Patents

Logarithmic converting circuit

Info

Publication number
JPH02118893A
JPH02118893A JP63273550A JP27355088A JPH02118893A JP H02118893 A JPH02118893 A JP H02118893A JP 63273550 A JP63273550 A JP 63273550A JP 27355088 A JP27355088 A JP 27355088A JP H02118893 A JPH02118893 A JP H02118893A
Authority
JP
Japan
Prior art keywords
transistors
difference
trs
diodes
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63273550A
Other languages
Japanese (ja)
Other versions
JP2734564B2 (en
Inventor
Toshiro Nozoe
野添 敏郎
Koji Takemoto
竹本 宏二
Shigeru Kawakami
茂 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63273550A priority Critical patent/JP2734564B2/en
Publication of JPH02118893A publication Critical patent/JPH02118893A/en
Application granted granted Critical
Publication of JP2734564B2 publication Critical patent/JP2734564B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To obtain the title circuit, which is composed of the minimum number of elements and pins and executes a stable operation, by logarithmically changing the difference between an added result obtained by adding the potential difference between the respective Bs (base) and Es (emitter) of two transistors (Trs) and potential difference between the respective anodes and cathodes of two diodes for the difference of the voltages respectively applied to the respective Bs of other two Trs. CONSTITUTION:Voltage VB of a constant voltage source 18 is applied to the respective bases of transistors (Trs) 1 and 2, and the respective anodes of diodes 3 and 4 are connected to the respective emitters of the Trs 1 and 2. Further, the collectors of Trs 5 and 6 are connected to the respective cathodes of the diodes 3 and 4, and different voltages are applied to the respective bases of the Trs 5 and 6. The difference between an added result obtained by adding the potential difference between the respective base and the emitter of the Tr 1 and 2, and the potential difference between the anode and the cathode of the diode 3 and 4 logarithmically changes for the difference of the voltage applied to the respective base of the Tr 5 and 6. Namely, when voltage Vin is impressed to an input terminal 17 of this circuit, the variation is converted into a logarithm and appears at output voltage terminals 19 and 20.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテレビ、VTR、オーディオ機器、衛星放送受
信機等の電子通信機器の電気回路に使用することのでき
る対数変換回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logarithmic conversion circuit that can be used in electrical circuits of electronic communication equipment such as televisions, VTRs, audio equipment, and satellite broadcast receivers.

従来の技術 従来より、トランジスタを用いた対数変換回路トシてト
ランジスタのベース・エミッタ間電圧vBEとエミッタ
電流IE  との間の関係式、k:ボルツマン定数、 
  τ−絶絶対温度9電 を用いた回路が使われておジ、その実用回路としてはオ
ペアンプを用いた回路がよく使用されている。従来15
IIj金第2図に示す。第2図はオペアンプを用いた代
表的な対数変換回路の実用例全表わす。
Conventional technology Conventionally, in a logarithmic conversion circuit using a transistor, a relational expression between the base-emitter voltage vBE of the transistor and the emitter current IE, k: Boltzmann constant,
A circuit using τ - Absolute Temperature 9V is used, and a circuit using an operational amplifier is often used as a practical circuit. Conventional 15
IIj gold shown in Figure 2. FIG. 2 shows all practical examples of a typical logarithmic conversion circuit using an operational amplifier.

21 、22はオペアンプ、23 、24は対数特性を
得るためのトランジスタで、特性のそろった吻が使用さ
れる。25,26,2ア,28は出力電圧の特注を決定
する抵抗、29は入力端子、3゜は出力端子、31は出
力電圧を決定するための基準電圧源、32.33は発振
防止のためのコンデサである。
21 and 22 are operational amplifiers, 23 and 24 are transistors for obtaining logarithmic characteristics, and transistors with uniform characteristics are used. 25, 26, 2a, 28 are resistors that determine the customization of the output voltage, 29 is an input terminal, 3° is an output terminal, 31 is a reference voltage source for determining the output voltage, 32 and 33 are for preventing oscillation. It is a condesa.

発明が解決しようとする課題 従来例では出力電圧voutは次式で表わされる。Problems that the invention aims to solve In the conventional example, the output voltage vout is expressed by the following equation.

ここでR1,R2,R5,R6は各々抵抗25,26゜
27.28の抵抗偵、viユは入カフ1NB”、vre
f ”基準電圧である。
Here, R1, R2, R5, and R6 are resistances of 25, 26° and 27.28 degrees, respectively, vi is the input cuff 1NB, and vre is
f” is the reference voltage.

この場合、第2図のトランジスタ23.24の特性の揃
った物を使う必要がある。従来例の回路をIC化する場
合、(1〜 2つのオペアンプの働きをする差動入力の
ハイゲイン(数十dB)  アンプを2つ内蔵するため
素子が多くなる。(2)、負帰還回路のため発振防止の
ための配慮が必要である。
In this case, it is necessary to use transistors 23 and 24 shown in FIG. 2 that have the same characteristics. When converting a conventional circuit into an IC, the number of elements increases because it incorporates two differential input high-gain (several tens of dB) amplifiers that function as one or two operational amplifiers.(2) Therefore, consideration must be given to preventing oscillation.

(1(2)のため発振防止用のコンデンサが必要であり
、内蔵する場合は面積が大きくなりコストアップになり
、外付けにする場合はコンテ゛ンサを付けるため4本の
ピンが必要である等の問題かめる。
(1 (2) requires a capacitor to prevent oscillation, and if it is built-in, the area will increase and the cost will increase; if it is externally mounted, four pins are required to attach the capacitor, etc.) Think about the problem.

本発明は前記問題点に鑑み、対数変換回路をICに内蔵
する場合に、少ない素子数で少ないピン数で、動作の安
定な回路を実現する手段を提供するものである。
In view of the above-mentioned problems, the present invention provides means for realizing a circuit with stable operation using a small number of elements and a small number of pins when a logarithmic conversion circuit is built into an IC.

課題を解決するための手段 前記の課題を解決するため本発明の対数変換回路は、第
1.第2のトランジスタの各々のベースに等しい電圧を
加え、第1第2のトランジスタの各々のエミッタに第1
、第2のダイオードの各々のアノードを接続し、第1.
第2のダイオードの各々のカソードに第3.第4のトラ
ンジスタのコレクタをm Fし、第3.第4のトランジ
スタの各々のベースに異なる電圧を与える事により生じ
る男1 、第2のトランジスタの各々のベース・エミッ
タ間の電位差および第1.第2のダイオードのア゛ノー
ド・カッド間の電位差を加えたものの差が、第3゜第4
のトランジスタの各々のベースに加えた電圧の差に対し
て対数的に変化すること全利用する構成にしている。
Means for Solving the Problems In order to solve the above problems, the logarithmic conversion circuit of the present invention has the following features: Applying equal voltages to the bases of each of the second transistors and applying equal voltages to the emitters of each of the first and second transistors.
, the anodes of each of the second diodes are connected;
The third diodes are connected to the cathodes of each of the second diodes. mF the collector of the fourth transistor; By applying different voltages to the bases of each of the fourth transistors, there is a potential difference between the bases and emitters of each of the first and second transistors and the first and second transistors. The difference between the potential difference between the anode and the quad of the second diode is the difference between the third and fourth diode.
The structure takes full advantage of the fact that the voltage varies logarithmically with respect to the difference in voltage applied to the bases of each transistor.

作   用 本発明は上記の構成により、(1)少ない素子で溝成し
占有面積を小さくできる。(2)  負帰還回路を用い
ないので安定性が良く、発振防止のためのコンデンサが
必要でない。等のメリットがあり、特にIC化する場合
に有効である。
Effects The present invention has the above-described configuration, (1) it is possible to reduce the area occupied by the grooves with a small number of elements. (2) Stability is good because no negative feedback circuit is used, and no capacitor is required to prevent oscillation. It has the following advantages, and is particularly effective when integrated into an IC.

実施例 以下本究明の一天、側例の対@双換回路について図面全
参照しなから1況明する。
Embodiments In the following, we will clarify the details of the pair-to-converter circuit of this research without referring to all the drawings.

第1図は本究明の実施例に於ける対数変換回路の回路図
を示す。第1図に於いて1,2はトランジスタ3,4は
ダイオード6.6はトランジスタ、7.8はダイオード
、9R1,10R2,11R3,12R4。
FIG. 1 shows a circuit diagram of a logarithmic conversion circuit in an embodiment of the present investigation. In FIG. 1, 1 and 2 are transistors 3, 4 are diodes, 6.6 are transistors, 7.8 are diodes, and 9R1, 10R2, 11R3, 12R4.

13Rs T 14Re 、 1tsR−r  は抵抗
、16は基準電圧源、17は入力電圧端子vIN−18
はトランジスタ1゜2のベースの′直圧源、19 、2
0は出力直圧端子■。、v2を表わす。
13Rs T 14Re , 1tsR-r are resistors, 16 is a reference voltage source, 17 is an input voltage terminal vIN-18
is the direct voltage source at the base of transistor 1゜2, 19,2
0 is the output direct voltage terminal ■. , v2.

トランジスタ1,2のベースには?l[j圧源18より
電圧VBが供給される。トランジスタ1,2のエミッタ
は各々ダイオード3.4を通してトランジスタ6.6の
各々のコレクタに繋がる。トランジスタ5のベースは抵
抗9を通して基準電圧源16(電位vref)に繋がり
、トランジスタ6のベースは抵抗10を通して基準電圧
源16(?[位”ref)に繋がっている。トランジス
タ6、ダイオード7、抵抗11.12はカレントミラー
を構成し、トランジスタ6、ダイオード8、抵抗13.
14は力1/71−ミラー全購成する。トランジスタ6
のベースは抵抗16金1ffi して入力電圧端子17
に繋がる。
What about the bases of transistors 1 and 2? Voltage VB is supplied from l[j pressure source 18. The emitters of transistors 1, 2 are each connected through a diode 3.4 to the respective collector of a transistor 6.6. The base of the transistor 5 is connected to a reference voltage source 16 (potential vref) through a resistor 9, and the base of the transistor 6 is connected to a reference voltage source 16 (?[ref) through a resistor 10.Transistor 6, diode 7, resistor 11.12 constitutes a current mirror, which includes a transistor 6, a diode 8, a resistor 13.
14 buys all power 1/71-mirror. transistor 6
The base of the resistor is 16 gold 1ffi and the input voltage terminal 17
It leads to

トランジスタ6.6およびダイオード7.8は同一の特
性とし、R1:R2,R3:=R4,R6=R6とする
The transistor 6.6 and the diode 7.8 have the same characteristics, R1:R2, R3:=R4, R6=R6.

この時、トランジスタ5.6の直流電流増幅率が充分に
大きいとすると、 (vD1=ダイオード3の両端電圧、vBE3=トラン
ジスタ5のベース・エミッタ問直E) (”D2 = タ4 オt’ 4 (7)両端’を圧*
 VBB;4 = ) −y ンシヌタ6のベース・エ
ミッタ間[E )工E3=工1.工E4=工2.R1+
R3=R2+R4,vD1=vD2であるから またトランジスタ1 3.4に関して 工E1=IC3−工E3 IE2=工C4−IE4 でろるから(功より 、6.6、 ダイオード 一方トランジヌタ1,2の特性を同一とし、同時にダイ
オード3,4の特性を同一とすると次の様になる。
At this time, assuming that the DC current amplification factor of transistor 5.6 is sufficiently large, (vD1 = voltage across diode 3, vBE3 = base-emitter voltage of transistor 5) ("D2 = ta 4 ot' 4 (7) Press both ends*
VBB; 4 = ) -y Between the base and emitter of sensor 6 [E) E3 = E1. Engineering E4 = Engineering 2. R1+
Since R3 = R2 + R4, vD1 = vD2, and for transistor 1 3.4, E1 = IC3 - E3 IE2 = C4 - IE4. If the characteristics of the diodes 3 and 4 are made the same, the following will be obtained.

v1=”B−”BEl−vDl(”BEl = ) ラ
フ シヌli 11)ベース・エミッタ間電圧) v2−VB−vBE2−vD2(vBE2=トランジス
タ2のベース・エミッタ間電圧) vBE1=vBE2.vD1=vD2テアルカら、即ち
無信号時には出力電圧端子19.20の電位v1.v2
は等しい。
v1=”B-”BEl-vDl(”BEl=) rough sinuli 11) Base-emitter voltage) v2-VB-vBE2-vD2 (vBE2=base-emitter voltage of transistor 2) vBE1=vBE2.vD1= From vD2, that is, when there is no signal, the potential of the output voltage terminal 19.20 v1.v2
are equal.

次に、この回路の入力電圧端子17に電圧vinを印加
した時を考える。この時のIE4を’pl<とす工s1
:トランジスタ1.2の飽和電流工s2:ダイオード3
.4の飽和電流 ”工E4+Δ■F4 ・・・・・・・(4) ;c o時o IE2 k 1f2・vBx2 ’kV
BEらI vD2 k vD6ev2をv2′とすると v2=VB−vB12−vD6 ・(@ 従ってこの時の出力電圧端子19 差■る一v1 は次のとおり 20の′電位 T v2−V1= よる変化量が対数に変換されて出力電圧端子Vout1
 、Vout2間に現われる。即ち対数変換回路を構成
できる。
Next, consider the case where the voltage vin is applied to the input voltage terminal 17 of this circuit. At this time, IE4 is set to 'pl< and work s1
: Saturation current of transistor 1.2 s2: Diode 3
.. Saturation current of 4 "E4+Δ■F4 ・・・・・・(4) ;co IE2 k 1f2・vBx2 'kV
BE et al. I vD2 k vD6 If ev2 is v2', then v2 = VB - vB12 - vD6 ・(@ Therefore, the output voltage terminal 19 at this time. is converted into logarithm and output voltage terminal Vout1
, Vout2. In other words, a logarithmic conversion circuit can be constructed.

発明の効果 本発明は上記の構成により、■少ない素子で構成し占有
面積金車さくできる。■負帰還回路を用いないので安定
性が良く、発振防止のためのコンデンサが必要ない。等
の効果が得られ、特にIC化する場合に有効である。
Effects of the Invention With the above configuration, the present invention can be constructed with fewer elements and occupy less space. ■Since it does not use a negative feedback circuit, it has good stability and does not require a capacitor to prevent oscillation. These effects are particularly effective when integrated into an IC.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における対数変換回路の回路
図、第2図は従来例における対数変換回路の回路図であ
る。 1.2,5.6・・・・・・トランジスタ、3 、4 
、7゜8・・・・・・ダイオード、9,10,11,1
2,13゜14.16・・・・・・抵抗、18.18・
・・・・・定電圧電源、17・・・・・・入力電圧端子
、19 、20・・・・・・出力電圧端子。 即ちこの回路により入力電圧V、。全印加した事に蔀抹
FIG. 1 is a circuit diagram of a logarithmic conversion circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a logarithmic conversion circuit according to a conventional example. 1.2, 5.6...Transistor, 3, 4
, 7°8...Diode, 9, 10, 11, 1
2,13°14.16...Resistance, 18.18.
... Constant voltage power supply, 17 ... Input voltage terminal, 19, 20 ... Output voltage terminal. That is, the input voltage V, by this circuit. I'm disappointed in the fact that I applied all the power.

Claims (1)

【特許請求の範囲】[Claims] 第1、第2のトランジスタの各々のベースに等しい電圧
を加え、前記第1、第2のトランジスタの各々のエミッ
タに第1、第2のダイオードの各々のアノードを接続し
、第1、第2のダイオードの各々のカソードに第3、第
4のトランジスタの各々のコレクタを接続し、前記第3
、第4のトランジスタの各々のベースに異なる電圧を与
えることにより生じる前記第1、第2のトランジスタの
各々のベース・エミッタ間の電位差および前記第1、第
2のダイオードのアノード・カソード間の電位差を加え
たものの差が前記第3、第4のトランジスタの各々のベ
ースに加えた電圧の差に対して対数的に変化するように
したことを特徴とする対数変換回路。
Applying an equal voltage to the bases of each of the first and second transistors, connecting the anodes of each of the first and second diodes to the emitters of each of the first and second transistors, and The collectors of the third and fourth transistors are connected to the cathodes of the diodes of the third and fourth transistors.
, a potential difference between the base and emitter of each of the first and second transistors and a potential difference between the anode and cathode of the first and second diodes, which are caused by applying different voltages to the bases of each of the fourth transistors. 2. A logarithmic conversion circuit characterized in that the difference between the voltages added to the bases of the third and fourth transistors varies logarithmically with respect to the difference between the voltages applied to the bases of the third and fourth transistors.
JP63273550A 1988-10-28 1988-10-28 Logarithmic conversion circuit Expired - Fee Related JP2734564B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63273550A JP2734564B2 (en) 1988-10-28 1988-10-28 Logarithmic conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63273550A JP2734564B2 (en) 1988-10-28 1988-10-28 Logarithmic conversion circuit

Publications (2)

Publication Number Publication Date
JPH02118893A true JPH02118893A (en) 1990-05-07
JP2734564B2 JP2734564B2 (en) 1998-03-30

Family

ID=17529381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63273550A Expired - Fee Related JP2734564B2 (en) 1988-10-28 1988-10-28 Logarithmic conversion circuit

Country Status (1)

Country Link
JP (1) JP2734564B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006109157A (en) * 2004-10-06 2006-04-20 Asahi Kasei Microsystems Kk Logarithmic amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006109157A (en) * 2004-10-06 2006-04-20 Asahi Kasei Microsystems Kk Logarithmic amplifier

Also Published As

Publication number Publication date
JP2734564B2 (en) 1998-03-30

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