JPH02118882U - - Google Patents

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Publication number
JPH02118882U
JPH02118882U JP2770689U JP2770689U JPH02118882U JP H02118882 U JPH02118882 U JP H02118882U JP 2770689 U JP2770689 U JP 2770689U JP 2770689 U JP2770689 U JP 2770689U JP H02118882 U JPH02118882 U JP H02118882U
Authority
JP
Japan
Prior art keywords
signal
input
seconds
output
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2770689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2770689U priority Critical patent/JPH02118882U/ja
Publication of JPH02118882U publication Critical patent/JPH02118882U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示す図、第2図
は従来のスペクトラム拡散レーダ装置を示す図で
ある。 図において、1は信号発生器、2はτ秒のタイ
ミング発生器、3はコード発生器、4は0゜−1
80゜位相変調器、5は電力増幅器、6は送信用
空中線、7は受信用空中線、8は周波数変換器、
9は中間周波増幅器、10は分周器、11はnビ
ツトシフトレジスタ、12は中間周波信号、13
は復調信号1、14は復調信号2、15は復調信
号n、16は0゜−180゜位相復調器、17は
積分器1、18は積分器2、19は積分器n、2
0は検波信号1、21は検波信号2、22は検波
信号n、23は合成器、24は表示器、25はス
イツチ、26はスイツチ、27は増幅器である。
なお、各図中同一符号は同一または相当部を示す
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional spread spectrum radar device. In the figure, 1 is a signal generator, 2 is a τ second timing generator, 3 is a code generator, and 4 is 0°-1
80° phase modulator, 5 is a power amplifier, 6 is a transmitting antenna, 7 is a receiving antenna, 8 is a frequency converter,
9 is an intermediate frequency amplifier, 10 is a frequency divider, 11 is an n-bit shift register, 12 is an intermediate frequency signal, 13
are demodulated signal 1, 14 is demodulated signal 2, 15 is demodulated signal n, 16 is 0°-180° phase demodulator, 17 is integrator 1, 18 is integrator 2, 19 is integrator n, 2
0 is a detection signal 1, 21 is a detection signal 2, 22 is a detection signal n, 23 is a synthesizer, 24 is a display, 25 is a switch, 26 is a switch, and 27 is an amplifier.
Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] レーダ送信機の搬送波及びレーダ受信機のロー
カル信号を発生する信号発生器と、τ秒及びτ/
n秒(nは自然数)のタイミングを発生するタイ
ミング発生器と、このτ秒のタイミングにより1
ビツトτ秒で一周期nビツトからなる疑似雑音符
号を発生するコード発生器と、このコード発生器
が発生する疑似雑音符号に従つて上記搬送波に0
゜、180゜の位相変調をくわえる0゜−180
゜位相変調器と、この0゜−180゜位相変調器
の出力を所要の電力まで増幅する電力増幅器と、
この電力増幅器の出力である送信信号を空中に放
射する送信用空中線と、目標物からの反射波を受
信信号としてとらえる受信用空中線と、その受信
信号とローカル信号を混合して中間周波信号に変
換する周波数変換器と、その中間周波信号を所要
の電力まで増幅する中間周波増幅器と、上記疑似
雑音符号と上記タイミング発生器のτ秒のタイミ
ング信号を入力しτ秒ごとに疑似雑音符号が1ビ
ツトづつシフトしかつ各ビツトから信号を取り出
し得るnビツトシフトレジスタと、上記τ/n秒
のタイミング信号と上記nビツトシフトレジスタ
のn個の信号が入力されこのτ/n秒のタイミン
グ信号1ビツトが入力される毎にnビツトシフト
レジスタのn個の信号のうち隣接する信号を1つ
づつ順次選択するスイツチと、このスイツチの出
力により0゜、180゜の位相復調をおこなう0
゜−180゜復調器と、この0゜−180゜復調
器の出力と上記τ/n秒のタイミング信号が入力
され1個の入力端子とn個の出力端子を持ち、上
記τ/n秒のタイミング信号1ビツトが入力され
る毎にn個の出力端子のうち隣接する端子を1つ
づつ順次選択して入力端子と接続するスイツチと
、これらの出力端子それぞれに接続されたn個の
積分器と、これらn個の積分器の出力を入力し、
1つの信号に合成する合成器と、この合成器の出
力が入力される増幅器と、この増幅器の出力が入
力される表示器から構成されたことを特徴とする
レーダ装置。
a signal generator for generating the carrier wave of the radar transmitter and the local signal of the radar receiver;
A timing generator that generates a timing of n seconds (n is a natural number) and a timing of τ seconds
A code generator that generates a pseudo-noise code consisting of n bits per period in bits τ seconds, and a
0°-180 with 180° phase modulation
a phase modulator; a power amplifier that amplifies the output of the 0°-180° phase modulator to a required power;
A transmitting antenna emits the transmitted signal output from this power amplifier into the air, a receiving antenna captures the reflected wave from the target as a received signal, and the received signal and local signal are mixed and converted into an intermediate frequency signal. A frequency converter that generates a signal, an intermediate frequency amplifier that amplifies the intermediate frequency signal to the required power, the pseudo noise code and the timing signal of τ seconds from the timing generator are input, and the pseudo noise code is generated by 1 bit every τ seconds. An n-bit shift register that can shift and take out signals from each bit, the above-mentioned τ/n seconds timing signal, and n signals of the above-mentioned n-bit shift register are input, and one bit of this τ/n seconds timing signal is inputted. A switch that sequentially selects one adjacent signal among the n signals of the n-bit shift register each time it is input, and a switch that performs 0° and 180° phase demodulation using the output of this switch.
It has one input terminal and n output terminals into which the output of the 0°-180° demodulator and the above τ/n seconds timing signal are input, and the above τ/n seconds timing signal is inputted to the 0°-180° demodulator. A switch that sequentially selects adjacent terminals from n output terminals one by one and connects them to the input terminals each time one bit of a timing signal is input, and n integrators connected to each of these output terminals. and input the outputs of these n integrators,
A radar device comprising: a combiner for combining signals into one signal; an amplifier to which the output of the combiner is input; and a display to which the output of the amplifier is input.
JP2770689U 1989-03-10 1989-03-10 Pending JPH02118882U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2770689U JPH02118882U (en) 1989-03-10 1989-03-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2770689U JPH02118882U (en) 1989-03-10 1989-03-10

Publications (1)

Publication Number Publication Date
JPH02118882U true JPH02118882U (en) 1990-09-25

Family

ID=31250431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2770689U Pending JPH02118882U (en) 1989-03-10 1989-03-10

Country Status (1)

Country Link
JP (1) JPH02118882U (en)

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