JPH02118758A - Data transfer system - Google Patents

Abstract

PURPOSE:To decrease the overhead of a host device by having a shift register and a counter register and successively executing the writing of data given to a bit serial succeeding to the command into the memory without passing through a host device with the host device. CONSTITUTION:An information processor 2 provides a register 7 which is a shift register to fetch and hold the coming data and command in accordance with a clock, a register 9 which is a counter register to count the number of the times of the reception of a strobe signal initialized by a sequence activating signal and to come, and a control circuit 10 which is a control means to give a command to write the data to the area to add the continuous address of a memory 6 to storing means 3 to 5 when initialization is executed by the sequence activating signal, a counter register 9 counts the special value and a shift register 7 counts a value specified beforehand. Consequently, when the host device continues to send the data in succession to the command, the writing control to the memory is successively executed. Thus, the overhead of the host device is significantly decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system for transferring data to be written from a host device to an information processing device having a storage means capable of writing to an address designated by a write address.

〔overview〕

The present invention is a system for loading a program from a host device to an information processing device, in which the host device writes data given serially in bits following a command into memory and executes the data sequentially without intervention from the host device. This makes it possible to reduce overhead.

[Conventional technology]

A microprogram is often loaded from a service processor or a diagnostic control processor, which is a host device, into a control storage unit comprised of a RAM included in an information processing device. In addition, a service processor or a diagnostic control processor often writes initial data to an information processing device having a scratchpad memory as a work area when executing a microprogram before starting the device.

Conventionally, such data transfer has been performed by a host device simultaneously giving a data ring and a command to the information processing device, and by sequentially controlling write operations to a RAM such as a control storage unit or a scratch pad memory.

FIG. 5 is a block diagram showing a conventional example of microprogram loading. The diagnostic control processor 1 has a signal line 50
1, a command through the signal line 50.3, and a command data strobe through the signal line 502 to the information processing device 2.

The command and data strobe are synchronized with the clock of the information processing device 2 by the synchronization circuit 53, and the synchronization signal is sent to the register (DTB) 51 and the control circuit 52 via the signal line 505. When this synchronization signal arrives, the register (DTB) 51 takes in the data on the signal line 501. Control circuit 52 sends control information to signal lines 101 to 104 in response to commands sent via signal line 503 and synchronization signals sent via signal line 505. Signal lines 501 and 503 are each capable of 8-bit parallel transfer, and register (DTB) 51 is an 8-bit register. Control storage unit 6 is 16 bits
It has a 256-word configuration, and writing is performed in units of 16 bits. Therefore, the contents of the register (DTB) 51 are each 8-bit register (CBI).
I) 3 and register (CBL) 4, and then written to control memory B6. Register (CA) 5 is a register indicating the write address at this time, and is cleared to "0" or incremented by "+1" in response to a signal sent via signal line 104. Register (CBH) 3 and register (CBH)
L) Write instructions to 4 are sent to signal lines 101 and 10.
By the signal sent via 2. Further, a write instruction to the control storage section 6 is based on a signal sent via the signal line 103.

Table 1 Table 1 shows operations corresponding to command codes sent from the diagnostic control processor 1. Writing data to the control storage section 6 is performed in the following procedure. Command ″20
++ J is sent, the register (CA) 5 is cleared to "0", and at this time, the word "0" of the control storage section 6 is written as data.
” (step ■)
. Send command '101 J and register (DTB)
The upper 8 bits of data in 51 are transferred to the register (Ca
ll) Transfer to 3. As data at this time, data for the lower 8 bits of the control storage section 6 is sent out (step 2). Send command “1111 J and register (
The lower 8 bits of data in DTB) 51 are transferred to register (CBL) 4 (step ■). Register (CBH) 3 is sent to the address of control storage unit 6 indicated by register (CA) 5, which is sent to command “12II”.
and write data in register (CBL) 4 (
Step ■). Send the command “21N” and register (
CA) The address of 5 is incremented by "+1", and at this time, data for the upper 8 bits of the control storage section 6 is sent out as data (step 2). Return to step ■ (
Step ■).

In this way, data is sequentially written into the control storage section 6 by repeating Steps (1) and (2).

[Problem that the invention seeks to solve]

In such a conventional method, the ζ host device must control the RAM writing operation one by one every time data is sent to the information processing device, so there is a drawback that the overhead of the host device becomes large. Normally, a host device such as a diagnostic control device performs multiple processes at the same time, and this increase in overhead has the drawback of not only increasing the data transfer rate but also deteriorating the response of the host device.

Furthermore, in the conventional example, there are many signal lines between the host device and the information processing device. As devices become more and more integrated into LSI devices, the number of interface signals becomes an important factor in determining the physical size of the device. There is a drawback that the amount of wear cannot be reduced.

The present invention aims to eliminate such drawbacks and to provide a data transfer method that can reduce the overhead of a host device.

[Means for solving problems]

The present invention provides an information processing apparatus having a host device that sends data, commands, and strobe signals, and a storage means that stores in a memory data that arrives at a clock corresponding to the strobe signal that arrives based on the command that arrives from the host device. In a data transfer method comprising: a first signal line for serially transmitting data and commands one bit at a time, a second signal line for transmitting a strobe signal, and a sequence start signal from the host device to the information processing device. The information processing device includes a third signal line, and the information processing device includes a shift register that captures and holds incoming data and commands in accordance with the clock, and a counter that is initialized by the sequence activation signal and counts the number of times the incoming strobe signal is received. a register, and a command to write data into consecutively addressed areas of the memory when the counter register counts a specific value and the shift register counts a predetermined value, which is initialized by the sequence start signal. and a control means for applying the information to the storage means.

[Effect]

The data and commands to be transmitted are captured and held in the shift register according to the strobe signal.

On the other hand, a counter register counts the number of times the strobe signal is received. the counter register has a specific value, and
When the value of the shift register reaches a predetermined value, the data sent is sequentially written into consecutive addresses of the storage means.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of this embodiment. In FIG. 1, the same means as in FIG. 5 are given the same numbers.

As shown in FIG. 1, this embodiment includes a diagnostic control processor 1, which is a host device that sends data, commands, and strobe signals, and a clock that corresponds to the strobe signal that arrives based on commands that come from this host device. Register (CBH) 3, a register (CBH) which is a storage means for storing incoming data in the control storage unit 6 which is a memory;
BL) 4 and a register (CA) 5, and a signal line 109 for serially transmitting data and commands bit by bit, a signal line 108 for transmitting a strobe signal, and a sequence start signal to the upper level device. The information processing device 2 includes a register (DT) 7, which is a shift register, which takes in and holds incoming data and commands in accordance with the above-mentioned clock, and a signal line 107 that transmits data and commands from the above to the information processing device 2. A register (CNT) that is a counter register that is initialized and counts the number of times an incoming strobe signal is received.
9, and a command to write data into areas of the memory with consecutive addresses when the counter register counts a specific value and the shift register counts a predetermined value, which is initialized by the sequence activation signal. and a control circuit 10 which is a control means for providing the storage means with the following information.

Next, the operation of this embodiment will be explained.

Signal line 1 from diagnostic control processor 1 to information processing device 2
Data and commands are sent via signal line 1
A strobe signal is sent through line 08, and a sequence start signal is sent through signal line 107. These are all one signal line, and data and commands are transferred serially. The synchronization circuit 8 receives the strobe signal,
A synchronization signal synchronized with the clock of the information processing device 2 is sent to the signal lines 111 and 112. Register (DT)
7 is an 8-bit shift register, and a signal line 111
Each time a synchronization signal is sent via the signal line 109
The above data or command is taken into the least significant bit bit by bit, and at the same time, the already held value is shifted bit by bit from the lower to the upper bit. Register (CNT
) 9 is a 5-pit register having counting means, and when a sequence start signal is sent via the signal line 107, it becomes ro O000J, and thereafter the signal line 112
Each time a synchronization signal is sent via the , it counts up by ``+1''.

However, when the register value becomes ``rllooo'', it will roll instead of ``rlloo'' in response to the reception of the synchronization signal.
ool”. The value of register (CNT) 9 is sent to control circuit 10 together with the value of register (DT) 7. The control circuit 10 connects a control storage unit 6, a register (CBII) 3, and a register (
CBL) 4 and register (CA) 5. The functions of the signals sent through each signal line are the same as in the conventional example.

FIG. 2 is a block diagram showing the configuration of the control circuit 10. As shown in FIG. The register (CMD) 11 is cleared to "0.On" when a sequence activation signal is sent from the diagnostic control processor l via the signal line 107, and is cleared to "0.On" when a signal is sent from the control circuit 13 via the signal line 115. The value of register (DT) 7 sent via signal line 110 is taken in. The sequencer 12 uses the synchronization signal sent via the signal line 112 as a trigger to perform φ0, φ1, and φ2 in FIG.
Generate a pulse shown by . Here, the timing of pulse φ0 is the same timing as the signal sent via the signal line 112, and the timings when φ0, φ1, and φ2 are “1” are called phases 0.1 and 2, respectively. Make it.

Table 2 shows registers (CMDH! and registers (CNT)
The operation instructions sent by the control circuit 13 via the signal lines 101, 102, 103, 104 and 115 are shown in correspondence with the value of 9 and the phase number.

Table 2 and FIG. 3 are time charts of values until three strobe signals are output after the sequence start signal is sent. register(
DT) shows a situation in which the contents of the signal command and data on the signal line 109 are stored in order from the lower bit of 7.

Figure 4 shows command “10H” and data “12”, “
34” is sent, and data “1” is sent to the control storage address “0”.
This is a time chart when 234J is written.

As shown in Table 2, FIGS. 3 and 4, the control storage unit 6
Writing data to is performed in the following steps. The diagnostic control processor 1 sends a sequence start signal and registers (
CMD) 11 and register (CNT) 9 are cleared to "0" (step ■). The diagnostic control processor 1 serially transfers the command "l0HJ" starting from the upper bit, and each time a strobe signal is output, the command is transferred to the register (D
T) stored in 7 and register (CNT)
9 is incremented by "+1" (step ■). Register (CNT) 9 becomes “08” and phase 1
When this happens, the command "10HJ", which has 8 pits in register (DT) 7, is transferred to register (CMD) 11 (step ■).

Furthermore, when phase 0 is reached, register (CA) 5 is set to "0" in response to the signal sent via signal line 104.
Cleared (step ■). Following the command, the diagnostic control processor 1 serially transfers data "12" starting from the upper bit, and each time a strobe signal is output, the data is stored in register (DT) 7, and register (CNT) 9 is incremented by "+1". (Step ■). When register (CNT) 9 becomes "10" and becomes phase 0, the data "12HJ" in register (DT) 7 is transferred to register (CBH) 3 in response to a signal sent through signal line 101. (Step ■).Furthermore, the diagnostic control processor 1 transfers data "34" (Step Cv). Register (C
When NT) 9 becomes "18H" and phase 1 is reached, the data "34H" that has been set in register (DT) 7 is transferred to register (
CBL) Transfer to Step 4). Furthermore, in phase 2, a write signal is sent to the control storage unit 6, and thereby the data held in the register (CBH) 3 and the register (CBH) 4 is written to the address indicated by the register (CA) 5 (step ■).Furthermore, when phase 0 is reached, register (CA) 5
The value of is incremented by "+1". At this time, the value of register (CNT) 9 changes from "18M" to "09vI".
” (step ■). Continuing, step■
The same operations as steps 1 to 0 are repeated, and data is sequentially written into the words of the control storage unit 6.

〔Effect of the invention〕

As explained above, as the host device continues to send data in response to commands, writing control to the RAM is performed sequentially, so the overhead of the host device is significantly reduced compared to the conventional technology, and processing speed is improved. This has the effect of improving response. Also,
Since the number of interface signals between the host device and the information processing device is small, the amount of hardware can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the control circuit shown in FIG. 1. 3 and 4 are time charts showing the operation of the embodiment of the present invention. FIG. 5 is a block configuration diagram showing the configuration of a conventional example. 1... Diagnostic control processor, 2... Information processing device,
3-5.7.9.11.51...Register, 6...
Control memory, 8.53...Synchronization circuit, 10.13.5
2...Control circuit, 12...Sequencer.

Claims (1)

[Scope of Claims] 1. A host device that sends data, commands, and strobe signals, and a writing device that stores in memory data that arrives at a clock corresponding to the strobe signal that arrives based on the command that comes from the host device. In a data transfer system having an information processing device having an information processing device, a first signal line for serially transmitting data and commands one bit at a time, a second signal line for transmitting a strobe signal, and a sequence start signal are transmitted from the host device to the above-mentioned information processing device. The information processing device includes a shift register that captures and holds incoming data and commands in accordance with the clock, and a shift register that receives incoming strobe signals initialized by the sequence start signal. A counter register that counts the number of times, and when the counter register is initialized by the sequence start signal and counts a specific value, and the shift register counts a predetermined value, the data is assigned to consecutive addresses in the memory. and control means for giving a command to the writing means to write into the area.