JPH02117164A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH02117164A
JPH02117164A JP63270361A JP27036188A JPH02117164A JP H02117164 A JPH02117164 A JP H02117164A JP 63270361 A JP63270361 A JP 63270361A JP 27036188 A JP27036188 A JP 27036188A JP H02117164 A JPH02117164 A JP H02117164A
Authority
JP
Japan
Prior art keywords
chip component
paste
lead frame
recessed part
bottom face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63270361A
Other languages
Japanese (ja)
Inventor
Yoshiharu Kato
加藤　義治
Kohei Kurachi
耕平 倉地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin Corp
Original Assignee
Aisin Seiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin Seiki Co Ltd filed Critical Aisin Seiki Co Ltd
Priority to JP63270361A priority Critical patent/JPH02117164A/en
Publication of JPH02117164A publication Critical patent/JPH02117164A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To perform correctly positioning of chip component parts and make a paste exist between the chip component and a die pad part spread over surely the bottom face of the chip component by causing the bottom face of a lead frame to be larger than that of the chip component and providing a recessed part which prevents the chip component on a loading plane from moving when the chip component is loaded. CONSTITUTION:The bottom face of a lead frame 2 gets larger than that of chip component and a recessed part 3 is provided to prevent the chip component on a loading plane from moving when the chip component is loaded. Consequently, when the chip component is loaded, a paste is held in the recessed part and it does not overflow from the recessed part. As the chip component is held in the recessed part, no slippage of positions takes place. Further, the recessed part is equipped with grooved parts. There are two pieces of the grooved parts and they are intersected crosswise each other. Then the paste spreads over the whole bottom face of the chip component. Moreover, respective groove parts have further deep grooves 5 at their pointed ends. Since the paste gathers well in these deep grooves, overflow of the paste from the recessed part is suppressed.

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、印刷配線基板に搭載する電子部品のの部品で
あり、チップ部品を搭載し、その後部分的に切断されて
電子部品の配線および印刷配線基板への取りつけ用の端
子を構成するリードフレームに関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic component mounted on a printed wiring board, in which a chip component is mounted and then partially cut. The present invention relates to a lead frame that constitutes wiring for electronic components and terminals for attachment to a printed wiring board.

（従来の技術） 従来のリードフレームは、特開昭５７−１２８９４９号
公報に開示されるように、フラットな平板をプレスによ
り打ち抜いて形成し、その上に半導体等のチップ部品を
搭載していた（第５図参照）。この搭載の際、チップ部
品の搭載部（グイバンド部）にペーストを塗布し、ダイ
パッド部とチップ部品の底面との電気的結合を行ってい
る。その後、チップ部品の端子とリードフレームとの間
を配線するためにワイヤーボンディングを行っていた。(Prior art) As disclosed in Japanese Unexamined Patent Publication No. 57-128949, conventional lead frames are formed by punching out a flat plate using a press, and chip components such as semiconductors are mounted on the lead frame. (See Figure 5). During this mounting, paste is applied to the mounting part (guidance band part) of the chip component to electrically connect the die pad part and the bottom surface of the chip part. After that, wire bonding was performed to connect the terminals of the chip components and the lead frame.

（発明が解決しようとする課題） 従来の技術では、ダイパッド部がフラットであるため、
チップ部品の位置決めが困難であった。(Problem to be solved by the invention) In the conventional technology, since the die pad part is flat,
It was difficult to position the chip components.

このため、第６図に示すように、ペーストがチップ部品
６の底面全体に広がらず、信頼性に問題が起こる可能性
があった。また、チップ部品がずれてしまった場合、ワ
イヤーボンディングにおいてチップ部品の端子とリード
フレームとの間の距離にばらつきを生ずるために、ワイ
ヤー７が長くなりすぎて、ワイヤーが倒れる等の問題を
生ずる可能性があった。For this reason, as shown in FIG. 6, the paste does not spread over the entire bottom surface of the chip component 6, which may cause problems in reliability. Furthermore, if the chip component is misaligned, the distance between the terminal of the chip component and the lead frame will vary during wire bonding, which may cause problems such as the wire 7 becoming too long and falling over. There was sex.

そこで、本発明においては、チップ部品の位置決めを正
確に行うことを、その課題とする。また、チップ部品と
ダイバット部の間のペーストを確実にチップ部品の底面
に行き渡らせることを、その課題とする。Therefore, an object of the present invention is to accurately position the chip components. Another object of the present invention is to ensure that the paste between the chip component and the die butt part is spread over the bottom surface of the chip component.

〔発明の構成〕[Structure of the invention]

（課題を解決するための手段） 前記課題を解決するために本発明において用いた技術的
手段は、チップ部品を搭載する搭載面を有するリードフ
レームにおいて、その底面が前記チップ部品の底面より
も大きく、チップ部品の搭載時に前記搭載面上のチップ
部品の移動を防止する凹部を備えたことである。また、
前記凹部に、更に溝部を設けたことである。更に、前記
溝部を２本とし、また、２本の溝部は十字状に交差させ
たことである。そして、溝部の先端に更に深い溝を設け
たことである。(Means for Solving the Problem) The technical means used in the present invention to solve the above problem is to provide a lead frame having a mounting surface on which a chip component is mounted, the bottom surface of which is larger than the bottom surface of the chip component. , a concave portion is provided to prevent movement of the chip component on the mounting surface when the chip component is mounted. Also,
The recess is further provided with a groove. Furthermore, there are two grooves, and the two grooves intersect in a cross shape. Another feature is that a deeper groove is provided at the tip of the groove.

（作用） 上記の技術的手段によれば、チップ部品はその搭載時に
リードフレームの凹部に収まるので、位置ずれが起こら
ない。また、ペーストは凹部の中に収まるのでチップ部
品の搭載時にチップ部品の底面全体に行き渡る。また、
凹部に溝部、特に十字状の溝部を設ければ、ペーストの
まわり込みが起こりやすい。更に、溝部の先端に更に深
い溝を設ければ、ペーストはこの深い溝に溜まるため、
凹部からのペーストのはみ出しが防止できる。(Function) According to the above technical means, the chip component fits into the recess of the lead frame when it is mounted, so that positional displacement does not occur. In addition, since the paste fits in the recess, it spreads over the entire bottom surface of the chip component when the chip component is mounted. Also,
If a groove, especially a cross-shaped groove, is provided in the recess, the paste tends to wrap around the groove. Furthermore, if a deeper groove is provided at the tip of the groove, the paste will accumulate in this deeper groove.
Paste can be prevented from spilling out from the recesses.

（実施例） 以下、本発明の一実施例を図面を参照して説明する。(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第１−ａ図および第１−ｂ図を参照すると、リードフレ
ームのダイバット部２にはチップ部品よりひとまわり大
きい凹部３がプレス加工時に同時に設けられる。Referring to FIGS. 1-a and 1-b, a recess 3 that is slightly larger than the chip component is simultaneously provided in the die butt portion 2 of the lead frame during press working.

また、第’ｌ−ａ図および第２−ｂ図を参照すると、リ
ードフレームのダイバット部２にはチップ部品よりひと
まわり大きい凹部３が設けられ、更に、十字溝４が設け
られている。Further, referring to Figures 1-a and 2-b, the die butt portion 2 of the lead frame is provided with a recess 3 that is slightly larger than the chip component, and is further provided with a cross groove 4.

第３−ａ図および第３−ｂ図を参照すると、第２図の形
状に、更に、十字溝４の先端に深溝５が設けられている
。Referring to FIGS. 3-a and 3-b, a deep groove 5 is further provided at the tip of the cross groove 4 in the shape shown in FIG.

これらのリードフレームにチップ部品を搭載するとき、
第４図に示すように、ペースト８は凹部３の中に収まり
、はみ出さない。また、チップ部品６は凹部３に収まる
ので、位置ずれを起こさない。したがって、ワイヤーボ
ンディングされたワイヤー７の長さは一定となる。When mounting chip components on these lead frames,
As shown in FIG. 4, the paste 8 fits into the recess 3 and does not protrude. Moreover, since the chip component 6 is accommodated in the recess 3, no displacement occurs. Therefore, the length of the wire 7 wire-bonded is constant.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、リードフレーム
（２）の底面がチップ部品の底面よりも大きく、チップ
部品の搭載時に前記搭載面上のチップ部品の移動を防止
する凹部（３）を備えている。したがって、チップ部品
を搭載するとき、ペーストは凹部の中に収まり、はみ出
さない。また、チップ部品は凹部に収まるので、位置ず
れを起こさない。As explained above, according to the present invention, the bottom surface of the lead frame (2) is larger than the bottom surface of the chip component, and the recess (3) is provided to prevent the chip component from moving on the mounting surface when the chip component is mounted. We are prepared. Therefore, when mounting the chip component, the paste fits into the recess and does not protrude. Furthermore, since the chip components fit into the recesses, they do not shift in position.

また、凹部（３）には更に溝部（４）を有している。ま
た、溝部（４）は２本であり、この２本の溝部は十字状
に交差している。したがって、ペーストはチップ部品の
底部全体に行き渡るようになる。Further, the recess (3) further has a groove (4). Further, there are two grooves (4), and these two grooves intersect in a cross shape. The paste will therefore be distributed over the entire bottom of the chip component.

そして、溝部（４）の先端には更に深い溝（５）を有し
ている。したがって、ペーストはこの深い溝によく溜ま
るようになるので、ペーストの四部からのはみ出しが抑
えられる。A deeper groove (5) is provided at the tip of the groove (4). Therefore, the paste is well collected in these deep grooves, so that the paste is prevented from spilling out from the four parts.

このように、チップ部品の位置のばらつきが抑えられる
ので、ワイヤーボンディングの自動化ができ、コスト低
減する。また、ワイヤーの長さが一定にできるので、ワ
イヤーの高さを低くしてワイヤーの材料低減ができ、ワ
イヤーの倒れも防止できる。更に、ペーストのはみ出し
がなく、またチップ部品の底部全体に行き渡るので、信
頼性が向上する。また、放熱性が良くなり、チップ部品
の温度変化による特性変化を最小にできる。In this way, variations in the positions of chip components are suppressed, making it possible to automate wire bonding and reduce costs. Furthermore, since the length of the wire can be made constant, the height of the wire can be lowered to reduce the amount of material used for the wire, and it is also possible to prevent the wire from collapsing. Furthermore, reliability is improved because the paste does not run out and is spread over the entire bottom of the chip component. Furthermore, heat dissipation is improved, and changes in characteristics due to temperature changes in chip components can be minimized.

【図面の簡単な説明】[Brief explanation of drawings]

第１−ａ図は、本発明の第１の実施例のリードフレーム
の正面図である。第１−ｂ図は第１−ａ図のリードフレ
ームのＡ−Ａ断面を示す断面図である。第２−ａ図は、
本発明の第２の実施例のリードフレームの正面図である
。第２−ｂ図は第２−ａ図のリードフレームのＢ−Ｂ断
面を示す断面図である。第３−ａ図は、本発明の第３の
実施例のリードフレームの正面図である。第３−ｂ図は
第３−ａ図のリードフレームのＣ−Ｃ断面を示す断面図
である。第４図は、本発明の実施例のリードフレーム上
にチップ部品を搭載した際の説明図である。第５図は、
従来のリードフレームの正面図である。第６図は、従来
のリードフレーム上にチップ部品を搭載した際の説明図
である。 ２・・・グイバット部、３・・・凹部、４・・・十字溝
、５・・・深溝、６・・・チップ部品、７・・・ワイヤ
ー　８・・・ペースト。 第４Ｅ ｖ＆６図 第１８Ｗ 第３ａ図 （ｃ−ＣｖＴ面躬） １１２ａ図 第５ｇFIG. 1-a is a front view of a lead frame according to a first embodiment of the present invention. FIG. 1-b is a sectional view showing the AA cross section of the lead frame in FIG. 1-a. Figure 2-a is
FIG. 7 is a front view of a lead frame according to a second embodiment of the present invention. FIG. 2-b is a sectional view showing the BB cross section of the lead frame in FIG. 2-a. FIG. 3-a is a front view of a lead frame according to a third embodiment of the present invention. FIG. 3-b is a sectional view showing the CC section of the lead frame in FIG. 3-a. FIG. 4 is an explanatory diagram when chip components are mounted on the lead frame according to the embodiment of the present invention. Figure 5 shows
FIG. 3 is a front view of a conventional lead frame. FIG. 6 is an explanatory diagram when chip components are mounted on a conventional lead frame. 2... Guibat part, 3... Recessed part, 4... Cross groove, 5... Deep groove, 6... Chip component, 7... Wire 8... Paste. Figure 4E v & 6 Figure 18W Figure 3a (c-CvT surface slippage) Figure 112a Figure 5g

Claims (5)

【特許請求の範囲】[Claims] （１）チップ部品を搭載する搭載面を有するリードフレ
ームにおいて、その底面が前記チップ部品の底面よりも
大きく、チップ部品の搭載時に前記搭載面上のチップ部
品の移動を防止する凹部を備えた、リードフレーム。(1) A lead frame having a mounting surface on which a chip component is mounted, the bottom surface of which is larger than the bottom surface of the chip component, and provided with a recess that prevents movement of the chip component on the mounting surface when the chip component is mounted. Lead frame. （２）前記凹部に、更に溝部を有する、請求項（１）記
載のリードフレーム。(2) The lead frame according to claim (1), further comprising a groove in the recess. （３）前記凹部は、前記溝部を２本有する、請求項（２
）記載のリードフレーム。(3) Claim (2) wherein the recess has two grooves.
) Lead frame listed. （４）前記２本の溝部は十字状に交差している、請求項
（３）記載のリードフレーム。(4) The lead frame according to claim (3), wherein the two grooves intersect in a cross shape. （５）前記溝部は、その先端に更に深い溝を有する、請
求項（２）または請求項（４）記載のリードフレーム。(5) The lead frame according to claim (2) or claim (4), wherein the groove portion has a deeper groove at its tip.
JP63270361A 1988-10-26 1988-10-26 Lead frame Pending JPH02117164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63270361A JPH02117164A (en) 1988-10-26 1988-10-26 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63270361A JPH02117164A (en) 1988-10-26 1988-10-26 Lead frame

Publications (1)

Publication Number Publication Date
JPH02117164A true JPH02117164A (en) 1990-05-01

Family

ID=17485199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63270361A Pending JPH02117164A (en) 1988-10-26 1988-10-26 Lead frame

Country Status (1)

Country Link
JP (1) JPH02117164A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708294A (en) * 1995-02-28 1998-01-13 Nec Corporation Lead frame having oblique slits on a die pad
EP2605278A1 (en) * 2011-12-15 2013-06-19 Nxp B.V. Lead Frame with Die Attach Bleeding Control Features

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708294A (en) * 1995-02-28 1998-01-13 Nec Corporation Lead frame having oblique slits on a die pad
EP2605278A1 (en) * 2011-12-15 2013-06-19 Nxp B.V. Lead Frame with Die Attach Bleeding Control Features

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