JPH02116760A - Frequency measuring apparatus - Google Patents

Abstract

PURPOSE:To achieve a measurement of a frequency in a short time even when variations in a receiving level are large by ignoring an input signal for a period during which a reception level of an input signal is lowered within a measuring period to extend a measuring time by the period. CONSTITUTION:An output of a reception level drop detector 3 is down to an L level while a level of an input signal lowers and accordingly, an output Q of an FF circuit 8 attains a level L. Hence, a gate circuit 7b is closed to halt the counting of an input signal while the level lowers. While the level is low, an output -Q of the circuit 8 attains a level H to make invalid the inputting into a frequency divider 6 from a frequency divider 5 with a logic OR gate circuit 15. As a result, only while the output -Q of the circuit 8 is at the level H, a time is extended for opening the circuit 7b with the frequency divider 6. This enables short-time measurement of a frequency even when variations in a reception level are large as caused by a phasing or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device that measures the frequency and frequency of an input signal by counting the number of pulses of the input signal.

[Conventional technology]

In mobile communications, frequency measuring devices are provided to measure base station frequencies with high frequency stability and to subtract the frequency stability of the mobile station from the stability of the base station.

FIG. 5 is a configuration diagram showing an example of a frequency measuring device configured in a conventional mobile station. In the figure, (1) is a received signal input terminal, which is usually the output of the intermediate frequency amplitude limiting amplifier of the mobile station receiver. A signal is input. (2) is a reception level signal input terminal, into which the reception logarithmically amplified detection output normally configured in the mobile station is input. (3) is a reception level drop detector that detects a drop in reception level, (4) is a reference oscillator to create a gate signal for frequency measurement, and (5) is a divider that divides the frequency of the reference oscillator by one division. do. (6) is a divider that further divides the frequency divider output of (5) by 1/M (
7a) is connected to the gate circuit. (8) is a flip-flop circuit for periodically outputting the reception level drop detector output of (3) to the frequency divider output of (5). (9)
is a control circuit that generates a reset signal strobe signal for the counter circuit (start) and latch circuit (end) connected to the gate circuit output (7a), and the frequency divider output (6), (5)
) A reset signal and a strobe signal are generated by the frequency divider output.

αQ is a flip-flop circuit that outputs a low-level output in synchronization with the flip-flop output (8), and controls the latch circuit α1 via the gate circuit αυ connected to this flip-flop circuit. α→ is an arithmetic circuit that measures the output of the latch circuit in the α frame.

FIG. 6 is an explanatory diagram showing the operation of FIG. 5.

The signal input from the received signal input terminal (1) is a signal that is a radio wave received from a base station, reduced to an intermediate frequency by a local oscillator and a mixer, and then waveform-shaped into a rectangular wave.

The frequency of the input signal can be found by counting the number of pulses of this input signal with a counter circuit (2), holding the count value with a latch circuit (g), and measuring this with the arithmetic circuit α→.

The output of the reference oscillator (4) is sent to the divider (5)? The measurement period is set by dividing the frequency by (6) and opening and closing the gate (7a) at a constant period.

If the input signal drops below a certain level during this measurement period, the count value for that measurement period is not adopted. Therefore, the reception level drop detector (3) detects a drop in the input signal, closes the gate circuit αυ via the flip-flop circuit (8) #aO, and sends a latch command from the control circuit (9) to the latch circuit (to). This prevents inaccurate count values from being latched.

The signal input from the received signal input terminal of (1) is (7a)
While the other input of the gate is at a high level, the counter circuit (b) operates, and after the frequency divider output (6) changes from high level to low, the control circuit (9) first operates. @
The output of the counter circuit (6) is latched by the latch circuit 03 using the strobe signal, the frequency is measured by the arithmetic circuit α4, and then the counter circuit (6) is reset by the reset signal. When the output of the frequency divider (6) becomes high level again, the received signal passes through the gate circuit (7a) and a counting operation is performed. Here, when the received level signal in (2) decreases, the received level signal drop detector in (3) operates, and (
The D input of the flip-flop circuit (8) goes from high level to low level, and the flip-flop circuit (8) of the flip-flop circuit αQ blocks the strobe signal of the latch circuit (2) of the gate period with the gate circuit of αυ. ,
Frequency measurement of this gate period is not performed. Therefore, it is possible to prevent miscounting of frequencies when the reception level drops.

[Problem that the invention seeks to solve]

Conventional frequency measurement devices are configured as described above (because they are configured in this way, they do not measure the frequency when the reception level drops during the measurement period, so they only measure the frequency when the reception level is continuously high for a certain period of time). is possible. Therefore,
If the reception level fluctuates greatly due to fading or the like and the reception level continues to drop during the measurement period, frequency measurement is difficult to carry out and measurement takes time.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a frequency measuring device that can measure frequencies in a short time even when reception level fluctuations are large due to fading or the like.

[Means for solving problems]

The frequency measurement device according to the first invention of the present application, even when the received level of the input signal decreases within the measurement period, ignores the input signal during the period of decrease and extends the measurement time by the period of decrease. This enables frequency measurement.

A frequency measuring device according to a second aspect of the present invention is provided with an oscillator having almost the same frequency as the input signal, and counts the output of the oscillator during a period when the level of the input signal is decreasing.

[Effect]

When the level of the input signal decreases, the frequency measuring device according to the first invention lengthens the measurement time by the period of the decrease and ignores the input signal during the period of decrease.

The frequency measuring device according to the second aspect of the invention counts the output pulses of the oscillator having substantially the same frequency as the input signal during the period when the level of the input signal is decreasing.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In FIG. 1, (1) is a received signal input terminal, into which normally an intermediate frequency amplitude-limiting amplifier output signal of a receiver is input. (2) is a reception level signal input terminal, (3) is a reception level drop detector that detects a drop in reception level, (4)
is a reference oscillator for creating a gate signal for frequency measurement, and here it is selected to be N times the received signal frequency in (1). (5) is a divider that changes the frequency of the reference oscillator to 1/N.
The frequency is divided and a frequency approximately equal to the received signal frequency in 1) is output. (6) is a divider which divides the frequency of the frequency divider output of (5) by 1/M through the αG gate circuit and is connected to the gate circuit (7b). (8) is a flip-flop circuit for outputting the output of the reception level drop detector (3) in synchronization with the frequency divider output (5). (9) is a control circuit that generates the counter circuit connected to the gate circuit output in (7), the reset signal for the time latch circuit, and the strobe signal; A reset signal and a strobe signal are generated by the frequency generator output. 04 is an arithmetic circuit that measures the output of the (to) latch circuit.

FIG. 2 is an explanatory diagram showing the operation of FIG. 1.

During the input signal level drop period, the reception level drop detector (
The output of 3) becomes L level. In response, the Q output of the flip-flop circuit (8) goes to L level, closes the gate circuit (7b), and stops counting the input signals during the level drop period. Further, during the level drop period, the Q output of the flip-flop circuit (8) becomes H level, and the input from the divider (5) to the divider (6) is invalidated by the OR gate circuit αG. As a result, the time during which the divider (6) opens the gate circuit (7b) is extended by the period when the Q output is at the H level.

Next, the operation will be explained. The input signal input from the received signal input terminal of (1) operates the counter circuit of (2) while the input of the frequency divider output side of (6) of the gate (7b) is at a high level. After the frequency divider output changes from high level to low level, the control circuit (9) first latches the Kei counter circuit output to the latch circuit 03 using the strobe signal, and the arithmetic circuit (14) latches the output of the counter circuit 03. The frequency is measured and then the @ counter circuit is reset by a reset signal. When the frequency divider output of (6) becomes high level again, the received signal passes through the gate circuit (7) and a counting operation is performed. Here, when the received level signal (2) decreases, the received level signal/drop detector (3) operates, and the D input of the flip-flop circuit (8) changes from high level to low level, and (5) ), a low level signal is sent to the flip-flop circuit (8) to the gate circuit (7b), and a high level signal is sent to the gate circuit (a) in synchronization with the rise of the frequency divider output, and the reception level is High ζ)′″′C(3
) The input signals of the counter circuit in a and the branching unit in (6) are held at low and high levels, respectively, until the detector in (6) outputs a high level output, and the gate time of the counter is maintained until the received level signal is low. The period is extended, and the counter operation is stopped during the period when the reception level signal is low. Therefore, even when reception level fluctuations are large due to fading or the like and the reception level frequently decreases, the frequency can be measured in a relatively short time by extending the time during which the reception level signal has decreased.

In addition, in the embodiment described above, an example was shown in which the gate time of the counter is extended only during the period when the reception level decreases.
The gate time of the counter is constant, and the measurement may be performed by switching the reception input signal to be measured to another reference signal only during the period when the reception level is decreasing.

This embodiment will be explained below with reference to the figures. In FIG. 3, QQ is a switch circuit for switching the received signal to be measured, and the other parts are the same or equivalent to those in the embodiment shown in FIG. FIG. 4 is an explanatory diagram showing the operation of FIG. 3. Next, the operation will be explained. During the period when the reception level signal is lowered, the switch circuit Ql19 is controlled by the flip-flop output (8), and the QQ switch is switched to the frequency divider output side (5). Here, since the frequency divider output in (5) is selected to be almost the same as the received signal frequency in (1), there is almost no error even if the frequency divider output in (5) is counted only during the period when the reception level decreases. The measurement can be completed within a certain counter gate time without causing any problems.

〔Effect of the invention〕

In the first invention of the present application, frequency measurement is stopped during the period when the level of the input signal is decreasing, and when the level of the input signal is recovered, the measurement period is extended by the period when the level is decreasing, so that the frequency can be measured in a short time. It produces the effect that can be achieved.

In the second aspect of the present invention, the output of the oscillation circuit having almost the same frequency as the input signal is counted during the period when the level of the input signal is decreasing, so that the frequency can be measured in a short time.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a frequency measuring device according to an embodiment of the present invention, Fig. 2 is an explanatory diagram showing its operation, Fig. 3 is a block diagram according to another embodiment of the invention, and Fig. 4 is its operation. Fig. 5 is a configuration diagram of a conventional frequency measuring device, Fig. 6 is an explanatory diagram showing
The figure is an explanatory diagram showing the operation. In the figure, (1) is a received signal input terminal, (2) is a received level signal input terminal, (3) is a received level drop detector,
(4) is the reference oscillator, (5) # (6) is the branch unit, (
7a), (7b), Qu. αθ is a gate circuit, (8) and α0 are flip-flop circuits, (9) is a control circuit, @ is a counter circuit, α4 is a latch circuit, a< is an arithmetic circuit, and aQ is a switch circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A counter circuit that counts the number of pulses of an input signal, a gate circuit that controls the opening and closing of the input signal to this counter circuit, and a control that opens this gate circuit at a constant cycle and allows the input signal to pass through to the counter circuit. a measurement period setting circuit that applies a signal to the gate circuit; and a measurement period setting circuit that compares the input signal with a set level, closes the gate circuit when the input signal is below the set level, and controls the control signal of the measurement period setting circuit when the input signal returns to the set level or higher. A frequency measuring device comprising: a level drop detector that extends the period during which the input signal is below a set level. (2) A counter circuit that counts the number of pulses of an input signal, a gate circuit that controls opening and closing of the input signal to this counter circuit, and a control that opens this gate circuit at a constant cycle and allows the input signal to pass through to the counter circuit. a measurement time setting circuit that applies a signal to the gate circuit; an oscillation circuit that outputs a frequency substantially the same as the input signal; and a level drop detector that compares the input signal with a set level and outputs an output when the input signal is below the set level. and a switch circuit that inputs the output of the oscillation circuit as an input signal to the gate circuit during the output period of the level drop detector.