JPH02114557A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02114557A
JPH02114557A JP26736388A JP26736388A JPH02114557A JP H02114557 A JPH02114557 A JP H02114557A JP 26736388 A JP26736388 A JP 26736388A JP 26736388 A JP26736388 A JP 26736388A JP H02114557 A JPH02114557 A JP H02114557A
Authority
JP
Japan
Prior art keywords
semiconductor device
via holes
ground
ground conductor
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26736388A
Other languages
Japanese (ja)
Other versions
JP2720481B2 (en
Inventor
Akira Inoue
晃 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63267363A priority Critical patent/JP2720481B2/en
Publication of JPH02114557A publication Critical patent/JPH02114557A/en
Application granted granted Critical
Publication of JP2720481B2 publication Critical patent/JP2720481B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the number of via holes and to reduce a chip size by a method wherein the circumference of a semiconductor device is surrounded by a ground conductor. CONSTITUTION:The circumference of a semiconductor device is surrounded by a ground conductor 6 connected to ground electrodes 3 on the rear of the semiconductor device via holes 4. In general, a space is available in a circumferential part of the semiconductor device 8; the ground conductor 6 can be arranged easily; a width of the ground conductor 6 can be made large; accordingly, the individual ground electrodes 3 and the via holes 4 can be connected at a low inductance. Thereby, the via holes 4 can be used in common; the individual ground electrodes 3 can be grounded by the via holes 4 whose number is small; a chip size can be reduced; a cost of the semiconductor device 8 can be lowered.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に係り、特にモノリシックマイ
クロ波集積回路装置(以下、MMMoaいう)に関する
ものである0 〔従来の技術〕 第5図は、従来の半導体装置の一例を示す模式上面図で
、(1)は半導体基板で、この上に各素子が形成されて
、構成されるo(2) 、 f3+ 、 (5)はそれ
ぞれ金属電極であって、(2)は高周波信号に用いられ
る電極(以下RF電極という)、(3)は接地電極、(
5)は直流バイアス印加用の電極(以下Do″+を極と
いう)である。(4)は半導体基板(1)の裏面の接地
電極(3)と半導体基板(1)上面の接地電極(3)を
結ぶ貫通導体線路を成すバイアホールである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a monolithic microwave integrated circuit device (hereinafter referred to as MMMoa). [Prior Art] FIG. , is a schematic top view showing an example of a conventional semiconductor device, in which (1) is a semiconductor substrate, each element is formed on this, and o(2), f3+, and (5) are metal electrodes, respectively. (2) is an electrode used for high frequency signals (hereinafter referred to as RF electrode), (3) is a ground electrode, (
5) is an electrode for applying a DC bias (hereinafter referred to as a pole). (4) is a ground electrode (3) on the back surface of the semiconductor substrate (1) and a ground electrode (3) on the top surface of the semiconductor substrate (1). ) is a via hole that forms a through conductor line.

次に動作について説明する。一般にMMMoaは、マイ
クロ波帯の高周波信号を扱うため、金属配線や評価用の
プローブ針は、分布定数線路として機能する。このため
、プローブ針もコプレーナ線路などの伝送線路が用いら
れている。半導体装置のウェハ状態での評価では、グロ
ーブ針の接地導体と半導体装置の接地電極(3)とを、
高周波的に良好な状態で接触させ、不要な高周波信号の
反射が生じないようにする必要がある。このためRF電
極(2)の近傍に、接地電極(3)を設け、各々の接地
電極(31とプローブ針の接地導体を接触させなければ
ならず、多数の接地電極(3)が必要である。また、直
流バイアスの印加に当っても、半導体装置より漏れる高
周波信号があるため、直流バイアス印加用針にも伝送線
路を用い、高周波的に所望の特性インピーダンスにする
必要があり、直流バイアス印加用針の接地導体と半導体
装置の接地電極(3)とを高周波的に良好に接触しなけ
ればならない。そのため、DOK極(5)にも接地電極
(3)が必要となり、多数の接地電極(3)が必要であ
る。
Next, the operation will be explained. Since MMMoa generally handles high frequency signals in the microwave band, the metal wiring and the probe needle for evaluation function as a distributed constant line. For this reason, a transmission line such as a coplanar line is also used for the probe needle. In the evaluation of the semiconductor device in the wafer state, the ground conductor of the globe needle and the ground electrode (3) of the semiconductor device are
It is necessary to make contact in a good condition in terms of high frequency to avoid unnecessary reflection of high frequency signals. For this reason, a ground electrode (3) must be provided near the RF electrode (2), and each ground electrode (31) must be brought into contact with the ground conductor of the probe needle, thus requiring a large number of ground electrodes (3). Also, when applying DC bias, there is a high frequency signal that leaks from the semiconductor device, so it is necessary to use a transmission line for the needle for applying DC bias to achieve the desired characteristic impedance at high frequencies. The grounding conductor of the needle and the grounding electrode (3) of the semiconductor device must be in good contact at high frequencies. Therefore, the grounding electrode (3) is also required for the DOK pole (5), and a large number of grounding electrodes ( 3) is necessary.

一般に接地電極(3)は、バイアホール(4)により裏
面の接地電極(3)に結ばれているため、多数の接地電
極(3)があると多数のバイアホール(4)が必要であ
る。ところがバイアホールは、300声mx 3oop
mと大きなスペースを必要とするため、半導体装置の大
きさ(以下チップサイズという)が大きくなる。
Generally, the ground electrode (3) is connected to the ground electrode (3) on the back side by a via hole (4), so if there are a large number of ground electrodes (3), a large number of via holes (4) are required. However, Via Hall has 300 voices mx 3oop.
Since a large space of m is required, the size of the semiconductor device (hereinafter referred to as chip size) becomes large.

〔発明が解決しようとする課燻〕[The problem that the invention attempts to solve]

従来の半導体装置は以上のように構成されているので各
RF電極(2)やDCi極(5ンの近傍に接地電極[3
1を設けなければならず、多数のバイアホール(4)を
設けることが必要で、チップサイズが大きくなってコス
トが高くなってしまう問題点があった。
Since the conventional semiconductor device is configured as described above, a ground electrode [3] is placed near each RF electrode (2) and DCi pole (5).
1, and it is necessary to provide a large number of via holes (4), resulting in a problem that the chip size becomes large and the cost increases.

この発明は上記のような問題点を解消するためになされ
たもので、半導体装置の周囲を接地導体により囲むこと
によって、バイアホールの個数を少なくでき、チップサ
イズを小さくすることが可能で、コストを低減できる半
導体装置を得ることを目的とする。
This invention was made to solve the above problems, and by surrounding the semiconductor device with a ground conductor, the number of via holes can be reduced, the chip size can be reduced, and the cost can be reduced. An object of the present invention is to obtain a semiconductor device that can reduce the

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体装置の周囲を接地
導体により囲んだものである。
In the semiconductor device according to the present invention, the semiconductor device is surrounded by a ground conductor.

〔作 用〕[For production]

この発明における半導体装置は、半導体装置の周囲を接
地導体により囲むことにより、多数の接地電極に必要な
バイアホールを共用でき、バイアホールの個数を削減で
きるため、チップサイズを小さくできる。
In the semiconductor device according to the present invention, by surrounding the semiconductor device with a ground conductor, the via holes necessary for a large number of ground electrodes can be shared, and the number of via holes can be reduced, so that the chip size can be reduced.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例による半導体装置の模式上面図
、第2図は第1図に示す半導体装置をウェハよりスクラ
イプする以前のウェハを示す模式上面図である。図にお
いて、(1)〜(5)は第5図の従来例に示したものと
同等であるので説明を省略する。図中の斜線部は、パイ
7ホール(4)を介して半導体装置裏面の接地電極(3
)に結ばれた接地導体(6)であり、半導体装置の周囲
を囲んでいる。
An embodiment of the present invention will be described below with reference to the drawings. 1st
1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic top view showing a wafer before the semiconductor device shown in FIG. 1 is scribed from the wafer. In the figure, (1) to (5) are the same as those shown in the conventional example of FIG. 5, and therefore their explanation will be omitted. The shaded area in the figure indicates the ground electrode (3) on the back side of the semiconductor device via the pie 7 hole (4)
) and surrounds the semiconductor device.

(7)はスクライプライン、(8)は半導体装置、(9
)はウェハである。
(7) is a scribe line, (8) is a semiconductor device, (9
) is a wafer.

次に動作について説明する。半導体装R(8)のRIF
電極(2)、接地電極(3)及びDC電極(5)は、ア
センブリが容易なように、半導体装置(8)の周辺部に
形成されるため、第1図のように接地導体(6)を周囲
部分に設けるのが、最も効率的である。また、−般に半
導体装置(8)の周囲部分には、ス、クライブ時のダメ
ージを避けるため、回路素子を設けていない。半導体装
置(8)の周囲部分は、一般に余裕があり、容易に接地
導体(6)を配置できると共に、接地導体(6)の幅を
大きくとることが可能なため、低いインダクタンスで各
接地電極(3)とバイアホール(4)を結線できる。
Next, the operation will be explained. RIF of semiconductor device R(8)
Since the electrode (2), the ground electrode (3) and the DC electrode (5) are formed around the semiconductor device (8) for easy assembly, the ground conductor (6) is It is most efficient to provide it in the surrounding area. Further, in general, no circuit elements are provided around the semiconductor device (8) in order to avoid damage during scribing. There is generally ample space around the semiconductor device (8), and the ground conductor (6) can be easily arranged, and the width of the ground conductor (6) can be made large, so each ground electrode ( 3) and via hole (4) can be connected.

このように、半導体装置(8)の周囲を接地導体(6)
により囲んだため、バイアホール(4)を共用できるの
で、少ないバイアホール(4)により、各接地電極(3
)を接地でき、チップサイズの縮小が可能となり、半導
体装置(8)のコストを低くできる。
In this way, the ground conductor (6) is placed around the semiconductor device (8).
Since the via holes (4) can be shared, each ground electrode (3) can be
) can be grounded, the chip size can be reduced, and the cost of the semiconductor device (8) can be lowered.

次にウェハ状態での評価では、第2図の状態で、上面よ
りプローブ針を当てている。スクライプライン(7)は
ウェハ切断(スクライブ)時に削り取られる部分である
Next, for evaluation in the wafer state, a probe needle is applied from the top surface in the state shown in FIG. The scribe line (7) is a portion that is scraped off during wafer cutting (scribing).

なお、上記実施例では接地導体(6)をスクライプライ
ン(7)の外に設けたが、第3図に示すウニノーの上面
図のように、スクライプライン(7)上面にも接地導体
(6)を設けることにより、接地導体(6)の幅を大き
くでき、低インダクタンスにできるため、バイアホール
(4)の数を更に削減することができる。
In the above embodiment, the ground conductor (6) was provided outside the scribe line (7), but as shown in the top view of the Uni-Noh shown in FIG. By providing this, the width of the ground conductor (6) can be increased and the inductance can be reduced, so that the number of via holes (4) can be further reduced.

また、同一の幅になるようにすれば、スクライプライン
(7)の幅分だけ、チップサイズを縮小でき、第2図に
比べて、更にチップサイズを縮小可能で、半導体装置(
8)のコストを低くできる。
Furthermore, by making the width the same, the chip size can be reduced by the width of the scribe line (7), and the chip size can be further reduced compared to that shown in FIG.
8) The cost can be reduced.

また、第4図に示すウェハの上面図のように、接地導体
(6)を、複数の半導体装置にわたって設けることによ
り、チップサイズの縮小を行なうことも可能であり、上
記実施例と同様の効果を奏する。
Furthermore, as shown in the top view of the wafer shown in FIG. 4, by providing the ground conductor (6) over a plurality of semiconductor devices, it is also possible to reduce the chip size, and the same effect as in the above embodiment can be achieved. play.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、半導体装置の周囲を
接地導体により囲んだため、多数の接地電極に必要なバ
イアホールを共用でき、バイアホールの個数を削減でき
るので、チップサイズを縮小でき、半導体装置のコスト
を低くできる効果がある。
As described above, according to the present invention, since the semiconductor device is surrounded by a ground conductor, the via holes required for a large number of ground electrodes can be shared, and the number of via holes can be reduced, so the chip size can be reduced. This has the effect of lowering the cost of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例による半導体装置の模式
上面図、第2図は、第1図に示す半導体装置をウェハよ
りスクライプする以前のウエノ1を示す模式上面図、第
3図はこの発明の他の実施例によるスクライプライン上
に接地導体を設けたウェハを示す模式上面図、第4図は
、この発明の他の実施例による複数の半導体装置にわた
って接地導体を設けたウェハを示す模式上面図、第5図
は、従来の半導体装置の模式上面図である。 図において、(1)は半導体基板、(2)はRF4極、
(3)は接地電極、(4)はバイアホール、(5)はD
C電極、(6)は要地導体、(7)はスクライプライン
、(8)は半導体装置、(9)はウェハである。 なお、図中、同一符号は同一、又は相当部分をボす。 第1図 牛祥イ本基扱 尺F電す昂 坪にtノケメ バイアホール DXプ オシ) #−cゼニ 導 イ杢、 第2図 第4図 第3図 ♂14jl、 イ隼1項rx 1 ウェハ 第5図
FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic top view showing a wafer 1 before the semiconductor device shown in FIG. 1 is scribed from a wafer, and FIG. FIG. 4 is a schematic top view showing a wafer in which a ground conductor is provided on a scribe line according to another embodiment of the present invention, and FIG. 4 shows a wafer in which a ground conductor is provided across a plurality of semiconductor devices according to another embodiment of the present invention. FIG. 5 is a schematic top view of a conventional semiconductor device. In the figure, (1) is a semiconductor substrate, (2) is an RF4 pole,
(3) is the ground electrode, (4) is the via hole, (5) is D
C electrode, (6) is a main conductor, (7) is a scribe line, (8) is a semiconductor device, and (9) is a wafer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1 Ushisho basic handling measure F Densu Ngong Ping t Nokeme via hole DX setup) 1 Wafer Figure 5

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に複数個の高周波信号電極(以下RF電極
という)及び接地電極を有する半導体装置において、半
導体装置の周囲を接地導体により囲んだことを特徴とす
る半導体装置。
1. A semiconductor device having a plurality of high frequency signal electrodes (hereinafter referred to as RF electrodes) and a ground electrode on a semiconductor substrate, characterized in that the semiconductor device is surrounded by a ground conductor.
JP63267363A 1988-10-24 1988-10-24 Semiconductor device Expired - Lifetime JP2720481B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63267363A JP2720481B2 (en) 1988-10-24 1988-10-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63267363A JP2720481B2 (en) 1988-10-24 1988-10-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02114557A true JPH02114557A (en) 1990-04-26
JP2720481B2 JP2720481B2 (en) 1998-03-04

Family

ID=17443788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63267363A Expired - Lifetime JP2720481B2 (en) 1988-10-24 1988-10-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2720481B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56161342U (en) * 1980-04-28 1981-12-01
JPS6459831A (en) * 1987-08-31 1989-03-07 Toshiba Corp Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56161342U (en) * 1980-04-28 1981-12-01
JPS6459831A (en) * 1987-08-31 1989-03-07 Toshiba Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JP2720481B2 (en) 1998-03-04

Similar Documents

Publication Publication Date Title
JPH0151065B2 (en)
JPH04352305A (en) Method of adjusting three layer structured spiral inductor
JPH02114557A (en) Semiconductor device
JPH06338712A (en) High frequency integrated circuit
JPH11330298A (en) Package provided with signal terminal and electronic device using the package
JPS62294303A (en) Semiconductor device and its manufacture
US6051889A (en) Semiconductor device having a flip-chip structure
JPH02159753A (en) Semiconductor device
JPS63257306A (en) Semiconductor integrated circuit package
JPH06275736A (en) Semiconductor device
JP3854570B2 (en) High frequency device package
JPS61142803A (en) Integrated circuit
JPH11195720A (en) Semiconductor device
JPS61288446A (en) High-speed ic package structure
JPH02226801A (en) Distributed constant type transmission line
JPS61230333A (en) Integrated circuit
JP2878049B2 (en) High frequency transistor
JPH0799753B2 (en) Hybrid integrated circuit
JPH09196970A (en) Probe card
JPS6347610U (en)
JPS62176149A (en) Package for high frequency semiconductor element
JPS62291202A (en) Microstrip circuit
JPH03145141A (en) Semiconductor device
JPH0677228A (en) Sealed bump for high-frequency
JPS63124540A (en) Semiconductor device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071121

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081121

Year of fee payment: 11

EXPY Cancellation because of completion of term