JPH02113590A - Manufacture of printed-wiring board - Google Patents
Manufacture of printed-wiring boardInfo
- Publication number
- JPH02113590A JPH02113590A JP26662188A JP26662188A JPH02113590A JP H02113590 A JPH02113590 A JP H02113590A JP 26662188 A JP26662188 A JP 26662188A JP 26662188 A JP26662188 A JP 26662188A JP H02113590 A JPH02113590 A JP H02113590A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- conductor circuit
- wiring board
- printed wiring
- roughening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000007747 plating Methods 0.000 claims abstract description 102
- 239000004020 conductor Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000007788 roughening Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims abstract description 18
- 229910000365 copper sulfate Inorganic materials 0.000 claims abstract description 17
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims abstract description 9
- 239000004094 surface-active agent Substances 0.000 claims abstract description 6
- 125000006353 oxyethylene group Chemical group 0.000 claims abstract description 5
- 150000003464 sulfur compounds Chemical class 0.000 claims description 5
- 239000001011 safranin dye Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 abstract description 4
- 150000001875 compounds Chemical class 0.000 abstract description 3
- OARRHUQTFTUEOS-UHFFFAOYSA-N safranin Chemical compound [Cl-].C=12C=C(N)C(C)=CC2=NC2=CC(C)=C(N)C=C2[N+]=1C1=CC=CC=C1 OARRHUQTFTUEOS-UHFFFAOYSA-N 0.000 abstract 1
- 238000011282 treatment Methods 0.000 description 27
- 239000000243 solution Substances 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000010408 film Substances 0.000 description 14
- 239000010409 thin film Substances 0.000 description 13
- 238000009713 electroplating Methods 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000004381 surface treatment Methods 0.000 description 8
- 238000001556 precipitation Methods 0.000 description 7
- 229910001220 stainless steel Inorganic materials 0.000 description 6
- 239000010935 stainless steel Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 238000003756 stirring Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000013019 agitation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- UMGDCJDMYOKAJW-UHFFFAOYSA-N thiourea Chemical compound NC(N)=S UMGDCJDMYOKAJW-UHFFFAOYSA-N 0.000 description 2
- OIICUUGPVAEJSH-UHFFFAOYSA-M (2-bromophenyl)methyl-ethyl-dimethylazanium;bromide Chemical compound [Br-].CC[N+](C)(C)CC1=CC=CC=C1Br OIICUUGPVAEJSH-UHFFFAOYSA-M 0.000 description 1
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 1
- CYTYCFOTNPOANT-UHFFFAOYSA-N Perchloroethylene Chemical compound ClC(Cl)=C(Cl)Cl CYTYCFOTNPOANT-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Natural products NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- ZCDOYSPFYFSLEW-UHFFFAOYSA-N chromate(2-) Chemical compound [O-][Cr]([O-])(=O)=O ZCDOYSPFYFSLEW-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000366 copper(II) sulfate Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- CMMUKUYEPRGBFB-UHFFFAOYSA-L dichromic acid Chemical compound O[Cr](=O)(=O)O[Cr](O)(=O)=O CMMUKUYEPRGBFB-UHFFFAOYSA-L 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 150000002484 inorganic compounds Chemical class 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910000372 mercury(II) sulfate Inorganic materials 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000009864 tensile test Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、いわゆる転写法を利用した印刷配線板の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a printed wiring board using a so-called transfer method.
転写法を利用した印刷配線板の製造方法の1例を第4図
(a)〜(沿に示す。導電性の仮基板l上に金M薄膜2
をめっきにより形成する(第4図(a))。An example of a method for manufacturing a printed wiring board using the transfer method is shown in FIGS. 4(a) to 4(a).
is formed by plating (FIG. 4(a)).
金属薄膜2の上に、めっきレジスト3のイメージング(
imaging)により、形成しようとする導体回路と
逆のネガパターンを作製しくすなわち、形成しようとす
る導体回路の裏返しのパターンで金属薄膜2が露出する
ように、金属薄膜2をめっきレジスト3で覆い)、露出
している金属薄膜2の上に電気めっきにより導体回路4
を形成する(第4図(b))。導体回路4の接着力を高
めるため、導体回路4の表面に粗面化処理を施した(第
4図(C))後、めっきレジスト3を剥離除去する(第
4図(d))。この粗面化処理は、電気めっきにより、
導体回路4の表面に粗化めっき皮膜5を形成することに
より行っている。つぎに、仮基板1の導体回路4形成面
側に絶縁層材料7を重ね合わせて(第4図(el)、成
形プレス(矢印A、Bで示す)等により、導体回路4と
絶縁層8とを一体化し、仮基板lを剥離する(第4図(
f))。表面の金属薄膜2をエツチング等により除去し
て印刷配線板20が得られる(第4図(g))。Imaging the plating resist 3 on the metal thin film 2 (
(i.e., by covering the metal thin film 2 with a plating resist 3 so that the metal thin film 2 is exposed in the reverse pattern of the conductor circuit to be formed). , a conductor circuit 4 is formed by electroplating on the exposed metal thin film 2.
(Fig. 4(b)). In order to increase the adhesive strength of the conductive circuit 4, the surface of the conductive circuit 4 is roughened (FIG. 4(C)), and then the plating resist 3 is peeled off (FIG. 4(d)). This surface roughening treatment is done by electroplating.
This is done by forming a roughened plating film 5 on the surface of the conductor circuit 4. Next, the insulating layer material 7 is superimposed on the surface of the temporary substrate 1 on which the conductive circuit 4 is formed (FIG. 4(el)), and the conductive circuit 4 and the insulating layer 8 are formed by using a molding press (indicated by arrows A and B) or the like. and peel off the temporary substrate l (see Fig. 4).
f)). The printed wiring board 20 is obtained by removing the metal thin film 2 on the surface by etching or the like (FIG. 4(g)).
このように、転写法を利用した印刷配線板の製造方法は
、たとえば、導体回路を形成するためにエツチングを行
わずにすむため、導体回路のサイドエツチングが発生せ
ず、高密度の微細な回路パターンを形成できる点で優れ
ている。しかも、導体回路4の底面に粗化めっき皮膜5
が形成されているので、粗化めっき皮膜のない場合に比
べると、導体回路4と絶縁層8との接着力が強くなって
いる。In this way, the method of manufacturing printed wiring boards using the transfer method, for example, eliminates the need for etching to form conductor circuits, so side etching of conductor circuits does not occur, and it is possible to create high-density, fine circuits. It is excellent in that it can form patterns. Moreover, a rough plating film 5 is formed on the bottom surface of the conductor circuit 4.
is formed, the adhesive force between the conductive circuit 4 and the insulating layer 8 is stronger than that in the case without the roughened plating film.
しかし、上記従来の印刷配線板の製造方法は、導体回路
の表面を電気めっきにより粗面化処理するときに、微細
回路パターンへの析出不良、めっきレジスト際での粗面
化めっき析出不良が生じるという問題点があった。この
ため、導体回路と絶縁層との接着力が弱かったり、不良
な導体回路が形成されたりしていた。However, in the above-mentioned conventional method for manufacturing printed wiring boards, when the surface of the conductor circuit is roughened by electroplating, failure of deposition on the fine circuit pattern and failure of roughening plating at the edge of the plating resist occur. There was a problem. For this reason, the adhesive force between the conductor circuit and the insulating layer is weak, or a defective conductor circuit is formed.
そこで、この発明は、微細パターンやめっきレジスト際
であっても粗面状めっきの析出性を改善することができ
る印刷配線板の製造方法を提供することを課題とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a printed wiring board that can improve the precipitation of rough plating even when it is adjacent to a fine pattern or a plating resist.
上記課題を解決するため、発明者らは、粗面状めっきを
行うめっき液(めっき浴)の組成に着目し、上記の析出
不良を改善できる組成を検討し、この発明を完成した。In order to solve the above problems, the inventors focused on the composition of a plating solution (plating bath) that performs rough surface plating, studied a composition that could improve the above-mentioned precipitation defects, and completed the present invention.
したがって、この発明にかかる印刷配線の製造方法は、
めっきレジストを用いてめっき法により仮基板表面に形
成された導体回路の少なくとも粗化表面が、下記の成分
(a)および(b)のうち、少なくとも成分(alを含
む硫酸銅めっき液を用いた粗化めっきにより形成される
ものとされている。Therefore, the method for manufacturing printed wiring according to the present invention is as follows:
At least the roughened surface of the conductor circuit formed on the surface of the temporary substrate by a plating method using a plating resist is obtained by using a copper sulfate plating solution containing at least one of the following components (a) and (b) (Al). It is said that it is formed by roughening plating.
(a) オキシエチレン系界面活性剤、硫黄化合物お
よびサフラニン系染料の中から選ばれた少なくとも1種
。(a) At least one selected from oxyethylene surfactants, sulfur compounds, and safranin dyes.
(bl 塩化物イオン。(bl chloride ion.
上記の成分(a)および(blのうち、少なくとも成分
(a)を含む硫酸銅めっき液を用いることにより、粗化
めっきの析出性が改善され、めっきレジストに挟まれた
微細な回路溝やめっきレジスト際にも粗化めっきが析出
する。すなわち、微細な回路パターンの導体回路の表面
を粗化表面とすることができ、導体回路の表面の中央も
側部も同様に粗化表面とすることができる。したがって
、導体回路が微細なパターンであっても絶縁層との接着
力を強くすることができ、あるいは、導体回路の中央部
も側部も、絶縁層との接着力を同程度にすることができ
る。By using a copper sulfate plating solution containing at least component (a) of the above components (a) and (bl), the precipitation of roughened plating is improved, and fine circuit grooves and plating sandwiched between plating resists are improved. Roughening plating is also precipitated during resisting.In other words, the surface of the conductor circuit of a fine circuit pattern can be made into a roughened surface, and the center and sides of the surface of the conductor circuit can also be made into a roughened surface. Therefore, even if the conductor circuit has a fine pattern, the adhesive force with the insulating layer can be strengthened, or the adhesive force with the insulating layer can be maintained at the same level in both the center and the sides of the conductor circuit. can do.
つぎに、この発明にかかる印刷配線板の製造方法を、そ
の実施例を表す図面を参照しながら詳しく説明する。Next, a method for manufacturing a printed wiring board according to the present invention will be described in detail with reference to drawings showing examples thereof.
第1図(a)〜(hlは、この発明にかかる印刷配線板
の製造方法の第1の実施例を工程順に模式的に表す。FIGS. 1(a) to 1(hl) schematically represent a first embodiment of the method for manufacturing a printed wiring board according to the present invention in the order of steps.
まず、少なくとも表面が導電性である仮基板1の表面に
剥離層となる金属薄膜2を形成する(第1図(a))。First, a metal thin film 2 to be a release layer is formed on the surface of a temporary substrate 1 whose surface is conductive at least (FIG. 1(a)).
仮基板1としては、ステンレス、チタンなどの導電性の
金属板が使用されるが、絶縁基体の表面に導電性の層を
形成したものが使用されてもよい。これら導電性の金属
板や層は、仮基板上に剥離層となる金属薄膜、導体回路
などを電気めっきにより形成するときの雪掻として利用
される。仮基板lは、必要に応じて、少なくとも導体回
路を形成しようとする面を研磨、脱脂、酸処理などを適
宜施してもよい。前記剥離層は、たとえば、仮基板1を
電気めっきしたり、陽極電解処理や重クロム酸液浸漬処
理等のばくり処理を行ったりすることにより形成される
。As the temporary substrate 1, a conductive metal plate such as stainless steel or titanium is used, but an insulating substrate with a conductive layer formed on the surface may also be used. These conductive metal plates and layers are used as snow shovels when forming metal thin films, conductive circuits, etc. that will serve as release layers on temporary substrates by electroplating. If necessary, at least the surface of the temporary substrate 1 on which the conductor circuit is to be formed may be subjected to polishing, degreasing, acid treatment, etc. as appropriate. The release layer is formed, for example, by electroplating the temporary substrate 1 or by subjecting it to an anodic electrolysis treatment, a dichromic acid solution immersion treatment, or the like.
金属薄膜2の上に、めっきレジスト3のイメージングに
より、形成しようとする導体回路と逆のネガパターンを
作製しくすなわち、形成しようとする導体回路の裏返し
のパターンで金属薄膜2が露出するように、金属薄膜2
をめっきレジスト3で覆い)、露出している金属薄膜2
の上に電気めっきにより導体回路4を形成する(第1図
(b))。On the metal thin film 2, a negative pattern opposite to the conductor circuit to be formed is created by imaging the plating resist 3, that is, so that the metal thin film 2 is exposed in the reverse pattern of the conductor circuit to be formed. Metal thin film 2
covered with plating resist 3), and exposed metal thin film 2
A conductive circuit 4 is formed thereon by electroplating (FIG. 1(b)).
導体回路4の表面に粗面化処理を施した(第1図(C)
)後、めっきレジスト3を剥離除去して仮基板1の導体
回路形成面全面を露出させる(第1図(d))6以下、
導体回路4のうち少なくとも粗化表面を形成するための
粗面化処理を「第1次組面化処理」と言う。第1次組面
化処理は、たとえば、電気めっきにより、導体回路4の
表面に粗化めっき皮膜(粗化表面)5を形成することに
より行っている。そして、仮基板lの導体回路形成面全
面を粗面化処理する(第1図(e))。以下、仮基板1
の導体回路形成面全面に施す粗面化処理を「第2次相面
化処理」と言う。第2次相面化処理では、第1次組面化
処理で形成された、第3図(alにも見るような比較的
粗い粗化めっき皮膜5および金属薄膜2の上に、電気め
っきなどのめっき法により、第3図(b)にもみるよう
なより微細な粗面6を形成するのである。A roughening treatment was applied to the surface of the conductor circuit 4 (Fig. 1(C)
), the plating resist 3 is peeled off to expose the entire surface of the temporary substrate 1 on which the conductor circuit is formed (FIG. 1(d)) 6 and below.
A roughening process for forming at least a roughened surface of the conductor circuit 4 is referred to as a "first surface forming process." The primary surface forming treatment is performed by forming a roughened plating film (roughened surface) 5 on the surface of the conductive circuit 4 by, for example, electroplating. Then, the entire surface of the temporary substrate 1 on which the conductor circuit is formed is roughened (FIG. 1(e)). Below, temporary board 1
The surface roughening treatment performed on the entire conductor circuit forming surface is called "secondary phase surface treatment." In the second phase surface treatment, electroplating, etc. By this plating method, a finer roughened surface 6 as shown in FIG. 3(b) is formed.
仮基板lの導体回路4形成面側に絶縁層材料7を重ね合
わせて(第1図(fl)、成形プレス(矢印A、Bで示
す)等により、導体回路4と絶縁層8とを一体化し、仮
基Fi1を剥離する(第1図(g))。表面の金属薄膜
2および微細な粗面6をエツチング等により除去して印
刷配線板11が得られる(第1図(h))。この微細な
粗面6は、エツチングにより十分に除去され、隣り合う
導体回路4間の絶縁不良といった問題を生じない。The insulating layer material 7 is superimposed on the surface of the temporary substrate l on which the conductive circuit 4 is formed (FIG. 1 (fl)), and the conductive circuit 4 and the insulating layer 8 are integrated by a molding press (indicated by arrows A and B), etc. The surface metal thin film 2 and fine rough surface 6 are removed by etching or the like to obtain a printed wiring board 11 (FIG. 1(h)). This fine rough surface 6 is sufficiently removed by etching and does not cause problems such as poor insulation between adjacent conductor circuits 4.
第2図(al〜(glは、この発明の第2の実施例を工
程順に模式的に表す。この実施例では、導体回路全体を
第1次組面化処理で形成した粗化めっき皮膜5とするこ
と以外は、上記第1の実施例と同様に行う。第2図中、
第1図と同じものには同じ番号、記号を付している。第
1次組面化処理で導体回路を形成した後、めっきレジス
ト3を剥1tlt除去して仮基板1の導体回路形成面全
面を露出させる(第2図(C))。後は、第1の実施例
と同様にして印刷配線板10を得る(第2図(di−(
e)−(r)=(g) )上記第1および第2の実施例
は、第2次相面化処理も行っているので、導体回路と絶
縁層との接着力は、第2次相面化処理を行っていないも
のと比べると、大きくなっている。すなわち、この発明
では、第2次相面化処理を行わないよりも行う方が好ま
しい。FIG. 2 (al to (gl) schematically represent the second embodiment of the present invention in the order of steps. The process is carried out in the same manner as in the first embodiment above, except that:
Components that are the same as in Figure 1 are given the same numbers and symbols. After the conductor circuit is formed in the first assembling process, the plating resist 3 is stripped and removed by 1 tlt to expose the entire surface of the temporary substrate 1 on which the conductor circuit is formed (FIG. 2(C)). After that, the printed wiring board 10 is obtained in the same manner as in the first embodiment (see FIG. 2(di-(
e) - (r) = (g)) In the first and second embodiments above, the second phase surface treatment is also performed, so the adhesive force between the conductor circuit and the insulating layer is determined by the second phase surface treatment. It is larger than the one without surface treatment. That is, in the present invention, it is preferable to perform the secondary phase treatment rather than not performing it.
第1次組面化処理(第2次相面化処理を行わない場合)
または第2次相面化処理に続いて、接着力の耐熱・耐薬
品性を向上させる亜鉛めっき、クロメート処理を実施し
てから絶縁層を形成するようにしてもよい。このように
すると、導体回路と絶縁層との接着力が、熱や薬品に対
して劣化しにくくなるので好ましい。1st grading process (when not performing 2nd grading process)
Alternatively, the insulating layer may be formed after performing zinc plating or chromate treatment to improve the heat resistance and chemical resistance of adhesive strength following the secondary phase surface treatment. This is preferable because the adhesive strength between the conductor circuit and the insulating layer is less susceptible to deterioration due to heat and chemicals.
第2次相面化処理を複数回行って、導体回路と絶縁層と
の接着力をさらに向上させることもできる。第2次相面
化処理を複数回行う場合、同じ方法で粗面化処理を行っ
てもよいし、異なった粗面化処理を行ってもよい。後者
の場合、たとえば、エツチングにより仮基板の導体回路
形成面全面を粗面化したのち、さらに電気めっきにより
粗面化するという方法が採られる。The adhesion between the conductor circuit and the insulating layer can be further improved by performing the secondary phasing treatment multiple times. When performing the secondary phase surface treatment multiple times, the surface roughening treatment may be performed using the same method or may be performed using different surface roughening treatments. In the latter case, for example, a method is adopted in which the entire surface of the temporary substrate on which the conductor circuit is formed is roughened by etching, and then the surface is further roughened by electroplating.
この発明では、第1次組面化処理は、下記の成分(a)
および(b)のうち、少なくとも成分(a)を含む硫酸
銅めっき液を用いた粗化めっきにより行われるTa)
オキシエチレン系界面活性剤、硫黄化合物およびサフ
ラニン系染料の中から選ばれた少なくとも1種。In this invention, the primary composition treatment includes the following components (a):
and (b), Ta) performed by roughening plating using a copper sulfate plating solution containing at least component (a).
At least one selected from oxyethylene surfactants, sulfur compounds, and safranin dyes.
(bl 塩化物イオン。(bl chloride ion.
硫酸銅めっき液中の成分(a)の濃度は、0.001〜
10mMであることが好ましい。O,001mMを下回
ると、めっきレジストで挟まれた微細回路溝への析出性
改善効果が得られないことがある。The concentration of component (a) in the copper sulfate plating solution is 0.001 to
Preferably it is 10mM. If it is less than 0.001mM, the effect of improving the precipitation in the fine circuit grooves sandwiched between the plating resists may not be obtained.
10mMを上回ると、均一な粗化山が形成されないおそ
れがある。If it exceeds 10mM, there is a risk that uniform roughened peaks will not be formed.
硫酸銅めっき液中の成分(b)の濃度は、0〜200p
pmであることが好ましい。成分(b)を全く添加しな
くても、粗面状のパターンめっきを形成することができ
るが、成分(alの消費が非常に速くて補給回数が多く
なったり、成分(a)の分解生成物が蓄積したりして、
めっき液の再生処理(たとえば、活性炭処理)または新
建浴の必要が生じることがある。200ppmを上回る
と、均一な粗化山が形成されないおそれがある。The concentration of component (b) in the copper sulfate plating solution is 0 to 200p.
Preferably, it is pm. Although it is possible to form a rough pattern plating without adding component (b) at all, the component (Al) is consumed very quickly and needs to be refilled many times, and component (a) is decomposed and formed. Things accumulate,
It may be necessary to regenerate the plating solution (eg, activated carbon treatment) or to build a new bath. If it exceeds 200 ppm, there is a risk that uniform roughened peaks will not be formed.
成分(a)としては、オキシエチレン系界面活性剤、硫
黄化合物およびサフラニン系染料の中から選ばれた少な
くとも1種が使用される。硫黄化合物としては、たとえ
ば、チオ尿素など、=C=S。As component (a), at least one selected from oxyethylene surfactants, sulfur compounds, and safranin dyes is used. Examples of sulfur compounds include thiourea and the like, =C=S.
−S、=S=Oなどの基を持つ有機または無機の化合物
が使用される。Organic or inorganic compounds with groups such as -S, =S=O are used.
成分(blは、塩化物イオン(CI−)であり、たとえ
ば、硫酸銅めっき液中で塩化物イオンを生じうる化合物
をめっき液に添加することにより供給される。このよう
な化合物としては、たとえば、HCl2.NaCl1が
使用される。The component (bl) is a chloride ion (CI-), and is supplied, for example, by adding to the plating solution a compound that can generate chloride ions in the copper sulfate plating solution. Such compounds include, for example, , HCl2.NaCl1 are used.
この発明では、第2次組面化処理は、−船釣な粗化めっ
きにより行うことができるが、エツチング(たとえば、
浸漬、スプレーまたは電解)など他の方法により行って
もよい。被処理面に通電する場合には、電気めっきを行
う場合と同じ効果が得られる。In this invention, the secondary surface roughening treatment can be carried out by roughening plating, but can also be carried out by etching (for example,
Other methods such as dipping, spraying or electrolysis may also be used. When electricity is applied to the surface to be treated, the same effect as when performing electroplating can be obtained.
第1次組面化処理は、たとえば、成分(a)および(b
)のうち少なくとも成分(a)を必ず含み、Cu5O,
・511.0を10〜250 g/j!、H*SO,を
10〜250g/It、その他必要に応じて添加される
成分を含む適当な配合のめっき液を調製し、電流密度2
A/−程度、エアー攪拌しながら電気めっきで銅を粗面
状に析出することにより行われる。CuSO4・5Hオ
0は、多いほど高電流密度でめっき可能になるが、多す
ぎると均一電着性が劣ることがあるので、10g/It
程度が好ましい。H,SO4は多いほど均一電着性良好
であるが、多すぎるとCu5O+を多く入れられないこ
とがあるので、180g/j’程度が適当である。For example, the primary composition processing includes components (a) and (b).
), must contain at least component (a), Cu5O,
・511.0 from 10 to 250 g/j! , H*SO, at 10 to 250 g/It, and other components added as necessary.
This is carried out by depositing copper on a rough surface by electroplating to a degree of A/- while stirring with air. The more CuSO4.5H0 is used, the higher the current density becomes.
degree is preferred. The more H, SO4 there is, the better the uniform electrodeposition is, but if too much, Cu5O+ may not be able to be incorporated, so about 180 g/j' is appropriate.
第2次組面化処理は、たとえば、CuSO4・5H80
を10〜250 g/It、 HgSO4を10〜25
0 g/l、必要に応じて、HNOIをlθ〜200
g/l、20ppm程度の塩化物イオンなどを含む適当
な配合のめっき液を調製し、第1次組面化処理よりも高
電流密度、たとえば、5A#J程度で攪拌せずに3分間
程度電気めっきして銅を微細な粗面として析出すること
により行われる。Cu5Oa・5H80は、多いほど高
い電流密度でめっき可能になるが、多すぎると均一電着
性が劣ることがあるので、50 g / 1種度が好ま
しい。H1SO4は、多いほど均一電着性良好であるが
、多すぎるとCuSO4を多(入れられないことがある
ので、100g/j’程度が適当である。tlNO*を
添加すると微細な粗面を形成する条件範囲が広くなるの
で、めっきの条件管理がしやすくなる。oNosは、多
いほど高電流密度でのめっきが可能になるが、腐食性が
あるので作業環境との兼ね合いを考慮して添加量を設定
するのが好ましく、30 g / l程度が適当である
。塩化物イオンは、少ないほど高電流密度でのめっきが
可能になり、10ppm程度が適当である。また、第2
次組面化処理のめっき時に、攪拌を行う場合には、上記
電流密度よりもさらに高い電流密度にする必要がある。The secondary surface forming treatment is performed using, for example, CuSO4.5H80.
10-250 g/It, HgSO4 10-25
0 g/l, if necessary, HNOI lθ~200
Prepare a plating solution with an appropriate composition containing chloride ions of about 20 ppm, g/l, and plating at a current density higher than that of the primary grating treatment, for example, about 5A#J, for about 3 minutes without stirring. This is done by electroplating to deposit copper as a finely roughened surface. The more Cu5Oa.5H80 is used, the higher the current density becomes. The more H1SO4, the better the uniform electrodeposition, but if it is too much, CuSO4 may not be able to be added, so about 100g/j' is appropriate.When tlNO* is added, a fine rough surface is formed. The range of conditions for plating becomes wider, making it easier to manage plating conditions.The more oNos there is, the more plating becomes possible at higher current densities, but since it is corrosive, the amount added must be adjusted in consideration of the work environment. It is preferable to set the concentration of chloride ions, and approximately 30 g/l is appropriate.The smaller the amount of chloride ions, the more plating becomes possible at a higher current density, and approximately 10 ppm is appropriate.
When stirring is performed during plating in the subsequent surface forming treatment, it is necessary to use a current density higher than the above-mentioned current density.
工業的には、このようにして第2次組面化処理を行うの
が適切である。Industrially, it is appropriate to perform the secondary surface forming treatment in this manner.
第1次または第2次組面化処理のためのめっきを行う場
合、めっき液を攪拌することがあるが、その攪拌方法は
限定されない。たとえば、エアー攪拌したり、めっき液
をめっき槽内外で循環させてめっき槽外で攪拌したりす
ることが可能である。めっき液をめっき槽内外で循環さ
せる場合には、めっき槽へのめっき液の流入口、めっき
槽からのめっき液の流出口をそれぞれ、めっき液がめつ
き対象面に沿って流れるように配置してもよい。When performing plating for the first or second surface forming treatment, the plating solution may be stirred, but the stirring method is not limited. For example, it is possible to use air agitation, or to circulate the plating solution inside and outside the plating tank and stir it outside the plating tank. When circulating the plating solution inside and outside the plating tank, arrange the inlet for the plating solution into the plating tank and the outlet for the plating solution from the plating tank so that the plating solution flows along the surface to be plated. Good too.
また、めっき方法も上述のものに限られず、めっき全屈
のめっき液への供給方法も特に限定はない前記絶縁層材
料7としては、たとえば、樹脂を繊維質基材に含浸させ
てなるプリプレグ、樹脂のフィルムまたはシートなどが
使用される。また、絶縁層材料7を重ね合わせて成形プ
レスするという方法で導体回路4と絶縁層8とを一体化
する必要はなく、たとえば、仮基板をその導体回路形成
面がキャビティー内に向くようにしてキャビティーに配
置し、樹脂をキャビティー内に入れて成形して絶縁層8
を作るとともに、導体回路4と絶縁層8を一体化するよ
うにしてもよい。Further, the plating method is not limited to the above-mentioned method, and the method of supplying the plating solution to the plating solution for plating is not particularly limited. Examples of the insulating layer material 7 include prepreg made by impregnating a fibrous base material with resin; A resin film or sheet is used. Furthermore, it is not necessary to integrate the conductive circuit 4 and the insulating layer 8 by stacking the insulating layer materials 7 and pressing them together; for example, it is not necessary to integrate the conductive circuit 4 and the insulating layer 8 by overlapping the insulating layer materials 7 and pressing them. The resin is placed in the cavity and molded to form the insulating layer 8.
At the same time, the conductor circuit 4 and the insulating layer 8 may be integrated.
なお、この発明は上記実施例に限定されない。Note that this invention is not limited to the above embodiments.
たとえば、導体回路は、全体的に同一の材料で作られて
いる必要はなく、ボンディング部分を別の導電性材料で
作るようにしてもよい。導体回路と絶縁層とを一体化す
る前にめっきレジストを除去する必要はなく、めっきレ
ジストも絶縁層と一体化したりしてもよい。For example, the conductor circuit need not be made entirely of the same material; the bonding portions may be made of different conductive materials. It is not necessary to remove the plating resist before integrating the conductive circuit and the insulating layer, and the plating resist may also be integrated with the insulating layer.
以下に、この発明の具体的な実施例および比較例を示す
が、この発明は、下記具体的な実施例に限定されない。Although specific examples and comparative examples of the present invention are shown below, the present invention is not limited to the following specific examples.
一実施例1−
上記第1の実施例にしたがって印刷配線板を作った(第
1図(al〜(h))。Example 1 - A printed wiring board was made according to the first example described above (FIG. 1 (al to h)).
ビニールの粘着テープをマスキングテープとして用い、
同マスキングテープを貼りつけて片面をマスキングした
厚み1. O龍のステンレスFi(仮基板1)に光沢硫
酸銅めっきを施し、同ステンレス板のマスキングしてい
ない方の片面に厚み4.5p■の銅皮膜(金属薄膜2)
を形成した。この光沢硫酸銅めっきは、つぎの条件で行
った。Using vinyl adhesive tape as masking tape,
Thickness of one side masked with the same masking tape: 1. Bright copper sulfate plating is applied to Oryu's stainless steel Fi (temporary board 1), and a 4.5p thick copper film (metal thin film 2) is applied to the unmasked side of the same stainless steel plate.
was formed. This bright copper sulfate plating was performed under the following conditions.
得られた銅皮膜の上に、めっき用ドライフィルム(東京
応化工業株式会社製のプリント板めっき用ネガ型光硬化
性レジスト樹脂商標オーディルAP938)(めっきレ
ジスト3)を用いて、形成しようとする導体回路パター
ンの裏返しのパターンで銅皮膜が露出するように、ネガ
パターンを形成した。On the obtained copper film, use a dry film for plating (negative photocurable resist resin trademark Ordil AP938 for printed board plating manufactured by Tokyo Ohka Kogyo Co., Ltd.) (plating resist 3) to form a conductor. A negative pattern was formed so that the copper film was exposed by turning the circuit pattern upside down.
さらに、光沢硫酸銅めっきを行い、前記露出した銅皮膜
の上に、厚み30μ■のパターンめっき回路(導体回路
4)を形成した。この光沢硫酸銅めつきは、下記の条件
で行った。Furthermore, bright copper sulfate plating was performed, and a patterned plating circuit (conductor circuit 4) having a thickness of 30 μm was formed on the exposed copper film. This bright copper sulfate plating was performed under the following conditions.
さらに、つぎの条件で1次硫酸銅粗化めっき(第1次相
面化処理)を行い、パターンめっき回路の表面に厚み8
μ層の粗化めっき皮膜5を形成したつぎに、5M量%の
水酸化ナトリウム水溶液によりレジストを除去してステ
ンレス板のパターンめっき回路の形成された方の片面全
面を露出させ、この面金面に、硫酸銅粗化めっきにより
粗面化めっき(第2次組面化処理)を行って微細な粗面
6を形成した。この硫酸銅粗化めっきは、下記の条件で
行った。 ゛
全面に粗面化めっきの施された面にFR−4(NEMA
規格)のプリプレグ(エポキシ樹脂をガラス布基材に含
浸させてなるもの)(絶縁層材料7)を重ね合わせて、
温度170℃、圧力30kgf/cxl、時間90分間
の条件で加熱加圧成形し、一体化した。これにより、ス
テンレス板上に、銅皮膜を介して、導体回路が基板(絶
縁層8)に埋め込まれてなる積層板が形成された。この
積層板を銅皮膜とともに、ステンレス板から引き剥がし
たのち、表面の銅皮膜を過硫酸ナトリウムエツチング液
により除去し、印刷配線板11を得た。Furthermore, primary copper sulfate roughening plating (primary phase surface treatment) was performed under the following conditions, and the surface of the pattern plating circuit was coated with a thickness of 8.
After forming the μ layer roughening plating film 5, the resist is removed with a 5M% sodium hydroxide aqueous solution to expose the entire surface of the stainless steel plate on which the pattern plating circuit is formed. Then, surface roughening plating (secondary surface roughening treatment) was performed using copper sulfate roughening plating to form a fine rough surface 6. This copper sulfate roughening plating was performed under the following conditions. ``FR-4 (NEMA) is applied to the entire surface with roughening plating
Standard) prepreg (made by impregnating a glass cloth base material with epoxy resin) (insulating layer material 7),
They were integrated by heating and pressure molding at a temperature of 170° C., a pressure of 30 kgf/cxl, and a time of 90 minutes. As a result, a laminate was formed on the stainless steel plate in which the conductive circuit was embedded in the substrate (insulating layer 8) via the copper film. After this laminate was peeled off from the stainless steel plate together with the copper coating, the copper coating on the surface was removed using a sodium persulfate etching solution to obtain a printed wiring board 11.
一実施例2一
実施例1において、第2次組面化処理を行わなかったこ
と以外は、実施例1と同様にして印刷配線板を得た。Example 2 A printed wiring board was obtained in the same manner as in Example 1 except that the secondary surface forming treatment was not performed.
一実施例3−
上記第2の実施例にしたがって印刷配線板を作った(第
2図(al〜(幻)。Example 3 - A printed wiring board was made according to the second example (see Fig. 2 (illustration)).
実施例1において、パターンめっき回路の形成を光沢硫
酸銅めっきにより行う代わりに、第1次組面化処理によ
り行い、表面が粗面状の厚み38μのパターンめっき回
路(導体回路S)を形成したこと以外は、実施例1と同
様にして印刷配線板10を得た。In Example 1, instead of forming the patterned plating circuit by bright copper sulfate plating, it was performed by primary assembling treatment to form a patterned plating circuit (conductor circuit S) with a rough surface and a thickness of 38 μm. A printed wiring board 10 was obtained in the same manner as in Example 1 except for the above.
一実施例4一
実施例1において、第1次組面化処理の条件をつぎのよ
うにしたこと以外は、実施例1と同様にして印刷配線板
を得た。Example 4 A printed wiring board was obtained in the same manner as in Example 1, except that the conditions for the primary surface forming treatment were as follows.
(攪拌・・・−船釣なエアー攪拌条件
一実施例5一
実施例1において、第1次組面化処理の条件をつぎのよ
うにしたこと以外は、実施例1と同様にして印刷配線板
を得た。(Agitation... - Air agitation conditions for boat fishing - Example 5 - Printed wiring was carried out in the same manner as in Example 1, except that the conditions for the first assembling process were as follows. Got the board.
一比較例一
実施例1において、第1次組面化処理の条件をつぎのよ
うにしたこと以外は、実施例1と同様にして印刷配線板
を得た。Comparative Example 1 A printed wiring board was obtained in the same manner as in Example 1, except that the conditions for the primary surface forming treatment were as follows.
仮基板の導体回路形成面の裏面のマスキングは、転写成
形後もそのままにして、転写成形を繰り返すことができ
た。なお、転写成形を繰り返す場合、導体回路を剥離し
た面は研磨再生することが好ましい、最初の転写成形に
入る前にも仮基板の導体回路を形成しようとする面を研
磨することが好ましい。The masking on the back side of the conductor circuit forming surface of the temporary substrate was left as it was after transfer molding, and transfer molding could be repeated. In addition, when repeating transfer molding, it is preferable to re-polish the surface from which the conductor circuit has been peeled off. It is also preferable to polish the surface of the temporary substrate on which the conductor circuit is to be formed before starting the first transfer molding.
実施例1〜5および比較例で得られた各印刷配線板につ
いて、微細パターン(回路幅75n、回路同士の間隔7
5n)の導体回路の接着力を稠べた。測定方法は、JI
S規格C6481に準じた方法で、引張試験機を用いて
90”方向の引き剥がし強度を測定し、l cm幅あた
りに換算した。単位はkgf/cn+である。また、第
1次組面化処理終了後に、上記微細パターン部での粗化
めっきの析出状態を顕微鏡により観察し、うまく析出し
ている(○)か、否(×)かを調べた。結果を第1表に
示した。Regarding each printed wiring board obtained in Examples 1 to 5 and Comparative Example, fine patterns (circuit width 75n, interval between circuits 7
The adhesion strength of the conductor circuit (5n) was investigated. The measurement method is JI
The peel strength in the 90" direction was measured using a tensile testing machine in accordance with S standard C6481, and was converted to per 1 cm width. The unit is kgf/cn+. After the treatment was completed, the state of precipitation of the roughened plating on the fine pattern portion was observed using a microscope to determine whether the precipitation was successful (◯) or not (x).The results are shown in Table 1.
第 1 表
第1表かられかるように、各実施例で得られた印刷配線
板は、微細パターンの導体回路の接着力が大きく、しか
も、析出状態が良い。比較例のものは、微細パターンの
導体回路の接着力が非常に小さく、しかも、析出状態が
悪い、また、実施例の中でも、第2次組面化処理を行っ
た実施例1゜3〜5の方が、それを行っていない実施例
2よりも接着力が大きいことがわかる。成分(a)の中
でも、エチレングリコール系界面活性剤を用いた実施例
1,3は、他のものを用いた実施例4,5よりも接着力
が良い。Table 1 As can be seen from Table 1, in the printed wiring boards obtained in each example, the adhesive strength of the finely patterned conductor circuit was large, and the deposition state was good. In the comparative examples, the adhesion force of the conductor circuit of the fine pattern was very small, and the deposition condition was also poor. It can be seen that the adhesive force is greater in Example 2 in which this is not done. Among component (a), Examples 1 and 3 using an ethylene glycol surfactant had better adhesive strength than Examples 4 and 5 using other components.
以上に述べたように、この発明にかかる印刷配線板の製
造方法は、転写法を利用したものにおいて、微細パター
ンやめっきレジスト際であっても粗面状めっきの析出性
を改善することができ、微細パターンの導体回路と絶縁
層との接着力が改善された印刷配線板が得られる。As described above, the method for manufacturing a printed wiring board according to the present invention, which utilizes a transfer method, can improve the precipitation of rough plating even at the edge of a fine pattern or plating resist. , a printed wiring board with improved adhesion between the finely patterned conductor circuit and the insulating layer can be obtained.
第1図(al〜(hlはこの発明の印刷配線板の製造方
法の第1の実施例を工程順に模式的に表す断面図、第2
図(al〜(g)はこの発明の印刷配線板の製造方法の
第2の実施例を工程順に模式的に表す断面図、第3図(
a)および(blは第1次組面化処理にょる粗化めっき
皮膜と第2次組面化処理による微細な粗面を拡大して模
式的に表す断面図、第4図(al〜(川は従来の1例を
工程順に模式的に表す断面図である。
■・・・仮基板 3・・・めっきレジスト 4・・・導
体回路 5・・・粗化めっき皮膜 6・・・微細な粗面
8・・・絶縁層 10.11・・・印刷配線板
第2図FIG. 1 (al to (hl) is a sectional view schematically showing the first embodiment of the method for manufacturing a printed wiring board of the present invention in the order of steps;
Figures (al to g) are cross-sectional views schematically showing the second embodiment of the method for manufacturing a printed wiring board of the present invention in the order of steps;
a) and (bl are enlarged cross-sectional views schematically showing the roughened plating film obtained by the primary surface forming treatment and the fine roughened surface formed by the secondary surface forming treatment, and FIGS. The river is a cross-sectional view schematically showing one conventional example in the order of steps.■...Temporary substrate 3...Plating resist 4...Conductor circuit 5...Roughened plating film 6...Fine Rough surface 8... Insulating layer 10.11... Printed wiring board Figure 2
Claims (1)
上にめっきレジストを用いてめっき法により形成された
、粗化表面を有する導体回路を絶縁層と一体化して前記
仮基板を剥離し、前記絶縁層に前記導体回路が転写され
てなる印刷配線板を製造する方法において、前記導体回
路の少なくとも粗化表面が、下記の成分(a)および(
b)のうち、少なくとも成分(a)を含む硫酸銅めっき
液を用いた粗化めっきにより形成されることを特徴とす
る印刷配線板の製造方法。 (a) オキシエチレン系界面活性剤、硫黄化合物およ
びサフラニン系染料の中から選ばれた少なくとも1種。 (b) 塩化物イオン。[Scope of Claims] 1. A conductive circuit having a roughened surface formed by a plating method using a plating resist on the surface of a temporary substrate whose surface is electrically conductive at least, and which is integrated with an insulating layer to produce the temporary substrate. In the method for manufacturing a printed wiring board in which the conductor circuit is transferred to the insulating layer by peeling off the conductor circuit, at least the roughened surface of the conductor circuit contains the following components (a) and (
Among b), a method for manufacturing a printed wiring board, characterized in that the printed wiring board is formed by roughening plating using a copper sulfate plating solution containing at least component (a). (a) At least one selected from oxyethylene surfactants, sulfur compounds, and safranin dyes. (b) Chloride ion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26662188A JP2654126B2 (en) | 1988-10-22 | 1988-10-22 | Manufacturing method of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26662188A JP2654126B2 (en) | 1988-10-22 | 1988-10-22 | Manufacturing method of printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02113590A true JPH02113590A (en) | 1990-04-25 |
JP2654126B2 JP2654126B2 (en) | 1997-09-17 |
Family
ID=17433359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26662188A Expired - Fee Related JP2654126B2 (en) | 1988-10-22 | 1988-10-22 | Manufacturing method of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2654126B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094489A (en) * | 2007-09-19 | 2009-04-30 | C Uyemura & Co Ltd | Method of manufacturing buil-dup multilayer board |
JP2010067946A (en) * | 2008-09-08 | 2010-03-25 | Samsung Electro-Mechanics Co Ltd | Method of manufacturing printed circuit board |
KR20140112405A (en) * | 2013-03-13 | 2014-09-23 | 아지노모토 가부시키가이샤 | Method for manufacturing multilayer printed wiring board and composite containing prepreg with carrier metal foil using the same |
-
1988
- 1988-10-22 JP JP26662188A patent/JP2654126B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094489A (en) * | 2007-09-19 | 2009-04-30 | C Uyemura & Co Ltd | Method of manufacturing buil-dup multilayer board |
JP2014030055A (en) * | 2007-09-19 | 2014-02-13 | C Uyemura & Co Ltd | Method for manufacturing buildup laminated substrate |
TWI472280B (en) * | 2007-09-19 | 2015-02-01 | Uyemura C & Co Ltd | Manufacture method of buildup circuit board |
KR101505623B1 (en) * | 2007-09-19 | 2015-03-24 | 우에무라 고교 가부시키가이샤 | Manufacture method of buildup circuit board |
TWI479961B (en) * | 2007-09-19 | 2015-04-01 | Uyemura C & Co Ltd | Manufacture method of buildup circuit board |
JP2010067946A (en) * | 2008-09-08 | 2010-03-25 | Samsung Electro-Mechanics Co Ltd | Method of manufacturing printed circuit board |
KR20140112405A (en) * | 2013-03-13 | 2014-09-23 | 아지노모토 가부시키가이샤 | Method for manufacturing multilayer printed wiring board and composite containing prepreg with carrier metal foil using the same |
JP2014179388A (en) * | 2013-03-13 | 2014-09-25 | Ajinomoto Co Inc | Method of manufacturing multilayer printed wiring board and prepreg-containing composite material with carrier metal foil used for the same |
Also Published As
Publication number | Publication date |
---|---|
JP2654126B2 (en) | 1997-09-17 |
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