JPH02113494A - Multistage variable conductance circuit, neurochip using the circuit, read/write method for the chip, and semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a multistage variable conductance circuit which has a high reliability and is easy to integrate by connecting a variable conductance element to the connection point between a multidifferential negative resistance element and a load element in a series circuit consisting of them. CONSTITUTION:An FET 2 as the variable conductance element is connected to the connection point between a multidifferential negative resistance element 1 and a load resistance 3. Then, a multistage variable conductance circuit is constituted. That is, a multilevel stabilizing circuit consists of the element 1, and the conductance of the element 2 is controlled stepwise by its output. That is, the state which the conductance of the element 2 can take is limited to several discontinuous values. Thus, the reproducibility and the set precision of the output are improved. Integration is facilitated because the number of elements is smaller.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-stage variable conductance circuit suitable for constructing a neural circuit model, an integrated circuit called a neurochip using the same, and a method for reading and writing the same. , and a semiconductor device that implements the above circuit.

[Conventional technology]

Arithmetic elements based on conventional neural circuit models, that is, neurochips and their circuits are discussed, for example, in "Nikkei Microdevices", July 1988 issue, pages 53 to 65.

In the neurochip described above, the synapse, which is an important component thereof, is composed of, for example, a variable conductance circuit.

Conventionally, a method for realizing a variable conductance circuit is as shown in FIG. 5 (,), for example.

There is a method of changing the amount of charge accumulated in the gate 7 of the MOSFET 8, and a method of connecting a large number of FETs in parallel and changing the number of FETs in a conductive state, as shown in FIG. 8(b).

However, in method (a), the amount of accumulated charge changes over time due to the presence of current leak.
There are problems in terms of accuracy, reproducibility and reliability, and (b
) method has the problem that the number of elements connected in parallel increases, and as a result, density cannot be increased when attempting to integrate the device.

[Problem to be solved by the invention]

As mentioned above, in the conventional technology, the coupling constant changes due to leakage current, or a large number of elements are required to change the coupling constant, so there are problems in terms of reliability and ease of integration. There was a problem.

The purpose of the present invention is to solve the problems of the prior art as described above, to provide a multi-stage variable conductance circuit that is highly reliable and easy to integrate, and to provide a neurochip using the same. be.

[Means to solve the problem]

In order to achieve the above object, the invention according to the first claim includes: a multiple differential negative resistance element having two or more differential negative resistance characteristics in current/voltage characteristics; and a load element thereof;
A multi-stage variable conductance circuit is constituted by the multiple differential negative resistance element and the variable conductance element connected to the connection point between the two in the series circuit with the load element.

That is, in the present invention, a multi-value stable circuit is constructed by multiple differential negative resistance elements, and the conductance of the variable conductance element is controlled in stages according to the output thereof.

Note that the above-mentioned multiple differential negative resistance element is, for example, the first
This corresponds to the multiple differential negative resistance element 1 in the embodiment shown in Figure 3, and the load element is also the load resistor 3 or FETs 4 and 5.
, and the variable conductance element has the same <FET2
corresponds to

Further, in the invention according to the second claim, in the multi-stage variable conductance circuit according to the first claim,
The device is configured to switch the conductance from one stage to another by applying an external input to the connection point of the series circuit or the load element. The connection point for providing the above-mentioned external input corresponds to, for example, the control voltage input terminal 7 in the embodiments shown in FIGS. 1 to 3 described later.

Furthermore, in the invention set forth in claim 3, means corresponding to synapses in the neurochip are constituted by the multi-stage variable conductance circuit set forth in claim 1 or 2. A neurochip using this synapse corresponds to, for example, the embodiment shown in FIG. 11 described later.

In addition, the invention described in the fourth claim is an invention of a readout method in a double rotator using the synapse as described above, and includes a multiple differential negative resistance element and a load element of a multi-stage variable conductance circuit serving as the synapse. The connection state of the synapse is read out by extracting the potential at the connection point between the two in a series circuit (that is, the input point of the variable conductance element) to the outside.

This method corresponds, for example, to the method described in the embodiment shown in FIG. 12 below.

In addition, the invention stated in the 5th rJI claim is an invention of a writing method in a double rotor chip using the synapse as described above, and includes a multiple differential negative resistance element and a load element of a multi-stage variable conductance circuit serving as the synapse. The connection state of the synapse is switched by applying a pulsed voltage signal from the outside to the connection point or load element of the series circuit, and switching the operating point of the multi-stage variable conductance circuit. . This method corresponds to, for example, the method explained later using the circuit of FIG. 3 and the characteristic diagram of FIG. 4.

Further, the invention according to claim 6 is a semiconductor device comprising a multi-stage variable conductance circuit as described above,
At least one of a field effect transistor, a bipolar transistor, a photodiode, a light emitting diode, and a laser, and an element having a plurality of differential negative resistances in current/voltage characteristics are integrated on the same substrate. This semiconductor device corresponds to, for example, the embodiments shown in FIGS. 7 to 10 below.

Further, the invention as set forth in claim 7 is an invention showing a specific configuration of the semiconductor device as set forth in claim 6, wherein the element having the plurality of differential negative resistances is connected to a potential of at least three layers. It is configured to form a resonant tunnel structure having a barrier layer. This invention corresponds to, for example, the embodiments shown in FIGS. 7 to 9 below. That is, the possible states of the conductance of the variable conductance element are limited to several discontinuous values. This increases output reproducibility and setting accuracy. This also makes it possible to read out the output state accurately. Furthermore, since the number of elements is small, integration becomes easy.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

(Example 1) FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In Fig. 1, 1 is a multiple differential negative resistance element, 2 is an FE
T, 3 is a load resistance, 6 is a power supply terminal, and 7 is a control voltage input terminal.

The above-described multiple differential negative resistance element 1 has current-voltage characteristics as shown by a curve 100 in FIG. 4(a). In addition,
Although the characteristic of curve 100 in FIG. 4(a) is a double negative resistance characteristic, the essential circuit operation of an element having triple or more negative resistance characteristics is significantly different from that in the case of double negative resistance. Therefore, the operation will be explained below using the double negative resistance characteristic, that is, the curve 100 in FIG. 4(a). Furthermore, the characteristics shown by the curve 100 in FIG. 4(a) can be realized by connecting ordinary negative resistance elements in series.

In the circuit of FIG. 1, the power supply voltage is V. , when the voltage applied to the multiple differential negative resistance element 1 (hereinafter abbreviated as element 1) is V, the voltage applied to the load resistor 3 is V. −■ becomes. Since the current flowing through the gate of FET 2 can be ignored, the current flowing through element 1 and load resistor 3 are equal, and this is considered as a work. Further, since the product of the resistance value R of the load resistor 3 and the current I is the voltage drop in the load resistor, V, -V=R·min (1). Rewriting this, it becomes V=V, -RI (1)'.

The characteristic of (1)' above is shown in Figure 4 (a) by straight line 1.
It is 01.

As is clear from the above, the intersections of the straight line 101 and the curve 100 are the operating points of this circuit, but the three points 110, 111, and 112 are stable. That is, F.E.
The gate potential of T2 is one of the potentials 110, 111, and 112. These potentials can be switched by grounding the control voltage input terminal 7 via a suitable resistor.

Here, considering an operational amplifier circuit having an FET represented by FET2 in FIG. 1 as an input conductance, the sixth
The result will be as shown in the figure. Note that the circuit shown in FIG. 2.3 described later can be similarly applied instead of the circuit shown in FIG. 1.

In FIG. 6, an input conductance circuit 9 corresponds to the circuit in FIG. 1, and the FET 2 in FIG. 1 is connected as an input conductance as shown.

In this circuit, since the input terminal of the operational amplifier 10 is at the virtual ground potential, the FET 2 constituting the input conductance
The source-gate voltage of is equal to the voltage V applied to the element 1. Therefore, as the voltage (2) changes in multiple steps as described above, the conductance of FET 2 also changes in multiple steps. In the single operational amplifier circuit shown in FIG. 6, the amplification factor is the product of the input conductance value and the resistance value of the feedback resistor 11, so it is possible to change the amplification factor of this operational amplifier circuit.

As described in the explanation section of the conventional example, the conventional method of changing the conductance is as shown in FIGS. 5(a) and 5(b).
), but in (a), the amount of accumulated charge changes over time due to the presence of current leakage, so there are problems in terms of accuracy, reproducibility, and reliability.
Furthermore, in the parallel connection of elements as shown in (b), the number of elements increases, and as a result, there is a problem that the density cannot be increased when integrating the elements. In contrast, according to the present invention, it is possible to change the conductance in multiple stages with high precision, good reproducibility, and high reliability using a small number of elements.

(Example 2) FIG. 2 is a circuit diagram of a second embodiment of the invention.

This embodiment has a circuit in which the load resistor 3 shown in FIG. 1 is replaced with a normally-on type load FET 4.

There is a difference in current/voltage characteristics when the load is a resistor and when it is an FET, and as a result, only one load line corresponds to the load line in Example 1, that is, the straight line 101 in FIG. 4(a). In the example, the curve 104 is shown in FIG. 4(a). As a result, the operating point becomes 122.124°126.

This embodiment does not require a resistive element as compared to the first embodiment, and can be constructed with only two types of elements, an FET and a negative resistance element, which is advantageous in integration.

(Example 3) FIG. 3 is a circuit diagram of a third embodiment of the present invention.

This embodiment differs from FIG. 2 in that the control voltage input terminal 7 is the gate terminal of the load FE'r5. Therefore, the load curve changes depending on the gate voltage, that is, the potential of the control voltage input terminal 7 in FIG.
The curves are as shown in curves 102 to 106 in Figure (a). for example,
If the load curve is 106, the operating point is 120. Next, when the potential of the control voltage input terminal 7 is changed to change the load curve to 105.104, the operating point becomes 12.
1,122, and when the load curve further reaches 103, the operating point jumps and becomes 125.

If the control voltage is changed to return the load curve to 104, the operating point becomes 124.

FIG. 4(b) illustrates the above operation with the operating point voltage on the vertical axis and the control voltage on the horizontal axis.

The figure also shows the voltage at the operating point shown in FIG. 4 (,). Further, the arrows in the figure indicate the direction in which the operating points jump. For example, operating points 122, 124, and 126 are points on the same load curve, but switching between them is possible by pulsing the control terminal voltage for a short time and then returning it. can be easily understood from figure (b). That is, in this case, it is possible to switch the operating point using a pulse-like voltage signal from the outside, and there is an advantage that the external circuit can be simplified.

In addition, in the above-mentioned embodiment 1.2.3, the same operation can be performed even if bipolar transistors are used for the portions using FETs.

(Embodiment 4) FIG. 7 is a diagram showing a fourth embodiment of the present invention, and is a cross section of a semiconductor device that realizes the multiple differential negative resistance elements and load elements of the multi-stage variable conductance circuit as described above. A structural diagram is shown.

In FIG. 7, on a semi-insulating GaAs substrate 201, n
type GaAs channel layer 202 (n: 2XIO”
/ad, thickness 2000), multiple negative resistance diode 203 (multiple differential negative resistance element), and ohmic electrode 2
04°205.207 and Schottky gate electrode 20
6 is formed.

The above ohmic electrodes 204, 205 and 207 are made of AuGe alloy, and the Schottky gate electrode 2
Although AQ is used for 06, other materials can be used as long as they can obtain ohmic contact and Schottky contact, respectively.

In addition, the multiple negative resistance diode 203 has a quantum well layer (double barrier structure, all undoped) and 500mm thick n-type Ga
As (n: I
It has a structure sandwiched by s (n : 1 xlO"/a().

In this example, two quantum well layers were used to achieve double negative resistance characteristics, but to achieve triple, quadruple, or more negative resistance characteristics, the number of stacked quantum well layers could be changed accordingly. It can be increased accordingly.

An equivalent circuit of the structure shown in FIG. 7 is shown in FIG. 10(a).

Showing the correspondence between Figures 7 and 10, 203 is 306
, 204 is 303, 5205 is 304, 206 is 3
02 and 207 correspond to 301, respectively.

Terminal 303 of the circuit shown in FIG. 10(a) as above
By connecting this to the gate of another FET, the circuit shown in FIG. 3 can be constructed. That is, according to this embodiment, the circuit shown in the third embodiment of FIG. 3 can be easily formed on the same substrate, and a large number of the variable conductance circuits shown in the third embodiment can be easily integrated. I can do it.

Note that the thickness of the channel layer used here, the carrier concentration,
Alternatively, the values such as the thickness of the quantum well layer are not absolute, and the material is not limited to GaAs, but InGaAs, AQGaAs, etc. may also be used. In short, the key point of this embodiment is to integrate multiple barrier diodes on the FET structure. Furthermore, the electrode arrangement does not necessarily have to be as shown in FIG. It may also be provided on the side wall.

(Embodiment 5) FIG. 8 is a diagram showing a fifth embodiment of the present invention, in which a cross section of a semiconductor device realizing the multiple differential negative resistance element and load element portion of the multi-stage variable conductance circuit as described above is shown. A structural diagram is shown.

In FIG. 8, on a semi-insulating GaAs substrate 201, an n-type GaAs layer 211, a multiple negative resistance diode layer 203°r1-type GaAs collector WJ210 (n
: 5 xlO"/i, thickness 4000), p-type Ga
As base layer 209 (p:LXlo"/cd, thickness 1000), n-type A Q 0., Gao, 7As
Emitters /H2O3 (n: IXIO''/a&, thickness 2000) are formed, and ohmic electrodes 212, 213, 214, 215 are formed on them.

The above electrode 213 uses an A u Z n alloy, and the other electrodes use A u G c to obtain ohmic contact with the P-type and n-type Jv, respectively.

The equivalent circuit of this embodiment is shown in FIG. 10(b). That is, in this example, 208°209.
A bipolar transistor 307 having each layer of 210 as an emitter, base, and collector serves as a load element, and a multiple negative resistance diode 306 is connected in series with the bipolar transistor 307 .

In this embodiment, bipolar transistor 307
By applying an appropriate bias to the base of , the same effect as in the fourth embodiment can be obtained.

Although a GaAs/AQGaAs heterojunction bipolar transistor was used in this example, it may also be a homojunction transistor, or other materials such as I
Of course, similar effects can be obtained by using heterojunctions such as nGaP/GaAs and InAQAs/InGaAs, or homozygotes thereof.

(Embodiment 6) FIG. 9 is a diagram showing a sixth embodiment of the present invention, and is a partial sectional view showing only the emitter 208 and base 209 in FIG. 8.

In this embodiment, the portion of the emitter electrode 212 is
As shown in the figure, the bipolar transistor is made to function as a phototransistor by having a structure with an open window to allow external light to enter the emitter surface.

The equivalent circuit of this example is shown in FIG. 10(C).

In this embodiment, when switching the conductance, it is possible to use a light pulse instead of using an external voltage or current pulse.

Note that the emitter electrode 212 in this embodiment is as follows.

As in Example 5, an A u G c alloy was used, but if a transparent electrode such as In, O, SnO2, etc. is used instead, light can be made to enter without necessarily opening the window. Furthermore, if light is incident from the side or oblique direction in the figure, the same effect can be obtained even without opening the window.

(Embodiment 7) FIG. 11 is a circuit diagram of an embodiment of a neurochip using the multi-stage variable conductance circuit of the present invention.

In FIG. 11, i nl~i n-1in1~in
J is an input signal and its inverted input signal. Also, W.I.”
The part indicated by (i, j are natural numbers) is a so-called synapse, and the coupling element 401 (indicated by a circular symbol) constituting it is the multi-stage variable conductance circuit of the third embodiment. However, in this case, one with variable conductance in eight steps is used.

Note that in the coupling element 401, control voltage input terminals in the variable conductance circuit and the like are not shown, and the two terminals of the coupling element 401 correspond to both terminals of the FET 2 in FIG. 3.

Further, the input line is connected to each amplifier AP or axon Si, Si, etc. via a synapse. Furthermore, signals from various inputs and axons are weighted and input to the input of each amplifier AP through synapses. The output signal of the amplifier is then outputted to the axon again. That is, the human input signal has a feedback circuit called an amplifier-axon-synapse amplifier.

Due to the feedback action, the potential of each axon settles down to a certain stable point depending on the strength of the connection between the input signal and the synapse. This is so-called neurocomputing, and the axonal potential at a stable point, i.e., Si, SL (i is a natural number)
The potential of is the calculation result.

In this example, a chip was fabricated with 6 amplifiers and 30 synapses (only a part of which is shown in FIG. 11).

The number of elements required at this time is FET per amplifier.
5 elements, 12 elements per synapse, 1 total 390
It was. On the other hand.

When the conventional variable conductance circuit shown in FIG. 5(b) is used, 36 FETs are required per synapse, and a total of 1110 FETs are required to achieve the same function as in this embodiment. It becomes necessary.

Therefore, according to this embodiment, the number of elements can be significantly reduced, and the chip area can be significantly reduced. Furthermore, when using the variable conductance circuit shown in FIG.
Eight input lines are required for each coupling element, but in this embodiment, one input line is required for each coupling element regardless of the number of conductance variable stages, so the number of wiring lines can be significantly reduced.

(Example 8) FIG. 12 is a diagram showing the eighth example of the present invention, and Example 3
A readout FET 501 and a discrimination circuit 50 are added to the circuit shown in FIG.
2. A circuit with reference human power 503 is shown.

In the circuit of FIG. 12, the read FET501
is normally off, and becomes conductive by applying a gate voltage only during reading. Also.

The discrimination circuit 502 receives the signal from the readout transistor 501, that is, the FET serving as a variable conductance element.
2 gate potential (multiple differential negative resistance element 1 and load element 5
The electric potential at the connection point) is compared with the reference human power 503, and the difference and sign are output as a signal.

By doing so, it becomes possible to read out the magnitude of the conductance of the variable conductance element 2 non-destructively.

This circuit can be used, for example, as the coupling element 401 of the neurochip of the seventh embodiment.

When this circuit is used, the following becomes possible.

First, since it becomes possible to read out the connection state in a synapse, it becomes possible to completely copy the connection state of one neurochip to another chip. Copying is performed as follows. First, the connection state is read out at a certain synapse on the copy source chip by setting the reference human power 503 to zero potential, and that signal is used as the reference signal of the corresponding synapse on the copy destination chip. Next, a signal pulse is input to the control voltage input terminal 7 of the synapse to be copied, and the discrimination circuit 50
Make the output of 2 become zero. By repeating this for all synapses, it becomes possible to copy the connection state between chips.

Second, the bond state can be recorded on another medium, such as a magnetic recording material, using methods similar to those used for copying. The output of the neurochip for a certain input is
Changing the connection strength of synapses so as to match the originally required output is called learning, and according to this embodiment, the learning results can be recorded and copied.

〔Effect of the invention〕

According to the present invention, it is possible to stably realize a multi-stage variable conductance circuit with good accuracy and reproducibility with a small number of elements. Furthermore, the circuit of the present invention has the advantage that it can be easily integrated, and has many other excellent effects such as being able to realize a neurochip that can record and copy connection states with higher accuracy.

[Brief explanation of the drawing]

1 is a circuit diagram of Embodiment 1 of the present invention, FIG. 2 is a circuit diagram of Embodiment 2 of the present invention, FIG. 3 is a circuit diagram of Embodiment 3 of the present invention, and FIG. 4(a) is a circuit diagram of Embodiment 3 of the present invention. Example 1.2 of the invention. and 3, FIG. 4(b) is an input/output characteristic diagram of Example 3, and FIG.
The figure is a circuit diagram of a conventional example, and FIG. 6 is an embodiment 1.2 of the present invention.
and 3, FIG. 7 is a cross-sectional structural diagram of the fourth embodiment of the present invention, FIG. 8 is a cross-sectional structural diagram of the fifth embodiment of the present invention, and FIG. 9 is a cross-sectional structural diagram of the fifth embodiment of the present invention.
The figure is a cross-sectional structural diagram of a part of Embodiment 6 of the present invention, and FIG. 10 (
a), (b), and (c) are each Example 4.5゜6 of the present invention.
FIG. 11 is a circuit diagram of the seventh embodiment of the present invention, and FIG. 12 is a circuit diagram of the eighth embodiment of the present invention. Explanation of symbols> 1...Multiple differential negative resistance element 2...FET (variable conductance element) 3...
Load resistance 4...Load F E T5...
・Load FET 6...fIl, source terminal 7
...Control voltage input terminal 8...MO8FET9
...Input conductance 10...Operation amplifier 11...Feedback resistance 100...Multiple negative resistance characteristics 101...Resistive load characteristic straight lines 102-106...FET load characteristic curves 110-11
2...Operating point at resistive load 120-128...FE
Operating point at T load 201-=GaAs substrate 202...n-type GaAs channel layer 203...multiple negative resistance diode 204...output electrode 205...diode ground electrode 20G...gate electrode 207. ...Drain electrode 208...Emitter layer 209...Base layer 210...Collector layer 211...Electrode extraction layer 212...Emitter electrode 213...Base electrode 214...Collector electrode 215... Diode ground electrode 301...power supply terminal 302...control voltage input terminal 303...output terminal 304...ground terminal 305...load FET 306...multiple negative resistance cord 307...load Bipolar transistor 308...Phototransistor 401...Coupling element 501...Reading transistor 502...Discrimination circuit 503...Reference input

Claims (1)

[Claims] 1. A multiple differential negative resistance element having two or more differential negative resistance characteristics in current/voltage characteristics, a load element thereof, and a series connection of the multiple differential negative resistance element and the load element. A multi-stage variable conductance circuit comprising: a variable conductance element connected to a connection point between the two in the circuit. 2. The multi-stage variable conductance circuit according to claim 1, wherein the multi-stage variable conductance circuit is configured to switch the conductance from one stage to another by applying an external input to the connection point of the series circuit or the load element. . 3. In a neurochip equipped with means corresponding to a synapse serving as an input/output interface within or between neurons, the means corresponding to the synapse is constituted by the multi-stage variable conductance circuit according to the first or second claim. A neurochip characterized by: 4. In the neurochip according to claim 3, by extracting the potential at the connection point between the multiple differential negative resistance element and the load element in the series circuit of the multi-stage variable conductance circuit serving as the synapse to the outside. , a neurochip readout method characterized by reading out the connection state of synapses. 5. In the neurochip according to claim 3, a pulse is applied from the outside to a connection point between the multiple differential negative resistance element and the load element in a series circuit of the multi-differential negative resistance element and the load element in the multi-stage variable conductance circuit serving as the synapse. 1. A method for writing a neurochip, characterized in that a synaptic connection state is switched by applying a voltage signal of the form and switching the operating point of the multi-stage variable conductance circuit. 6. Field effect transistor, bipolar transistor,
1. A semiconductor device comprising at least one of a photodiode, a light emitting diode, and a laser, and an element having a plurality of differential negative resistances in current/voltage characteristics, integrated on the same substrate. 7. The semiconductor device according to claim 6, wherein the plurality of elements having differential negative resistance are formed in a resonant tunnel structure having at least three potential barrier layers.