JP3182182B2 - Magnetic-sensitive semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to a magnetic-sensitive type semiconductor device used for detecting a magnetic pole of a brushless motor in the like.

[0002]

2. Description of the Related Art A Hall element is generally used for detecting a magnetic pole of a brushless motor or the like. Since the output value of this Hall element is small, it is usually necessary to amplify it with an amplifier or the like. FIG. 5 shows a conventional configuration example of the amplifier circuit.

[0003] One current terminal 41c of the Hall element 41 is connected to the positive side of the power supply via a constant current FET 42, and the other current terminal 41d is grounded.

The output terminals 41a and 4a of the Hall element 41
1b is grounded to the gates of normally-on type FETs 43 and 44, respectively. Each of these FETs 43,
The outputs of the drain 44 are output O ₁ and O ₂ , respectively, and load resistors 45 and 46 are connected between each drain and the input side of the constant current FET 42, respectively.
The sources of the FETs 43 and 44 are connected to two level shift diodes 47a, 48a or 47, respectively.
b, 48b are grounded.

Here, the level shift diodes 47a,
The gates 48a, 47b, and 48b are provided because the amplification FETs 43 and 44 are of a normally-on type and their gate voltages need to be used lower than the source voltages.

FIG. 6 shows an example of a pattern obtained by converting the circuit of FIG. 5 into an IC.
Shown in

[0007]

The above-mentioned FIG.
In the amplifying circuit shown in (1), the level shift diodes 47a, 48a, 47b, and 48b are absolutely necessary.
In addition to this, not only an extra diode manufacturing process is required, but also a diode installation space is required to make the entire detector an IC, which hinders miniaturization of the IC. ing.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and comprises a Hall element, a constant current FET connected between a current terminal of the element and a power supply connection terminal. Amplifying FETs each having a gate grounded are connected to two output terminals of the Hall element, and
A resistor is connected between the output side of each FET and a power supply connection terminal. A hall element portion is provided at the center of the square IC chip, and each amplifying FET is provided on one diagonal side sandwiching the hall element portion. Section, FE for constant current on one side of the other diagonal
It is characterized in that a T portion is arranged.

It is particularly preferable that the active layer constituting the Hall element section is a two-dimensional carrier layer and the FET section is a HEMT.

[0010]

According to the above configuration, the output of the Hall element can be stably amplified without using a level shift diode, and the arrangement of circuit components can shorten the wiring distance and reduce the chip area. Can be measured.

Further, if the active layer constituting the Hall element portion is a two-dimensional carrier layer and each FET portion is a HEMT, the active layer becomes
Mobility of electrons in the three-dimensional electron gas layer (about 7000 cm ² / V
・ Sec) is the case of a single-layered active layer (about 5000 cm)
² / V · sec), and the thickness of the two-dimensional carrier gas layer is at least one order of magnitude thinner than the active layer formed by ion implantation. Is a HEMT, the switching speed can be increased.

[0012]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

One current terminal 1c of the Hall element 1 is connected to a power supply connection terminal 10 via a constant current FET 2, and the power supply connection terminal 10 is connected to a positive side of a drive power supply (not shown). . The other current terminal 1d is connected to the power supply connection terminal 11 (GND).

The sources of the amplifying FETs 3 and 4 are connected to the two output terminals 1a and 1b of the Hall element 1, respectively, and the gates of the FETs 3 and 4 are both grounded. On the drain side of each of the FETs 3 and 4, load resistances 5, 6
Is connected. Then, signals between the FET 3 and the load resistor 5 and between the FET 4 and the load resistor 6 are extracted as output signals O ₁ and O ₂ , respectively.

FIG. 2 shows a pattern diagram in which the circuit of FIG. 1 is integrated into an IC.

The IC is composed of a quadrangular chip. One Hall element is disposed in the center, amplification FETs 3 and 4 are disposed on one diagonal side of the Hall element, and two constant current FETs are disposed on one side of the other diagonal. ing. Reference numerals 5 and 6 are the above-described load resistors.

Next, the operation of the above circuit will be described.

First, the input resistance R _IN of the Hall element 1 is set to 80
Assuming 0Ω and 1 _DSS of the constant current FET 3 is 2 mA, the input voltage V _HX of the Hall element 1 is 1.6 V.
In this state, the magnetic flux density acting on the Hall element 1 becomes 100
When G (Gauss) changes, the output voltage of the Hall element 1 becomes about 4 mV. Since the output terminal voltage of the Hall element 1 is V _HX /2=0.8 V, the threshold voltage V _T of each of the amplifying FETs 3 and 4 must be It is necessary to set V _T <−0.8 V, and in this example, V _T = −1.2 V
Is set to The resistance values R _L1 and R _L of the load resistors 5 and 6
_L2 is desirably R _L1 and R _L2 ≦ 3 kΩ to reduce the influence of external noise. And each FE for amplification
Assuming that the mutual conductance of T is g _m = 10 mS, an output voltage signal of about 120 mV is obtained in the embodiment of the present invention.

When this circuit is formed into an IC, the arrangement of various circuit components is as shown in FIG. 2. By this arrangement, the wiring can be minimized and the chip area can be minimized.

FIG. 3 is a sectional view taken along line AA of FIG.

As shown in FIGS. 2 and 3, the magnetically sensitive semiconductor device has a Hall element 1 and FETs 2, 3, and 4 on a semi-insulating GaAs substrate 21. The Hall element 1 has an n-type active layer 22 formed by implanting Si in a cross shape on the surface of a GaAs substrate 21.
The active layer 22 is a layer in which carriers (here, electrons) travel, and has a carrier concentration of 10 ¹⁷ cm ⁻³ (at this time, the mobility of the carriers is about 5000 cm ^2).
/ V · sec. ). On each end of the cross of the active layer 22, there are three layers of Au—Ge / Ni / Au, respectively, and the input units 10 and 11 that make ohmic contact with the active layer 22.
And output units O ₁ and O ₂ are provided alternately.

The FET 2 includes an input section 10, a current correction section 25 provided near the input section 10, and an input section 10.
And a current correction unit 25. The current correction unit 25 is connected to the input unit 10 of the active layer 22.
It intersects with a nearby part and makes the current flowing through the input unit 10 uniform. Gate 26 is a metal-to-active layer 22
It is in semiconductor contact and controls the input current flowing through the input section 10. For example, when the left input section 11 is grounded and a positive voltage is applied to the right input section 10 in the drawing, the input current flowing between the input sections 10 and 11 is reduced by keeping the voltage applied to the gate 26 constant. Can be controlled.

FIG. 4 is a sectional view taken along line AA of FIG. 2 showing another embodiment.

This magnetically sensitive semiconductor device has a semi-insulating Ga
On the As substrate 11, one Hall element part and a HEMT part (FE
T2, 3, 4 parts). Here, HEMT (High Electron Mobility Transistor) means a field effect transistor that controls a two-dimensional carrier gas concentration at a gate.

One part of the Hall element is made of semi-insulating GaAs.
A cross-shaped mesa portion 32 is provided on the surface of the substrate 21.
The mesa portion 32 is made of GaAs by epitaxial growth.
Undoped GaAlAs layer 33, n-type G
aAlAs layer 34 and n-type GaAs layer 35 are sequentially stacked,
These layers 33, 34, 35 are formed by mesa etching. With this structure, the heterojunction interface between the GaAs substrate 21 and the undoped GaAlAs layer 33 (GaAs
On the substrate side), a two-dimensional electron gas layer 36 can be formed as an active layer. The mobility of electrons in the two-dimensional electron gas layer 36 is about 7,000 cm ² / V · sec. On each cross-shaped end of the mesa portion 32, Au-Ge / N
The input portions 10 and 11 and the output portions O ₁ and O ₂ which are composed of three layers of i / Au and make ohmic contact with the n-type GaAs layer 35 are provided alternately.

The HEMT 2 includes an input section 10, a current correction section 25 provided near the input section 10, and a gate 26 provided between the input section 10 and the current correction section 25.
Consists of The current correction unit 25 intersects a portion near the input unit 10 of the mesa unit 32 and makes the current flowing through the input unit 10 uniform. The gate 26 has an n-type GaAs layer 35
Recess groove 3 extending from the surface to the surface of n-type GaAlAs layer 34
7, the n-type GaAlAs layer 3
4 is brought into metal-semiconductor contact to control the electron concentration of the two-dimensional electron gas layer 36. For example, when the input unit 11 on the left side is grounded and a positive voltage is applied to the input unit 10 on the right side, the input current flowing between the input units 10 and 11 is connected by connecting the gate 26 to the current correction unit 25. It can be constant.

Generally, when the applied magnetic flux density is B and the magnitude of the drive current is I, the Hall voltage V _H generated by the Hall element portion is expressed as V _H = K _H IB (1). Here, K _H (called product sensitivity) is an amount determined by the physical properties and element shape of the active layer constituting the Hall element portion, and increases as the carrier mobility increases and the thickness of the active layer decreases. Become. Therefore, when the active layer constituting the Hall element portion is formed of a two-dimensional carrier gas layer, the carrier mobility of the two-dimensional carrier gas layer is the same as that of the single-layer structure shown in FIG. 3 (about 5000 cm ² / V · s).
ec). For example, GaAlAs / Ga
The mobility of electrons in the two-dimensional electron layer constituted by the As heterojunction is about 7000 cm ² / V · sec. Moreover, 2
The thickness of the two-dimensional carrier gas layer is at least one digit thinner than the active layer formed by the ion implantation of FIG. Therefore, the sensitivity to the applied magnetic field is improved as compared with that of FIG. Further, since the FET section is made of the HEMT, the switching speed is faster than that of the FET section in FIG. Therefore, the switching speed of the magnetically sensitive semiconductor device is improved.

[0028]

As described above, according to the present invention,
The output of the Hall element can be stably amplified without using a level shift diode. As a result, the manufacturing process of the diode can be omitted and the manufacturing process can be simplified. In addition, when the whole detector is integrated into an IC, the installation space for the diode is not required.
The size of the C chip can be reduced.

If the active layer constituting the Hall element section is a two-dimensional carrier gas layer and the FET section is a HEMT, the sensitivity to the applied magnetic field and the switching speed can be further improved, which is useful.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a pattern diagram in which the circuit of FIG. 1 is integrated into an IC.

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a sectional view taken along line AA of FIG. 2 showing another example.

FIG. 5 is a circuit configuration diagram showing a conventional example.

FIG. 6 is a pattern diagram in which the circuit of FIG. 5 is integrated into an IC.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Hall element 1a, 1b Output terminal 1c, 1d Current terminal 2 Constant current FET 3 Amplification FET 5, 6 Load resistance 10, 11 Power supply connection terminal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 43/06 G01R 33/07 G11B 5/37

Claims (2)

(57) [Claims] A constant current FET connected between a current terminal and a power supply connection terminal of the Hall element;
The two output terminals of the Hall element are connected to amplifying FETs whose gates are grounded, respectively.
On the output side of the ET, a resistor is connected between each of the power supply connection terminals. A hall element section is provided at the center of the square IC chip, and each amplifying FET section is provided on one diagonal side of the hall element section. A magneto-sensitive type semiconductor device, wherein a constant current FET section is arranged on one side of another diagonal line. 2. A device comprising: a Hall element; a constant current FET connected between a current terminal of the element and a power supply connection terminal;
The two output terminals of the Hall element are connected to amplifying FETs whose gates are grounded, respectively.
On the output side of the ET, a resistor is connected between each of the power supply connection terminals. A hall element section is provided at the center of the square IC chip, and each amplifying FET section is provided on one diagonal side of the hall element section. A magneto-sensitive semiconductor, wherein a constant current FET section is arranged on one side of the other diagonal line, the active layer forming the Hall element section is formed of a two-dimensional carrier gas layer, and each of the FET sections is formed of a HEMT. apparatus.