JPH02113173U - - Google Patents

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Publication number
JPH02113173U
JPH02113173U JP2163589U JP2163589U JPH02113173U JP H02113173 U JPH02113173 U JP H02113173U JP 2163589 U JP2163589 U JP 2163589U JP 2163589 U JP2163589 U JP 2163589U JP H02113173 U JPH02113173 U JP H02113173U
Authority
JP
Japan
Prior art keywords
power level
audio signal
level meter
drive means
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2163589U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2163589U priority Critical patent/JPH02113173U/ja
Publication of JPH02113173U publication Critical patent/JPH02113173U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一つの実施例に係るパワー
レベルメータの回路図、第2図は第1図の動作を
説明する線図、第3図の図1乃至4は各々第1図
中の二重対数圧縮回路の変形例を示す回路図、第
4図は第1図中のクランプ回路と表示ドライバ回
路中のバイアス回路の変形例を示す回路図である
。第5図は従来のパワーレベルメータの一部を示
す回路図である。 主な符号の説明、10:バツフア回路、20,
20A,20B,20C,20D:二重対数圧縮
回路、22,22A,22B,22C,22D:
オペアンプ、ZD,ZD1,ZD2:ツエナーダ
イオード、D10〜19:ダイオード。
FIG. 1 is a circuit diagram of a power level meter according to one embodiment of this invention, FIG. 2 is a diagram explaining the operation of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a modification of the double logarithmic compression circuit. FIG. 4 is a circuit diagram showing a modification of the clamp circuit and the bias circuit in the display driver circuit in FIG. FIG. 5 is a circuit diagram showing part of a conventional power level meter. Explanation of main symbols, 10: Buffer circuit, 20,
20A, 20B, 20C, 20D: Double logarithmic compression circuit, 22, 22A, 22B, 22C, 22D:
Operational amplifier, ZD, ZD1, ZD2: Zener diode, D10-19: diode.

Claims (1)

【実用新案登録請求の範囲】 音量コントロールより後段から取り出したオー
デイオ信号に基づき、レベル指示手段の駆動を行
うドライブ手段を備えたパワーレベルメータにお
いて、 ドライブ手段の入力側に、オーデイオ信号を二
重対数圧縮する二重対数圧縮手段を設けたこと、 を特徴とするパワーレベルメータ。
[Claim for Utility Model Registration] In a power level meter equipped with a drive means for driving a level indicating means based on an audio signal taken out from a stage subsequent to the volume control, the audio signal is input to the input side of the drive means in a double logarithm. A power level meter characterized by comprising a double logarithmic compression means.
JP2163589U 1989-02-27 1989-02-27 Pending JPH02113173U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2163589U JPH02113173U (en) 1989-02-27 1989-02-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2163589U JPH02113173U (en) 1989-02-27 1989-02-27

Publications (1)

Publication Number Publication Date
JPH02113173U true JPH02113173U (en) 1990-09-11

Family

ID=31239045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2163589U Pending JPH02113173U (en) 1989-02-27 1989-02-27

Country Status (1)

Country Link
JP (1) JPH02113173U (en)

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