JPH021129A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device using a bipolar transistor by a method wherein, according to a base potential, a base current can be flowed in a reverse direction in addition to a base current in a forward direction. CONSTITUTION:An N<+> type buried layer 22, an epitaxial silicon layer 23, an N-type well 24 and a field oxide film 25 are formed on the surface of a P<-> type silicon substrate 21. A collector extraction layer 26, a P<-> type base region 27, an N<+> type emitter region 28, an emitter polycide 29 and a P<+> type layer 30 are formed at opening parts; in addition, an N<+> type layer 31 are piled up on the surface of the collector extraction layer 26. This whole assembly is covered with a silicon oxide film 32; a collector electrode, a base electrode and an emitter electrode 35, 36, 37 composed of Al-Si 34 are formed at contact openings via a Ti/TiN film 33. Accordingly, a reverse base current, between the collector and the base, which is larger than a forward base current can flow according to a change in a base potential. Thereby, it is possible to realize a transistor whose base current has a negative region in addition to a conventional positive region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device using a bipolar transistor.

(Prior art) Conventionally, a bipolar transistor inputs base current,
It has been used as a current amplification element that outputs collector current. For example, in an NPN bipolar transistor, if a positive collector-emitter voltage VCE and a base-emitter voltage vBE (vcI!>VB+) are given, then Vs
T! For various values of , the collector current IC assumes an amplified positive value, while also the base current 1. is also correct.

(Problems to be Solved by the Invention) However, the range of application of conventional bipolar transistors is also limited due to their uniform operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device using a novel bipolar transistor that can flow a base current in the reverse direction in addition to the forward base current depending on the base potential.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a forward base current between a base and an emitter, and a reverse base current between a collector and a base.
When ICB, I BB < I depending on the base potential
The present invention provides a semiconductor device using a bipolar transistor in which the collector-emitter voltage VCE is set to be ce.

(Function) By setting the voltage between the collector and emitter to a high voltage, the forward base current between the base and emitter is
Bl! A larger reverse base current ICB can flow between the collector and the base, and a transistor can be realized in which the base current has a negative region in addition to the conventional positive region.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view of the bipolar transistor used in this example.

An N-type buried layer 22 is provided on the surface of the P-type silicon substrate 21 to reduce collector resistance, and a P-type epitaxial silicon layer 23 is further provided. Phosphorus is introduced into this P-type epitaxial silicon layer 23 and N
A mold well 24 is formed. A field oxide film 25 is formed on the surface, a collector extraction layer 26 reaching the N-type buried layer 22 is provided in the opening, and a P-type base region 27 is provided in the other opening. A part of the P- type base region 27 has an N+ layer of 24×5 μm in size.
A mold emitter region 28 is formed and an emitter polycide 29 is further provided. Also, the P-type base region 27
Inside, a P-type layer 30 is formed in self-alignment with the emitter polycide 29, and furthermore, on the surface of the collector extraction layer 26,
An N green mold layer 31 is formed overlappingly.

The entire structure is covered with a silicon oxide film 32, and collector, base, and emitter electrodes 35.36.37 made of T1-5I34 are provided in the contact openings with Ti/TiN films 33 interposed therebetween.

In manufacturing, first, a P-type silicon substrate 21 is coated with 5
The N-type buried layer 22 is formed by thermally diffusing sb at 1250° C. for 25 minutes in a B203 atmosphere. Then, 5i)1
2CI2. A P-type epitaxial silicon layer 23 was grown by treatment at 1150° C. for 10 minutes in a +B2HG atmosphere. After this, phosphorus P+ was accelerated at a voltage of 160 KeV,
Ion implantation was performed with a dose layer of 5 x 10i2cffl-'', and N was diffused at 1100°C for 290 minutes in an N2 atmosphere.
A mold well 24 was formed. and field oxide film 25
After the formation, phosphorus P+ is ion-implanted to form an N-type collector extraction layer 26, and boron B+ is further ion-implanted at an accelerating voltage of 30k.
A P- type base region 27 was formed by implanting ions at a dose of 5 x 101013a at a dose of 50 eV.After this, a thin silicon oxide film was formed on the surface, and an opening was made to cover the polysilicon by 500 layers, and arsenic As+ 60KeV.

Ions are implanted at a dose of 5.times.10"am-", and then Ho5t is deposited and patterned to form emitter polycide 29. Then, boron B+ is ion-implanted into the P◆ type layer 30. Further, arsenic As+ is ion-implanted to form an N-type layer 31. After this, a silicon oxide film 32 is deposited, a contact opening is formed, and the bottom of the contact hole is filled with Ti/
TiN33 is deposited, and AQ-3i34 is further deposited and patterned to form collector, base, emitter electrodes 35,
Form 36°37.

FIG. 3 is an impurity distribution diagram of the NPN bipolar transistor formed in this manner.

The emitter is P' with an impurity concentration of 1.5X10"am""3
Junction depth from the surface of the '' type epitaxial silicon layer 23 is 0.15.B, the base is 3 x 10''aa-''
With a junction depth of 0.3 μs and a collector well area of approximately 4XlO"01-".

FIG. 1 is a circuit diagram showing the operation of this NPN bipolar transistor 11.

Base-emitter voltage VB! , when the collector-emitter voltage is VCB, the collector current with respect to VBH.

, base current 1. is shown in Figure 4.

Figure 4 shows the values when VCE is set to 6.25V.

OV≦V a a < 0.45 V 1' is VBB (
7) Positive base current Ia flowing from the positive terminal of the power supply to the base 13 (at v86×0.87), negative base current flowing from the base 13 to the positive terminal of the power supply VBg -I B , 0.87V <VB [! Then VB again
It was found that a positive base current ra flows from the positive terminal of the power source B.

Figure 5 shows the results when VCE is set to 5.75V, and the VBt' region where the base current IB becomes negative is 0.75V.
50<Van<0.66V.

However, as shown in Figure 6, VCEI"1v
Then, no negative base current was observed in the entire vaFl(7) region (VBH≧O), and it was always positive.

As shown in FIG. 7, the above-mentioned negative base current is caused by the forward direction base current Iaa flowing from the base to the emitter (represented as IBF in the figure because it is in the forward direction) and the PN junction between the base and collector. This is explained by the magnitude relationship of the reverse base current ICB (expressed as IBR because it is in the opposite direction) between the collector and the base due to carriers generated by the avalanche multiplication phenomenon.

That is, I IaI! l> l When ICBI, the fourth
In the figure, Ov≦V a a < 0, 45 V and 0.87 V < VBI! (7) As observed in the region, the base current IB becomes positive.

When Iaal < l Ica I, 0.45V <
Negative base current −I to be am in the region of Van<0.87V.

bawl.

When electrons injected from the emitter enter the depletion region of the base-collector junction, these electrons generate electron-hole pairs by impact ionization because the collector voltage is set to be a large voltage in the direction of avalanche breakdown. Then, the generated electrons and holes drift toward the collector and the base, respectively, due to the electric field between the base and collector. The holes that drift to the base create a negative base current IBR, and the positive base current IBF from the base to the emitter is fixed at a fixed base-emitter voltage VB+! limited by. As a result, a reverse base current is observed when IBR is greater than IBF. On the other hand, when this reverse base current appears, the generated electrons will slightly add to the magnitude of the collector current because the electron current is smaller than the electron current injected from the emitter.

This will be explained below using a formula.

In the Ebars-Mail model, in a normal transistor, the collector current ICO and base current IBF are expressed by equations (1) and (2).

rco=αF I as(exp(' ””) 1
) Swamp T I cs(exp('”') 1 ) −
■T Iar=(1-ap) II! 5(exp(""")
1) T (1 (ER) IC3 (6 α
F is the fraction of current that reaches the collector out of the current that flows across the emitter-base junction.

αF represents the proportion of the current flowing across the collector-base junction that reaches the emitter.

In addition, Numa is Boltzmann's constant, T is absolute temperature, and spear is electric charge.

Furthermore, the collector-base voltage Vc [! is high and the avalanche multiplication effect at the PN junction between the base and collector cannot be ignored, the collector current IC becomes IC; MICo...■, where ICO is the collector current when the avalanche multiplication effect is ignored. The current, n is a coefficient, and BVcao represents the withstand voltage between the base and the collector when the emitter is open.

As shown in Figure 7, the holes generated by avalanche multiplication flow into the base due to the electric field, and the base current IB in the opposite direction
It becomes R.

Therefore, IBR becomes R= (M 1) ICO...■, and the base current becomes 1. Express it as the difference between the forward base current IBF and the reverse base current IBR.

IB==INF-IBR=IBF-(M-1)
IC8=(1(M-1)hpp) IBF
...becomes 0. In addition, emitter current 1. is 1. =I.

. +IBF. Here, hFE is the current gain (h
rf! = Ic.

/IBF).

Note that this operation can be similarly explained not only for NPN bipolar transistors but also for PNP bipolar transistors.

Now, bipolar transistors exhibiting such negative base current have new fields of application.

For example, a flip-flop is a conventionally known voltage holding device. However, since the flip-flop is composed of six elements, there is a problem in achieving high integration.

Now, consider the case where a capacitive load exists between the base and emitter of the bipolar transistor shown in FIG.

? At (7), the base voltage vBE is OV≦VB! <0.4
In the case of 5V, the charge accumulated in the load flows out from the base to two voltages, so the voltage Vaa across the load decreases to Ov.
, while 0.45V < Van < 0.87
When VTE is present, charge is accumulated in the load due to the reverse base current, so the voltage vBE across the load increases to 0.
87Vl:, approaching, while VBg>0.87V
1', the load's charge flows from the base to the emitter due to the positive base current, so the voltage across the load VaE
! falls and approaches 0.87V. As above, V
BE! Since it is held at Ov or 0.87V, it is possible to hold the voltage with a self-amplification function.

FIG. 8 shows an example of the voltage holding circuit.

In this embodiment, an n-channel M is used as a switching element.
An OS transistor Q□ is used, and its drain or source is connected to the base of an NPN bipolar transistor Q2.

A clock φ4 is applied to the gate of the MoS transistor Q1, and a clock φB is applied to the other end.

The capacitance in this case is the junction capacitance between the base and the emitter, and the junction capacitance between the collector and the base also functions as a load capacitance.

FIG. 9 shows the groove forming clock φA of the MOS transistor Q1.
, input clock φB, and MOS transistor Q1
and shows the voltage level of the output terminal provided at the connection node of bipolar transistor Q2. V is 0.87
V and Vp are 0.45V, and VL is OV.

φA becomes high level, and the base becomes φ, )0. l17V
When φA becomes low level, the high level voltage applied to the base is discharged by the positive base current and settles to 0.87V. Then 0.45V to the base
When <φa<0.87V is applied, the output potential increases to 0.87V due to the negative base current. When φe<0.45V is applied to the base, the positive base current converges to Ov.

If φa>0.45V (7), the boundary potential is 0
．． Holds 87V and outputs φB (0.45V, O
It becomes possible to hold and output V.

This means that one circuit can be used as a voltage holding circuit in place of a flip-flop with a small number of elements.

This is because a negative current is generated in the base current, and as shown in Figure 6, when the collector-emitter voltage vcg = IV, the base current is positive for all VBH, so the discharge mode As a result, voltage cannot be maintained.

In FIG. 9, the connection node between the MoS transistor Q1 and the bipolar transistor is used as the output terminal.

After holding, turn on MOS transistor Q□ again and φB
The input terminal can also be used as the output terminal.

In FIG. 10, a capacitive element C such as a MOS capacitor is connected to the connection node in addition to the bipolar transistor, and this capacitive element is used to actively perform the charging and discharging.

In this case, the input end of φB is also used as the output end, but the output end may be placed at the connection between the bases of Ql and Q2.

As mentioned earlier, the present invention can of course be applied to PNP bipolar transistors.

FIG. 11 is an example of this, and shows the case of a PNP bipolar transistor corresponding to FIG.

In this case, the collector-emitter voltage V. I! When is a predetermined negative voltage (-V volts), as shown in FIG. 12, a negative base current - with respect to the base-emitter voltage vBu
Can play IB.

When a PNP bipolar transistor is applied to a voltage holding circuit, a negative voltage can now be held, as understood from FIGS. 10 and 11.

The voltage holding circuit explained above is a latch circuit, base i1! It can be applied to potential generation circuits and memories such as SRAM. Furthermore, oscillation circuits, sense amplifiers, and switching circuits can be constructed using bipolar transistors that exhibit negative base current.

FIG. 13 is a circuit diagram illustrating another embodiment of the present invention.

The input potential vxN is input to the first node, which is the base of the first NPN bipolar transistor TRI, and its emitter is connected to the base of the second NPN bipolar transistor TR2, and the output potential Vour is set as the second node. is observed.

Collector potentials VCC□ and VCC of TRI and TR2, respectively
Output V for input potential V when z is set to 8 V
The relationship of OUT is shown in FIG.

The relationship between the base current IB and collector current IC with respect to the base-emitter voltage VBH of TR2 in this example is shown in the 15th section.
Shown in the figure. Here, a transistor TR2 manufactured using exactly the same process parameters as the bipolar transistor explained in FIG. 2 was used. In addition, in this example, TRI
Also, using a transistor manufactured with exactly the same process parameters as TR2, −V CCx = V CCz = 8
It was set to V.

TRI functions as a charging means, and as VZ= is increased from Ov, V OUT becomes TRI as shown by the solid line in Figure 14.
Emitter current of 1. The difference between the positive base currents of TR2 and TR2 increases while taking a potential at which the difference becomes zero (I CB+I B=I nE). However, as shown in Figure 15, lc
o, 46V<Vaa<1.22V TR2 (7) Since the reverse base current is larger than the forward base current, in the circuit shown in Fig. 13, VOUT is around 0.46 (
The battery enters charging mode at the time of V engineering N=o and siv (vl). At this time, the base, emitter junction and base of TR2.

The junction capacitance of the collector junction becomes V due to charging. LIT is v2
It rises sharply to (,1,22V). Here, in the circuit of FIG. 13, the emitter current is actually 1. Flows in Figure 14 (') V 1- V * is the above ICB+
II! = voltage that satisfies IBEI, IQ in Figure 15
The boundary potential between -IQ and -IQ takes values near 0.46V and 1.22V. The arrows shown in the characteristic diagram in the figure are the characteristics when increasing VIN and then decreasing VIN.
V when IN is raised to a region greater than 0.81 V. L
IT is latched to v2.

That is, this circuit can be used for memory, voltage detection circuits, and A/D conversion circuits.

When voc2 is set to 1V, no reverse base current appears in TR2, so as shown by the dotted line in Figure 14,
vout changes continuously for vxN, and V OUT
No sharp changes are observed.

FIG. 16 shows an embodiment in which a resistive element is inserted between the base and emitter of TR2 in FIG. 13.

FIG. 17 shows the input/output characteristics when R connected between the base and emitter of TR2 in FIG. 16 is set to IMΩ.

By using the above-mentioned resistor R, the absolute amount by which VOUT changes sharply, as shown in Figure 17 compared to Figure 14, is reduced from 0.76 (=1.22-0.46) V when resistor R is not included. If R is included (7) 0.44 (=1.20-0.7
6) V4: Can be changed and the VIN at that time
The value of can be changed from 0.81V to 1.31V.

FIG. 18 shows an example in which a capacitive element C is inserted between the base and emitter in FIG.
The time constant of uT is changed.

TRI in the above embodiment has the same reverse base current characteristics as TR2. However, the function of TRI may be such that the emitter current IE increases with respect to an increase in VIN. TRI is effective even if it is a normal NPN bipolar transistor that lowers the collector-emitter voltage VCB and does not exhibit a negative base current, as shown in FIG.

Furthermore, instead of TRI, it is also effective to connect an M○S transistor TR3 as shown in FIG. 19 or a diode D1 as shown in FIG. 20. At this time, TR3 is an n-type MO
It may be an S transistor or a P-type MOS transistor.

Further, the above resistance element R is made of high resistance polysilicon, MO
The capacitive element C can be formed by an S transistor, a bipolar transistor, etc., and the capacitive element C can be formed by a MoS capacitor, a PN junction capacitor, etc.

In the above embodiment, NPN bipolar transistors were used for both TRI and TR2, but as shown in FIG.
PNP bipolar transistors can also be used.

In this case, VCC and VC have a negative voltage, for example 8V.
When VIN is also given a negative voltage, from VOUT,
A negative potential change is output.

Next, as shown in FIG. 22, V 0LJT and VSS
The present invention is effective even when a PNP transistor TR3 is added between the two. The input/output characteristics in Figure 22 are shown in Figure 23.
As shown in the figure. If VIN in Figure 22 is gradually increased from Ov, the input/output characteristics will become as shown in Figure 23 (■) @VI
When the high level of N is VIN<Vxu, when VXN is gradually lowered from the high level, the input/output characteristics return to the trajectory shown by ■ in FIG. 23, as in the previous embodiment. Also, VIN (7
) When the high level is V zH (7), when vxN is gradually lowered from the high level, the input/output characteristic becomes a hysteresis characteristic as shown by ■ in FIG. In this way, if the L level of vxN is modified by VIN and the H level is used as V IL N > V IH, the second
The circuit shown in FIG. 2 works as a Schmitt trigger circuit.It will be explained below. As shown in Figure 15, VCE
= 8V (Vcct = VCCz = 8V)
, between VB = 0.46V and 1.22V (7), TR2 is a negative base current -I as shown by the dotted line.
B flows, otherwise a positive base current I as shown by the solid line
B flows.

It is shown in FIG. 24(a). VBII when VrN=OV(7) of transistor circuits TR1 and TR3 in FIG. 22!
The characteristics of the current at the connection between TRI and TR3 for
Shown in Figure (b). TRI functions as a charging means, and TR3 functions as a discharging means as described later. VB
When Fi is lower than VIN (= OV), that is, when it is negative, one IO shown by the dotted line flows due to the emitter current of transistor TRI, and vB[! When is positive, the process 0 shown by the solid line due to the emitter current of transistor TR3
flows. The characteristics shown in Fig. 23 are the same as those shown in Figs. 15 and 24 (b
) by combining.

This can be explained as shown in FIGS. 25(a) to 25(d).

Here, (a) to (d) in Fig. 25 are respectively shown in Fig. 23.
It is a figure explaining the state of (a) to (d) of a figure. In addition, in FIG. 25, the dotted line indicates the base of TR2, that is, V
The solid line indicates the current in the direction of charging the OUT terminal, and the current in the direction of discharging the base of TR2. Therefore, v
outT will stabilize at a potential where the total current charging the base of TR2 and the total current discharging it are equal in magnitude.

Figure 25 (a) shows that VXN is raised from OV to 0.4
VO with respect to the base potential VBE of TR2 when set to V
These are the characteristics of each current flowing in and out of the LI block. VIN=Ov
When VIN is increased, voUT is at Ov, and as shown in FIG. The voltage increases as the potential becomes equal. However, when VIN=0.76V is exceeded, as shown in FIG. 25(b), Vat! is from Ov,
At any value up to 1.22V, current flows in the direction of charging, so VBB rises steeply and reaches 1.22V.
It stabilizes and becomes voUT. If you further increase vrN,
The stable potential vouT continues to rise at the point where the total current in the charging direction becomes equal to the total current in the discharging direction, and as shown in FIG.
a>, when VIN=2V, VOUT=1.3
6 Next, when vIN is lowered from 2v, V
OUT goes down at a potential where the total current in the charging direction and the total current in the discharging direction are equal. Figure 25(d) D is vI
The state when N=0.3v is shown.

Here, current IO due to the emitter of transistor TR3
acts to cancel the negative base current of the TR2 transistor. Therefore, if there is no transistor TR3, even if VXN is lowered to Ov, VOUT is latched at 1.22V as shown in (e) in FIG. 26, and VOt1 = OVt does not drop. When vIN is further lowered from 0.3v and Vzs=0.1V or less, - in Fig. 25(d).
As shown by the dotted chain line, IQ deviates from the negative base current -■, and reaches the potential where the total current in the charging direction and the total current in the discharging direction are equal, that is, the potential where the base current IB on the low level side changes from -Io. descends steeply. This steep decline is TR
By changing the base potential of 3, the emitter current 1. This is nothing more than making the magnitude of the negative base current −K8 larger than the magnitude of the negative base current −K8 by changing the current. That is, the discharge transistor TR3 is latched at 1.22V.
By controlling the base potential of TR2 so that TR3 has Io (discharge current) larger than the absolute value of the negative base current -In of TR2, the latch level can be reset.

In addition, as another example of FIG. 22, as shown in FIG. 27, when TRI in FIG. 22 is replaced from an NPN bipolar transistor to an N-type MOS transistor, and TR3 is replaced from a PNP bipolar transistor to a P-type MOS transistor, also exhibits similar characteristics.

FIG. 28 shows another embodiment used in a Schmitt trigger circuit. FIG. 29 shows an example of a Schmitt trigger circuit using pnp bipolar transistors. In this circuit, as shown in FIG.
Both T operate at a negative potential.

FIG. 31 shows an embodiment in which negative base current is eliminated by changing the value of Vc.

FIG. 32 shows the operation. vH=1.4v from vIN
When input through the switching element of the n-type MOS transistor, V outT is latched to 1.22 V, which is the boundary potential between the positive and negative base currents on the high level side. However, by changing vc from 8v to Ov, 1. Since there is no longer a positive base potential through which a negative base current flows, vOUT drops from the latched 1.22V.
It falls from Ov. This can be used as a reset function for memory devices and the like.

〔Effect of the invention〕

According to the present invention, a completely new semiconductor device using a reverse base current can be provided.

[Brief explanation of the drawing]

Fig. 1 is an operational circuit diagram using an NPN bipolar transistor, Fig. 2 is a cross-sectional view of the bipolar transistor, Fig. 3 is a diagram showing its impurity profile, and Fig. 4 is a Vc
Figure 5 shows the base current when E=6.25V, Figure 5 shows the case when VcE=5.75V, Figure 6 shows ■c11
! =1. 7 is a diagram for explaining its operation; FIG. 8 is a diagram for explaining its application to a voltage holding circuit; FIG. 9 is a diagram for explaining its operation; FIG. 10 is a diagram for explaining its operation.
The figure shows another example. Figures 11 and 12 are diagrams explaining the case of PNP bipolar transistors. Figures 13, 14, 15, 16, 17, and 18. , FIG. 19, FIG. 20, and FIG. 21 are diagrams for explaining other embodiments, FIG. 22, and FIG. 23. Figure 24, Figure 25, Figure 26, Figure 27, Figure 28,
FIG. 29 and FIG. 30 are diagrams showing still other embodiments, and FIG.
32 are diagrams showing other embodiments. Agent: Patent Attorney Noriyuki Ken Yudo Mitsuyuki Matsuyama Diagram base, 1 min.
8E () 111m Pace, emic relaxation pressure BE () Fig. 12 Fig. 1O Fig. V ('C/ Fig. 13 IH [v) Fig. 14 Base, work ξ 1, 7 ■ Electric loaf 8E ( ] Fig. 15 cct Fig. 18 cct Fig. 21 Fig. 20 BE (] Fig. 24 (α) Fig. 25 (b) (ct) Fig. 25 (C) Fig. 26 Fig. 27 Fig. 28 Fig. 29 Figure 30

Claims (19)

[Claims] (1) Forward base current between base and emitter is I_B
_E, reverse base current between collector and base is I_C
When _B, I_B_E<I_C depending on the base potential
Collector-emitter voltage V_C_E so that _B
1. A semiconductor device characterized by using a bipolar transistor configured with . (2) The semiconductor device according to claim 1, wherein I_C_B is an avalanche multiplication current. (3) The semiconductor device according to claim 1, wherein the bipolar transistor is an NPN transistor. (4) The semiconductor device according to claim 1, wherein the bipolar transistor is a PNP transistor. (5) Forward base current between base and emitter is I_B
_E, reverse base current between collector and base is I_C
When _B, I_B_E>I_C depending on the base potential
1. A semiconductor device using a bipolar transistor in which a collector-emitter voltage V_C_E is set so that two states, _B and I_B_E<I_C_B, exist and the polarity of the base current is reversed accordingly. (6) Forward base current between base and emitter is I_B
_E, reverse base current between collector and base is I_C
When _B, I_B_E<I_C depending on the base potential
1. A semiconductor device comprising: a bipolar transistor _B; and a switching element connected to the base of the bipolar transistor. (7) Claim 6, wherein a capacitive element is provided at the connection between the base of the bipolar transistor and the switching element.
The semiconductor device described. (8) The semiconductor device according to claim 6, wherein the switching element is a MOS transistor. (9) Forward base current between base and emitter is I_B
_E, reverse base current between collector and base is I_C
When _B, I_B_E>I_C depending on the base potential
1. A semiconductor device characterized in that two states exist: _B, I_B_E>I_C_B, and a base potential is held at a boundary potential between both states. (10) A bipolar transistor, a switching element provided between a base and an input of the bipolar transistor, and a capacitive element provided at a connection between the base and the switching element, wherein the voltage between the base and the emitter is The collector-emitter voltage is set to a high voltage so that the polarity of the base current changes as the base current increases, and when the input potential is within a predetermined range, the polarity of the base current changes after the switching element is turned off. A semiconductor device characterized in that a base potential converges to a potential, and when an input potential is in another range, converges to a potential different from the converging base potential. (11) The semiconductor device according to claim 10, further comprising an output section provided at a connection between the base of the bipolar transistor and the switching element. (12) The semiconductor device according to claim 10, wherein the input section is also used as an output section. (13) A first bipolar transistor whose base is an input, and a second bipolar transistor whose base is connected to the emitter of the first bipolar transistor and whose output is the emitter. , the forward base current between the base and emitter is I_B_E, and the reverse base current between the collector and base is I_C_B. A semiconductor device characterized by having a set voltage between the two. (14) It is equipped with a diode connected to its input, and a bipolar transistor whose base is connected to the other end of this diode and which serves as an output.This bipolar transistor has a forward base current between its base and emitter that is
_B_E, the reverse base current between collector and base is I
1. A semiconductor device characterized in that, when _C_B, a voltage between a collector and an emitter is set so that I_B_E<I_C_B according to a base potential of a bipolar transistor. (15) It is equipped with a MOS transistor whose gate is input, and a bipolar transistor whose base is connected to this MOS transistor and whose output is output. , a semiconductor device characterized in that, when a reverse base current between the bases is I_C_B, a voltage between a collector and an emitter is set so that I_B_E<I_C_B according to a base potential of a bipolar transistor. (16) comprising a charging means and a bipolar transistor whose base is connected to the charging means and whose output is the bipolar transistor;
When the forward base current between the base and emitter of this bipolar transistor is I_B_E, and the reverse base current between the collector and base is I_C_B, I_B_E<I_
A semiconductor device characterized in that a voltage between a collector and an emitter is set to be C_B. (17) A charging means, a bipolar transistor whose base is connected to the charging means and which outputs the bipolar transistor, and a discharging means connected to the base, and this bipolar transistor has a forward base between its base and emitter. When the current is I_B_E and the reverse base current between the collector and base is I_C_B, the voltage between the collector and emitter is set so that I_B_E<I_C_B according to the base potential of the bipolar transistor, and the charging means writes. A semiconductor device characterized in that a latch potential of a loaded base is reset by the discharge means. (18) I_C_B- in I_B_E<I_C_B
Claim 17 characterized in that the reset is performed by controlling the discharging means to flow a current larger than the value of I_B_E.
The semiconductor device described. (19) comprising an input means and a bipolar transistor whose base is connected to the input means and which outputs the input means;
When the forward base current between the base and emitter of this bipolar transistor is I_B_E, and the reverse base current between the collector and base is I_C_B, I_B_E<I_
A semiconductor device characterized in that a collector-emitter voltage is initially set to be C_B, and a base latch potential written by the input means is reset by changing the collector-emitter voltage.