JPH02112038A - Reset signal generation circuit - Google Patents

Abstract

PURPOSE:To dissolve a runaway state in a short time by detecting the occurrence of the runaway of a CPU by monitoring the period of trigger signals outputted from the CPU at a fixed period when the CPU operates normally. CONSTITUTION:Trigger signals (f) having a fixed period T0 are inputted to a reset signal generation circuit 19 from the trigger output port TP of a CPU 5. The period T0 of the trigger signals (f) maintains a fixed value while the CPU 5 operates normally. When the CPU 5 makes a runaway for some reason, the runaway is detected by a trigger type multivibrator 19a and a reset signal having a specified pulse width Ts is impressed upon the CPU 5 from a monostable circuit 19b. As a result, the CPU 5 is cleared and the runaway state is released. When the reset state is canceled, the CPU 5 automatically returns to the normal operating state. Therefore, the runaway state of the CPU 5 can be dissolved automatically in a short time and, in addition, the CPU 5 can automatically return to the normal operating state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a reset signal generation circuit, and particularly to a CPU
The present invention relates to a reset signal generation circuit that automatically generates a reset signal to stop a CPU from running out of control when a (Central Processing Unit I) runs out of control.

[Prior Art] For example, in a terminal device equipped with a microcomputer that operates based on commands from an external host combinator, such as a printing device, the operating state of the microcomputer is checked when the terminal device is started up. It is necessary to return to the initial state. To return to this initial state, it is necessary to apply a reset signal to the CPU (central processing unit) of the microcomputer.

Generally, a reset signal generating circuit for applying a reset signal to the CPU of such a terminal device is configured as shown in FIG. 4, for example. That is, the method for applying the reset signal is to apply an external reset signal a from the host computer via the interface 1, or to apply a power supply reset signal A synchronized with the rise of the power supply from the power supply circuit 2. Actually, no matter which reset signal a or b is input using the gate circuit 3,
The circuit configuration is such that a CPU reset signal is applied to the CPU 4.

[Problems to be Solved by the Invention] However, the set signal generating circuit configured as shown in FIG. 4 has the following problems.

That is, once the CPU 4 starts operating normally, during the normal operation period, the control of the program may become inoperable due to noise or the like, and the CPU 4 may fall into a runaway state. (If the PU4 goes out of control, for example in a printing device, there is a concern that the carrier motor will stop rotating or the paper feed motor will not stop. Conventionally, when such a situation occurs, There is a method of applying the external reset signal a again from the host computer or cutting off the power to forcibly stop the operation of the entire terminal device, then turning on the power again and applying the power reset signal A. He had been hired.

But CPU! If the reset signal C is applied to the CPU using this method when the CPU is running, if there is no operator near the terminal device and the CPU runaway is discovered late, the runaway state will continue for a long time until the power is shut off. There is a problem that the terminal device itself may be damaged.

Furthermore, even when applying the external reset signal a from the host computer, if the host computer does not have a function to immediately detect an abnormal situation in the terminal device,
The application timing of the external reset signal a is delayed, causing the same problem as when the power is cut off.

The present invention detects the occurrence of CPU runaway by monitoring the cycle of a constant cycle trigger signal output from the CPU during normal operation, and can automatically apply a CPU reset signal when runaway occurs, thereby preventing the runaway state. It is an object of the present invention to provide a reset signal generating circuit that can resolve the problem in a short time and automatically return to the original state, and can further prevent damage to the entire device.

[Means for Solving the Problems] In order to solve the above problems, in the reset signal generation circuit of the present invention, the CPU (Central Processing Unit)
A trigger signal monitoring circuit that receives a trigger signal with a certain period output from the circuit and outputs an abnormal signal when this period falls outside of the allowable range, and a trigger signal monitoring circuit that receives the abnormal signal output from this trigger signal monitoring circuit and It is equipped with a monostable circuit that creates a reset signal having a pulse width and sends it to the CPU.

[Operation] In the reset signal generation circuit configured in this way,
When the CPU is operating normally, the trigger signal output from the CPU has a constant cycle, so no abnormal signal is output from the trigger signal monitoring circuit.

Further, when the CPU goes out of control, the period of the output trigger signal becomes undefined, and therefore falls outside the allowable range, and an abnormal signal is output from the trigger signal monitoring circuit. A reset signal having a specified pulse width is then applied to the CPU, and the runaway state of the CPU is released.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a schematic configuration of a printing device incorporating the reset signal generating circuit of the embodiment.

In other words, 5 in the figure is a CPU that executes various information calculation processes.
A ROM 7. which stores a control program is connected to the CPU 5 via a pass line 6. A character generator 8 for converting input character codes into dot character patterns, a RAM 9 for storing various variable data such as input character codes, and various information such as character codes and external reset signals from an external host computer 1o. It drives and controls an input interface 11, an operation panel 12 equipped with various operation switches including a power switch, various sensors 13 such as a print head home position sensor, and various motors 14 such as a carrier motor and a paper feed motor. A motor drive circuit 15, a head drive circuit 17 for driving a print head 16 that prints out dot characters, and the like are connected.

Further, each drive voltage VC+''D is supplied from the power supply circuit 18 to each of the above-mentioned electronic components.

19 in the figure is a reset signal generation circuit, and this reset signal generation circuit 19 includes a host computer 10.
An external reset signal d is sent from
is inputted, and at the same time, a power supply reset signal e is inputted from the power supply circuit 18. Furthermore, this reset signal generation circuit 19 receives a constant period T from the trigger output port TP of the CPU 5. A trigger signal f is input. Note that the period To of the trigger signal f maintains a constant value while the CPU 5 is operating normally. In addition, the CPU 5 is connected from the reset signal generation circuit 19 to the reset terminal R of the CPU 5.
A reset signal g is sent out.

The reset signal generating circuit 19 is configured as shown in FIG. That is, the trigger signal f output from the trigger output port TP of the CPU 5 is input to the trigger input terminal of the retrigger type multivibrator 19a as a trigger signal monitoring circuit in the reset signal generation circuit 19. As is well known, in this retrigger type multivibrator 19a, when a single trigger signal is input to the input terminal of the trigger, the output signal is changed to H level and at the same time, the built-in timer is activated. If the next trigger signal is not input within a preset allowable time TA, the output signal is inverted to L level.

Therefore, as long as the trigger signal f is continuously input within the permissible time TA, the output signal f maintains the H level. In this embodiment, the allowable time TA is set to be significantly longer than the period To of the trigger signal f.
As long as the trigger signal f is continuously outputted from the CPU 5 at a constant period To, the output signal R maintains the H level.

The output signal of the retrigger type multivibrator 19a is input to the input terminal of the next monostable circuit 19b. When the signal level at the input terminal falls from the H level to the L level, the monostable circuit 19b changes the output signal from the H level to the L level for a predetermined time TS from the falling time. That is, an internal reset signal i having a specified pulse width Ts is created. And this monostable circuit 1
The internal reset signal i created in step 9b is input to one input terminal of a gate circuit 19c having three input terminals.

The external reset signal d and the power supply reset signal e are input to the remaining two input terminals of the gate circuit 19c. That is, the reset signal d, e, i is applied to any one of the three input terminals of the gate circuit 19c.
is input, the reset signal is sent from the output terminal to CP
The U reset signal g is outputted and applied to the reset terminal R of the CPU 5.

Next, the reset signal generation circuit 19 configured as described above will be explained.
The operation will be explained using the time chart of FIG.

If the host computer 10 is already in operation,
When the power supply circuit 18 is powered on at time to, a power supply reset signal e is input from the power supply circuit 18 to the L level for a specified time T9, and the power supply reset signal e is outputted from the power supply circuit 18 to the C level via the gate circuit 19c.
It is applied to the reset terminal R of the CPU 5 as a PU reset signal g.

Thus, the CPU 5 is reset. And time 1
When the reset is canceled at 1, the CPU 5 starts normal operation. At the same time, a trigger signal f having a constant period To is started to be output from the trigger output port TP. trigger signal f
As long as the period 'ro is within the allowable time TA, the output signal of the retrigger type multivibrator 19a maintains the H level, so the internal reset signal i is not output from the monostable circuit 19a.

Then, when an external reset signal d having a specified pulse width Ts is input from the host computer 10 at time t2, a CPU reset signal g is sent from the gate circuit 19c, so that the CPU 5 is reset. therefore,
During the reset period (T5s111t2-t3), the trigger signal f is not output.

However, the specified time Ts of the reset signal g is the allowable time T^
Since it is shorter, the output signal of the retrigger type multi-bye break 19a does not change to L level. Therefore, the internal reset signal i is never output from the monostable circuit 19b. When the reset period Ts ends, the CPU 5 starts normal operation again and resumes outputting the trigger signal f.

However, if the CPU 5 starts to run out of control at time t4 due to some factor including noise, the output of the trigger signal f is interrupted, but at time t5 when the allowable time TA has elapsed since the output stopped.
At this point, the output signal of the retrigger type multivibrator 19a changes to L level. That is, an abnormal signal is output. As a result, the monostable circuit 19b is activated, and an internal reset signal i having a specified pulse width Ts is output, and is passed through the gate circuit 19C as the CPU reset signal g.
It is applied to the reset terminal R of PU5. As a result, C.P.
U5 is reset and the runaway state is released. and,
When the reset state is released at time t6 after the specified time Ts has elapsed, the CPU 5 starts operating normally again. Then, the output of the signal f is resumed normally.

If the reset signal generation circuit is configured in this way,
As shown in FIG. 3, when the CPU 5 goes out of control for some reason, the runaway state is detected by the retrigger type multivibrator 19a, and a reset signal having a specified pulse width Ts is sent from the monostable circuit 19b. is applied to the CPU 5. Therefore, the CPU 5 is cleared and the runaway state is released. Then, when the reset state is released, C
PU5 automatically returns to normal operating state.

That is, when the CPU 5 goes out of control, it is automatically reset, and after the runaway is released, it automatically returns to the original normal operating state. Therefore, with the CPU reset signal C in the conventional circuit shown in FIG. 3, there is no way to automatically stop the runaway state starting at time t4, but with the CPU reset signal g of the embodiment, It can be understood that the state is automatically released.

Therefore, even if there is no operator near the printing device in which this circuit is installed, the runaway state of the CPU is automatically released, thereby preventing damage to the device.

Note that the present invention is not limited to the embodiments described above. In the embodiment, the retrigger type multivibrator 19a is used as the trigger signal monitoring circuit, but for example, a watchdog timer may be used.

[Effects of the Invention] As explained above, according to the reset signal generation circuit of the present invention, occurrence of runaway of the CPU is detected by monitoring the cycle of the trigger signal with a constant cycle output from the CPU during normal operation. , a reset signal having a specified pulse width is applied to the CPU. Therefore, even if a runaway occurs in the CPU, the runaway state can be automatically resolved in a short time.
And it can automatically return to its original normal state. Furthermore, damage to the entire device can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a reset signal generation circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a printing device incorporating the circuit of the embodiment, and FIG. 3 is a block diagram of the circuit of the embodiment. A time chart showing the operation, FIG. 4 is a diagram showing a conventional reset signal generation circuit. 7 5...CPU, 10...Host computer, 11
...Interface, 18...Power supply circuit, 19.
...Reset signal generation circuit, 19a... Retrigger type multivibrator, 19b... Monostable circuit, 19c...
...Gate circuit, d...External reset signal, e...
Power supply reset signal, f...Trigger signal, g...CP
U reset signal. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A trigger signal monitoring circuit that receives a trigger signal with a fixed cycle output from a CPU (central processing unit) during normal operation and outputs an abnormal signal when the cycle falls outside of an allowable range, and an output from this trigger signal monitoring circuit. a monostable circuit that receives an abnormal signal generated by the CPU, generates a reset signal having a specified pulse width, and sends it to the CPU.