JPH02111263A - Full-wave voltage multiplying rectifier circuit - Google Patents

Full-wave voltage multiplying rectifier circuit

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Publication number
JPH02111263A
JPH02111263A JP26516288A JP26516288A JPH02111263A JP H02111263 A JPH02111263 A JP H02111263A JP 26516288 A JP26516288 A JP 26516288A JP 26516288 A JP26516288 A JP 26516288A JP H02111263 A JPH02111263 A JP H02111263A
Authority
JP
Japan
Prior art keywords
rectifier
connection point
capacitor
full
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26516288A
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Japanese (ja)
Inventor
Takamasa Mitsuya
高正 三ツ矢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichicon Corp
Original Assignee
Nichicon Corp
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Filing date
Publication date
Application filed by Nichicon Corp filed Critical Nichicon Corp
Priority to JP26516288A priority Critical patent/JPH02111263A/en
Publication of JPH02111263A publication Critical patent/JPH02111263A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To lower the ripple of output voltage by ensuring a full-wave rectification system and simply conducting extension to polyphase. CONSTITUTION:The pump-up of the storage charges of a capacitor by the valve action of a diode is utilized in the same manner as a Cockcroft circuit. The two capacitor rows of capacitors C11, C12, C13 and C21, C22, C23 connected at both ends of an AC power (e) alternately fill the roles for drive and for storing charges at every half wave of the AC power (e) by the action of diodes D10, D20 in the voltage multiplying rectifier circuit of a single-phase AC power. Accordingly, full-wave rectification is acquired, and each positive and negative half wave is symmetrized in the current waveform of the AC power (e).

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、単相または多相交流電源から全波電圧逓倍整
流して直流高電圧を得る回路に関するもので、直流高電
圧電源一般、フラッシュランプ点燈装置、着磁装置など
のコンデンサ充電回路に利用する全波電圧逓倍整流回路
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a circuit that obtains a high DC voltage by performing full-wave voltage multiplication rectification from a single-phase or polyphase AC power supply, and is useful for general DC high-voltage power supplies, flash lamp points, etc. This invention relates to a full-wave voltage multiplication rectifier circuit used in capacitor charging circuits for lighting devices, magnetizing devices, etc.

従来の技術 第8図に示すコツククロフト回路に代表される単相電圧
逓倍整流回路はよく知られているが、半波整流のために
出力電圧リップルが大きい、入力交流電源の電流が正と
負の半波で対称にならないなどの不都合があり、これを
改善するために第9図に示す対称形コツククロフト回路
とすることにより二相半波整流として、出力電圧リップ
ルの低減とトランスTの1次電流の対称化を図っていた
Conventional Technology Single-phase voltage multiplier rectifier circuits, such as the Kotskucroft circuit shown in Figure 8, are well known, but due to half-wave rectification, the output voltage ripple is large, and the current of the input AC power source is polarized between positive and negative. There are disadvantages such as the lack of symmetry in half waves, and to improve this, a symmetrical Kotscroft circuit shown in Figure 9 is used as a two-phase half-wave rectifier, reducing the output voltage ripple and reducing the primary current of the transformer T. The aim was to make the structure symmetrical.

第8図および第9図において、eは交流電源、Cia、
 Cib、 Cic、 C2a、 C2b、 C2c、
 C3a、C3b、 C3cはコンデンサ、DI 、D
la、 Dlb、D2、D2a、、D2b、、D3、D
3a、、D3b1D4、D4a。
In FIGS. 8 and 9, e is an AC power source, Cia,
Cib, Cic, C2a, C2b, C2c,
C3a, C3b, C3c are capacitors, DI, D
la, Dlb, D2, D2a,, D2b,, D3, D
3a,,D3b1D4,D4a.

D4b、 D5 、D5a、 D5b、 D6.D6a
、 D6bは整流器、Rは負荷抵抗、HV、LVは出力
端子である。
D4b, D5, D5a, D5b, D6. D6a
, D6b is a rectifier, R is a load resistance, and HV and LV are output terminals.

発明が解決しようとする問題点 しかし、上記の電圧逓倍整流回路は、出力電圧を低リッ
プル化あるいは交流入力電流の正負対称化しようとする
と、トランスの2次巻線のセンタータンプ化、コンデン
サとダイオードの数量増加、これに伴う回路の複雑化な
どの欠点があった。
Problems to be Solved by the Invention However, in the above-mentioned voltage multiplier rectifier circuit, in order to reduce the ripple of the output voltage or to make the positive and negative polarity of the AC input current symmetrical, it is necessary to center-tamp the secondary winding of the transformer, and to use capacitors and diodes. There were disadvantages such as an increase in the number of circuits and an accompanying increase in the complexity of the circuit.

問題点を解決するための手段 本発明は上記の欠点を除去した全波電圧逓倍整流回路で
、その特徴は全波整流式であることおよび多相化への拡
張が簡単に行うことができるから容易に出力電圧を低リ
ップル化できる特徴がある。
Means for Solving the Problems The present invention is a full-wave voltage multiplier rectifier circuit that eliminates the above-mentioned drawbacks, and its characteristics are that it is a full-wave rectifier type and that it can be easily expanded to multiphase. It has the feature that the output voltage can be easily reduced to low ripple.

以下、本発明の回路構成を単相および多相交流に対応で
きる一般的表現で記述する。
Hereinafter, the circuit configuration of the present invention will be described in general terms that can support single-phase and multi-phase alternating current.

単相または多相交流電源の給電線数をm(ただし、m≧
2)、逓倍整流回路段数をnとし、各給電線番号をi 
 (i=1.2.3−−−−−−−m)とする給電線i
からコンデンサをCiいC4z、Ci3C4L  −−
−−一−Cin (i = 1% 2.3、m)の順に
n個ずつ直列接続し、給電線iとコンデンサCi,の接
続点をio3コンデンザCijとCi(j+1) (i
 = 1.2.3−−−−−− m、j=1.2.3 
”−−−−−−n−1)の接続点をij、 mlンデン
サCinの出力側端子をinとし、給電線数回=2の場
合は接続点1(j−1)と接続点2jの間に整流器D2
ja(j = 1.2.3−−一=−n)を接続すると
ともに接続点2(j−1)と接続点1jとの間に整流器
D1jb(j = 1.2.3−−n)をそれぞれ接続
し、給電線数回≧3の場合は接続点(i−1) (j−
1)と接続点ijの間に整流器Dija(i=2.3 
     mX j=1.2.3n)および接続点m(
j4)と接続点1jとの間に整流器Dlja(j = 
1.2.3 −−−−− n)を接続するとともに接続
点(n+1) (j−1)と接続点ijO間に整流器D
ijb(+ = 1.2.3−−−−−一−−m−1、
j=1.2.3−・−−n)および接続点l (j−1
)と接続点mjの間に整流器Dmjb(j = 1.2
.3 −−−一−−・−n)をそれぞれ接続し、接続点
io (i=1.2.3〜−−−− m)の各々から整
流回路の出力端子の一方に整流器Dioを、接続点in
 (i=1.2.3−−−−−m)の各々からもう一方
の整流回路の出力端子に整流器Di(n+1)をそれぞ
れ接続し、上記すべての整流器の向きを負荷電流を供給
する向きに順方向としたことを特徴とする全波電圧逓倍
整流回路である。
The number of feeder lines for single-phase or polyphase AC power supply is m (however, m≧
2), the number of stages of the multiplier rectifier circuit is n, and each feeder line number is i.
(i = 1.2.3------m)
Ci C4z, Ci3C4L ---
--1-Cin (i = 1% 2.3, m) are connected in series in the order of n pieces, and the connection point between the feeder line i and the capacitor Ci is connected to the io3 capacitor Cij and Ci (j+1) (i
= 1.2.3--- m, j=1.2.3
The connection point of "----n-1) is ij, the output terminal of the ml capacitor Cin is in, and if the number of feed lines = 2, the connection point of connection point 1 (j-1) and connection point 2j is Rectifier D2 between
ja (j = 1.2.3--1 = -n) and a rectifier D1jb (j = 1.2.3--n) between connection point 2 (j-1) and connection point 1j. If the number of feeder lines ≥ 3, connect the connection point (i-1) (j-
A rectifier Dija (i=2.3
mX j=1.2.3n) and connection point m(
A rectifier Dlja (j =
1.2.3 ------- n) and a rectifier D between the connection point (n+1) (j-1) and the connection point ijO.
ijb(+ = 1.2.3−−−−−−−m−1,
j=1.2.3−・−−n) and connection point l (j−1
) and the connection point mj, a rectifier Dmjb (j = 1.2
.. 3 ----1--・-n), and connect a rectifier Dio from each connection point io (i = 1.2.3 to ----m) to one of the output terminals of the rectifier circuit. point in
Connect a rectifier Di(n+1) from each of (i=1.2.3-----m) to the output terminal of the other rectifier circuit, and change the orientation of all the rectifiers to the direction that supplies the load current. This is a full-wave voltage multiplication rectifier circuit characterized by a forward direction.

実施例 〔実施例1〕 第2図は本発明の単相交流電源の電圧逓倍整流回路の実
施例で、電源給電線数回=2、逓倍整流回路段数n=3
の場合である。
Embodiment [Example 1] Figure 2 shows an embodiment of a voltage multiplication rectifier circuit for a single-phase AC power supply according to the present invention, in which the number of power supply lines = 2, and the number of stages of the multiplication rectification circuit n = 3.
This is the case.

動作原理は従来のコツククロフト回路と同様にダイオー
ドの弁作用によるコンデンサの蓄積電荷のポンプツブを
利用する。しかし、従来のコツククロフト回路では接地
側のコンデンサ列を平滑用、非接地側のコンデンサを駆
動用として機能を固定しているのに対し、本発明による
慎相交流電源の電圧逓倍整流回路では、ダイオードD、
。、D2゜の作用により、交流型′/IJ、eの両端に
接続されたコンデンサCi1、C,□、ClffとC2
いC2□、C23の2つのコンデンサ列が交流電源eの
半波ごとに駆動用と電荷蓄積用の役割を交互に果たす。
The operating principle is similar to that of the conventional Kotscroft circuit, which utilizes the valve action of a diode to pump the accumulated charge in a capacitor. However, in the conventional Kotscroft circuit, the functions are fixed such that the capacitor array on the ground side is for smoothing and the capacitor on the non-ground side is for driving, whereas in the voltage multiplication rectifier circuit for a modest-phase AC power supply according to the present invention, the function is fixed by using a diode D.
. , D2°, the capacitors Ci1, C, □, Clff and C2 connected across the AC type '/IJ,e
The two capacitor rows C2□ and C23 alternately play the role of driving and charge storage every half wave of the AC power source e.

このために全波整流となり、交流電源eの電流波形は正
負の各半波が対称となる。
For this reason, full-wave rectification is performed, and the current waveform of the AC power source e has symmetrical positive and negative half-waves.

第2図に示す単相交流電源電圧逓倍整流回路図の動作を
説明すると、最初にコンデンサCIl〜CI3、CZ+
〜C23の電荷がゼロであるとする。交流電源eの正の
半波で、整流器D 218を通じてコンデンサCZIが
波高値Emまで充電された後、交流電源eの電圧がゼロ
に向かう間にコンデンサCZIの電荷の一部が整流器り
、2bを通じてコンデンサCIlと01□に移動する。
To explain the operation of the single-phase AC power supply voltage multiplication and rectification circuit diagram shown in Fig. 2, first, the capacitors CIl to CI3, CZ+
Assume that the charge on ~C23 is zero. After the capacitor CZI is charged to the peak value Em through the rectifier D 218 during the positive half wave of the AC power source e, a part of the charge in the capacitor CZI is transferred to the rectifier D 218 while the voltage of the AC power source e goes to zero. Move to capacitor CIl and 01□.

次の負の半波では、整流器り、bを通じてコンデンサC
8が波高値Emまで充電されるとともにコンデンサCa
lの電荷の一部が整流器D1□bを通じてコンデンサc
1□に移動した後、交流電源eの電圧がゼロに向かう間
にコンデンサCi,から整流器D2□aを通してコンデ
ンサC2□とCalに、コンデンサC+Zがら整流器り
、、aを通じてコンデンサC23にそれぞれ電荷が移動
する。次の交流電源eの正の半波では、再びCHIが波
高値Bmまで充電されるとともに、コンデンサC0の電
荷の一部が整流器D2□aを通してコンデンサC2Tt
に、コンデンサCi□の電荷の一部が整流器り、3aを
通してコンデンサC23にそれぞれ移動する。
In the next negative half-wave, the rectifier R, through b, capacitor C
8 is charged to the peak value Em, and the capacitor Ca
A part of the charge of l passes through the rectifier D1□b to the capacitor c
After moving to 1□, while the voltage of AC power supply e goes to zero, charges move from capacitor Ci to capacitor C2□ and Cal through rectifier D2□a, and from capacitor C+Z to capacitor C23 through rectifier R, , and a. do. At the next positive half-wave of the AC power supply e, CHI is charged again to the peak value Bm, and part of the charge on the capacitor C0 passes through the rectifier D2□a to the capacitor C2Tt.
Then, a part of the charge of the capacitor Ci□ is transferred to the capacitor C23 through the rectifier 3a.

以上のように交流量#eが正負に交番するごとにコンデ
ンサ列Ci〜CI3とC21’−C!ffが交互に電荷
の蓄積およびポンプアップを繰返して、最終的に無負荷
の場合、各コンデンサCIl〜CI ff、C21〜C
ZZは交流電源eの波高値Emまで充電される。
As described above, each time the alternating current amount #e alternates between positive and negative, the capacitor arrays Ci to CI3 and C21'-C! When ff alternately accumulates charge and pumps up, and finally there is no load, each capacitor CIl~CI ff, C21~C
ZZ is charged to the peak value Em of the AC power source e.

したがって、無負荷出力電圧は第3図の破線VI4Vに
示すように3Emに交流電源eの全波整流波形が重畳し
た波形となる。第3図には接続点20.21.22.2
3の各電圧VZO1V21%V22、V21も併記して
いる。また、もう一方の電源供給線側の各接続点10.
11.12.13の電圧はそれぞれ接続点20.21.
22.23の各電圧波形と位相が180°ずれているこ
とは回路の対称性より明らかである。DlいD2゜、D
I3b 、 Dl4、D24は整流器、1.2は電源供
給電線、HV、LVは出力端子、Rは負荷抵抗である。
Therefore, the no-load output voltage has a waveform in which the full-wave rectified waveform of the AC power supply e is superimposed on 3Em, as shown by the broken line VI4V in FIG. Figure 3 shows connection points 20.21.22.2.
3, each voltage VZO1V21%V22 and V21 are also shown. Also, each connection point 10 on the other power supply line side.
The voltages at 11, 12, and 13 are applied to the connection points 20, 21, and 11, respectively.
It is clear from the symmetry of the circuit that the phase is 180° out of phase with each of the voltage waveforms in 22 and 23. DlD2゜、D
I3b, Dl4, and D24 are rectifiers, 1.2 is a power supply wire, HV and LV are output terminals, and R is a load resistance.

出力電圧のリップルを減少させるために第4図に示すよ
うに平滑用コンデンサCsを出力端子H■とLVの間に
接続すると、無負荷出力電圧は第3図に示す破線のピー
ク値4Emとなり、−船釣な表現を用いると、逓倍整流
回路段数nの場合の無負荷直流出力電圧ピーク値は(n
+1) Emとなる。
If a smoothing capacitor Cs is connected between the output terminals H and LV as shown in Fig. 4 in order to reduce the ripple in the output voltage, the no-load output voltage will have a peak value of 4Em as shown by the broken line in Fig. 3. -Using a casual expression, the no-load DC output voltage peak value when the number of stages of the multiplier rectifier circuit is n is (n
+1) becomes Em.

〔実施例2〕 第1図は、本発明の全波電圧逓倍整流回路で、多相交流
(m相交流、給電線数回)をn段電圧逓倍整流する場合
の動作原理は、各相間に実施例1で説明したところの本
発明による全波電圧逓倍整流回路が1組ずつ全部で0組
接続され、かつ各々のコンデンサ列を隣接する回路が共
有していると考えれば、隣接する相間の回路の動作は実
施例Iで説明した単相の本発明による全波電圧逓倍整流
回路の動作と同様であると考えられ、各相間の回路ごと
に位相がずれた整流出力を合成した電圧波形が出力端子
間に現れるものと考えられる。
[Embodiment 2] Fig. 1 shows a full-wave voltage multiplication rectification circuit of the present invention, and the operating principle when performing n-stage voltage multiplication rectification of multiphase AC (m-phase AC, several times on the feeder line) is as follows: If we consider that the full-wave voltage multiplier rectifier circuits according to the present invention as explained in Example 1 are connected one at a time, and that each capacitor row is shared by adjacent circuits, then The operation of the circuit is considered to be similar to the operation of the single-phase full-wave voltage multiplier rectifier circuit according to the present invention explained in Example I, and the voltage waveform is a composite of the rectified outputs whose phases are shifted for each circuit between each phase. It is thought that it appears between the output terminals.

第1図において、Cij(i=1.2.3−− m、j
 = 1 2.3 −−−−−−−−− n)はコンデ
ンサ、Dio(i=1.2.3 −−−−−−・−−−
−m)、Di(n+1) (i = 1.2.3 ・・
・・・・・・・・・ m)、DijaおよびDijb 
 (i=1.2.3−−−−−m、j=1.2.3−・
−・−−−−n )は整流器、1j(i=1.2.3−
−−m、  j = 1 、 2.3−=−−−n )
は接続点、i  (i=l 2.3・−・−・−−−−
m)給電線数、eは交流電源、HV、LVは出力端子で
ある。
In Figure 1, Cij(i=1.2.3−- m, j
= 1 2.3 −−−−−−−−− n) is a capacitor, Dio (i=1.2.3 −−−−−−・−−−
-m), Di(n+1) (i = 1.2.3...
・・・・・・・・・ m), Dija and Dijb
(i=1.2.3----m, j=1.2.3-・
-・---n) is a rectifier, 1j (i=1.2.3-
--m, j = 1, 2.3-=---n)
is the connection point, i (i=l 2.3・−・−・−−−−
m) Number of power supply lines, e is AC power supply, HV, LV are output terminals.

このように本発明の全波電圧逓倍整流回路は、原理的に
無限相交流電源に適用できるが、実施例2は最も一般的
な三相交流電源に適用した場合で、第5図はその回路図
を示す。
In this way, the full-wave voltage multiplication rectifier circuit of the present invention can be applied to an infinite-phase AC power supply in principle, but Embodiment 2 shows the case where it is applied to the most common three-phase AC power supply, and FIG. 5 shows the circuit. Show the diagram.

動作原理は各相間にΔ状に単相の本発明にょる全波電圧
逓倍整流回路が3組接続され、がっコンデンサ列を隣接
する回路が共有していると考えれば、実施例1と全く同
じである。しがし、三相交流電源に適用した場合、無負
荷出力電圧のリップルが著しく改善される6波高値と波
形が等しい単相交流と三相交流を本発明による全波電圧
逓倍整流回路で整流すると、無負荷出力リソプル電圧の
絶対値は通常の単相全波整流と三相全波整流の差異と同
様の改善効果がある。さらにリップル含有率で見ると、
リップル含有率は概略逓倍段数分のlに逓減されるので
、本実施例の3段3相逓倍回路はリップル含有率は平滑
回路なしでも約1%が得られる。
The operating principle is that three sets of single-phase full-wave voltage multiplication rectifier circuits according to the present invention are connected in a Δ shape between each phase, and if we consider that the adjacent circuits share the capacitor array, it is completely similar to the first embodiment. It's the same. However, when applied to a three-phase AC power supply, the ripple of the no-load output voltage is significantly improved.6 Single-phase AC and three-phase AC with equal waveforms and peak values can be rectified by the full-wave voltage multiplication rectifier circuit according to the present invention. Then, the absolute value of the no-load output Lithopul voltage has the same improvement effect as the difference between normal single-phase full-wave rectification and three-phase full-wave rectification. Furthermore, looking at the ripple content,
Since the ripple content rate is reduced approximately to 1 equal to the number of multiplication stages, the three-stage three-phase multiplier circuit of this embodiment can obtain a ripple content rate of approximately 1% even without a smoothing circuit.

第5図において、Ci1%CI2、Ci0、CZI、C
2□、C23、C3いC3□、C33はコンデンサ、D
IG、D++a XDzb 、 I)+za 、 D+
zb 、 I)、za、DIffb、D14、D20、
Dzta % Dz+b % Dzza、Dzzb 、
Dzia 、 Dz:+b 、 DZイD:IO,D3
+a 、D3+b 、、D、、2a 11):+zb 
、 Dz=a 、 D33b 、 Ds4は整流器、1
0.11.12.13.20.21.22.23.30
.31.32.33は接続点、l、2.3は給電線、e
は交流電源、Rは負荷抵抗、HV、LVは出力端子であ
る。
In Figure 5, Ci1%CI2, Ci0, CZI, C
2□, C23, C3 C3□, C33 are capacitors, D
IG, D++a XDzb, I)+za, D+
zb, I), za, DIffb, D14, D20,
Dzta% Dz+b% Dzza, Dzzb,
Dzia, Dz:+b, DZiD:IO,D3
+a, D3+b,,D,,2a 11):+zb
, Dz=a, D33b, Ds4 is a rectifier, 1
0.11.12.13.20.21.22.23.30
.. 31.32.33 is the connection point, l, 2.3 is the feeder line, e
is an AC power supply, R is a load resistance, and HV and LV are output terminals.

〔実施例3〕 第6図に示す実施例3は本発明の全波電圧逓倍整流回路
の出力電圧を半導体スイッチQによる位相制御によって
可変あるいは、安定化した場合である。インダクターし
は突入電源を抑制して半導体スイッチQを保護するため
のものである。
[Embodiment 3] Embodiment 3 shown in FIG. 6 is a case where the output voltage of the full-wave voltage multiplier rectifier circuit of the present invention is varied or stabilized by phase control using a semiconductor switch Q. The inductor is used to protect the semiconductor switch Q by suppressing inrush power.

第6図において、CIl、CI□、Ci0、C21、C
22、C23はコンデンサ、Dla、D++b 、D、
zb、DI3b  s  D14.  Dzo、  D
zta  %  Dzza  %  Dz:+a  %
D24は整流器、10.11.12.13.20.21
.22.23は接続点、eは交流電源、Csは平滑用コ
ンデンサ、Rは負荷抵抗、HV、LVは出力端子である
In FIG. 6, CIl, CI□, Ci0, C21, C
22, C23 is a capacitor, Dla, D++b, D,
zb, DI3b s D14. Dzo, D
zta% Dzza% Dz:+a%
D24 is a rectifier, 10.11.12.13.20.21
.. 22 and 23 are connection points, e is an AC power supply, Cs is a smoothing capacitor, R is a load resistance, and HV and LV are output terminals.

実施例3においては、半導体スイッチQにトライチック
を使用しているが、逆阻止3端子サイリスクの逆並列使
用あるいはトランジスタと整流器の複合接続したものな
どの他のスイッチング素子も使用可能である。
In the third embodiment, a tritic is used for the semiconductor switch Q, but other switching elements such as anti-parallel use of reverse blocking three-terminal tritic or a composite connection of a transistor and a rectifier can also be used.

また、多相回路の場合も各電源ラインに半導体スイッチ
を挿入すれば、単相回路と同様に電圧調整が可能である
Also, in the case of a multi-phase circuit, if a semiconductor switch is inserted into each power supply line, voltage adjustment is possible in the same way as in a single-phase circuit.

〔実施例4〕 第7図に示す実施例4は、本発明の全波電圧逓倍整流回
路の交流電源に高周波インバータを用いた場合で、第7
図ではインバータ回路にプッシュプル方式を使用したが
、他のインバータ(DC−ACコインバータ)回路も使
用できることは言うまでもない。第7図のインダクター
しは突入電流を抑制して半導体スイッチQ、、C2を保
護するためのものである。電源周波数を高周波化するこ
とで、同一出力電圧、電流、リップル電圧を得るために
要する各コンデンサの容量および電源トランスTの小型
軽量化をはかることができることは一般の直流電源と同
様である。
[Embodiment 4] Embodiment 4 shown in FIG. 7 is a case where a high frequency inverter is used as the AC power source of the full-wave voltage multiplication rectifier circuit of the present invention.
In the figure, a push-pull type inverter circuit is used, but it goes without saying that other inverter (DC-AC coinverter) circuits can also be used. The inductor shown in FIG. 7 is for suppressing inrush current and protecting the semiconductor switches Q, C2. As with a general DC power supply, by increasing the power supply frequency, it is possible to reduce the capacity of each capacitor and the size and weight of the power transformer T required to obtain the same output voltage, current, and ripple voltage.

第7図においてCiいCi□、Ci0、Cal、C2□
、C23はコンデンサ、D、 、D2 、D、。、D 
Ilb、DIZb、D+zb、  Dla、[)zo、
Dzta % Dzza %D2xa s Dzaは整
流器、10.11.12.13.20.21.22.2
3は接続点、C3は平滑用コンデンサ、Rは負荷抵抗、
HV、LVは出力端子、Eは直流電源である。
In Figure 7, Ci□, Ci0, Cal, C2□
, C23 is a capacitor, D, , D2 , D,. ,D
Ilb, DIZb, D+zb, Dla, [)zo,
Dzta % Dzza %D2xa s Dza is a rectifier, 10.11.12.13.20.21.22.2
3 is the connection point, C3 is the smoothing capacitor, R is the load resistance,
HV and LV are output terminals, and E is a DC power supply.

発明の効果 以上のように本発明の全波電圧逓倍整流回路は、従来の
半波整流による電圧逓倍整流回路に比べて低リップル化
、多相化への拡張が容易、交流電源の電流波形が正負で
対称となるなどの利点がある。
Effects of the Invention As described above, the full-wave voltage multiplication rectifier circuit of the present invention has lower ripples, is easier to expand to multi-phase, and has improved current waveforms of AC power supplies compared to conventional half-wave rectification voltage multiplication rectification circuits. It has the advantage of being symmetrical in positive and negative directions.

また、電圧逓倍率が逓倍整流回路段数をnとすると、コ
ツククロフト回路の2n倍に対して本発明の回路では(
n+1)倍で不利に見えるが、電源電圧および1段当り
の分担電圧は、使用する整流器の逆耐電圧で制限される
ため、出力電流が0.1A程度以上の比較的容量の大き
な直流高電圧発生器に使用すると、高逆耐電圧大容量の
整流器の入手が困難なために本発明の利点を生かすこと
ができるなど本発明の全波電圧逓倍整流回路は工業的な
らびに実用的価値大なるものである。
Furthermore, when the voltage multiplication rate is 2n times the number of stages of the multiplication rectifier circuit, the circuit of the present invention has (
n + 1) times, which may seem disadvantageous, but the power supply voltage and the shared voltage per stage are limited by the reverse withstand voltage of the rectifier used, so DC high voltage with a relatively large capacity with an output current of about 0.1 A or more When used in a generator, the advantages of the present invention can be utilized because it is difficult to obtain rectifiers with high reverse withstand voltage and large capacity.The full-wave voltage multiplication rectifier circuit of the present invention has great industrial and practical value. It is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のm相n段全波電圧逓倍整流回路の回路
図、第2図、第4図〜第7図は本発明の実施例の回路図
、第3図は第2図の各部の電圧波形図、第8図は従来の
コツククロフト回路に代表される単相電圧逓倍整流回路
の回路図、第9図は従来の対称形コツククロフト回路で
代表される二相半波電圧逓倍整流回路の回路図である。 Cij(i=1.2、−m、j=1.2、−−− n 
)Cs % CiaSctb、 Cic、 C2a、 
C2b、 C2c。 C3a、、C3b、 C3cはコンデンサ、Lはインダ
クタ、Dio(i=1.2、−m) 、D i (n+
1)  (i=1.2、−−−m) 、Dijaおよび
Dijb(i−1,2、−−m j = 1.2、−・
−n)  、D r  〜D 6、Dla−Dba、、
 Dab−Dabは整流器、Rは負荷抵抗、Q、Q、 
、Q2は半導体スイッチ、eは交流電源、HVおよびL
Vは出力端子、Eは直流電源、Tは電源トランスである
FIG. 1 is a circuit diagram of an m-phase n-stage full-wave voltage multiplication rectifier circuit of the present invention, FIGS. 2 and 4 to 7 are circuit diagrams of embodiments of the present invention, and FIG. Voltage waveform diagram. Figure 8 is a circuit diagram of a single-phase voltage multiplier rectifier circuit represented by a conventional Kotscroft circuit. Figure 9 is a circuit diagram of a two-phase half-wave voltage multiplier rectifier circuit represented by a conventional symmetrical Kotscroft circuit. It is a diagram. Cij (i=1.2, -m, j=1.2, --- n
) Cs % CiaSctb, Cic, C2a,
C2b, C2c. C3a, C3b, C3c are capacitors, L is an inductor, Dio (i=1.2, -m), D i (n+
1) (i=1.2, ---m) , Dija and Dijb (i-1,2, --m j = 1.2, ---
-n), Dr~D6, Dla-Dba,,
Dab-Dab is a rectifier, R is a load resistance, Q, Q,
, Q2 is a semiconductor switch, e is an AC power supply, HV and L
V is an output terminal, E is a DC power supply, and T is a power transformer.

Claims (1)

【特許請求の範囲】 単相または多相交流電源の給電線数をm(ただし、m≧
2)、逓倍整流回路段数をnとし、各給電線番号をi(
i=1、2、3・・・・・・・・・・m)とする給電線
iからコンデンサをCi_1、Ci_2、Ci_3Ci
j、・・・・・・・・・・・・Cin(i=1、2、3
、・・・m)の順にn個ずつ直列接続し、給電線 iとコンデンサCi_1の接続点をio、コンデンサC
ijとCi(j+1)(i=1、2、3・・・・・・・
・・・m)j=1、2、3・・・・・・・・・・・・n
−1)の接続点をij、コンデンサCinの出力側端子
をinとし、給電線数回=2の場合は接続点1(j−1
)と接続点2jの間に整流器D2ja(j=1、2、3
・・・・・・・・・・・n)を接続するとともに接続点
2(j−1)と接続点1jとの間に整流器D1jb(j
=1、2、3n)をそ れぞれ接続し、給電線数m≧3の場合は接続点(i−1
)(j−1)と接続点ijの間に整流器Dija(i=
2、3・・・・・・・・・・m、j=1、2、3n)お
よび接続点m(j−1)と接続点1jとの間に整流器D
1ja(j=1、2、3n)を接続 するとともに接続点(i+1)(j−1)と接続点ij
の間に整流器Dijb(i=1、2、3・・・・・・・
・・・・m−1、j=1、2、3・・・・・・・・・・
・・n)および接続点1(j−1)と接続点mjの間に
整流器Dmjb(j=1、2、3・・・・・・・・・・
・・・n)をそれぞれ接続し、接続点io(i=1、2
、3・・・・・・・・・・・・・m)の各々から整流回
路の出力端子の一方に整流器Dioを、接続点in(i
=1、2、3・・・・・・・・・・・・m)の各々から
もう一方の整流回路の出力端子に整流器Di(n+1)
をそれぞれ接続し、上記すべての整流器の向きを負荷電
流を供給する向きに順方向としたことを特徴とする全波
電圧逓倍整流回路。
[Claims] The number of feed lines of single-phase or multi-phase AC power supply is m (however, m≧
2), the number of stages of the multiplier rectifier circuit is n, and each feeder line number is i(
Ci_1, Ci_2, Ci_3Ci from the feeder line i where i = 1, 2, 3...m)
j, ・・・・・・・・・・・・Cin(i=1, 2, 3
,... m) are connected in series in the order of n pieces, and the connection point between the feed line i and the capacitor Ci_1 is connected to io, and the capacitor C
ij and Ci (j+1) (i=1, 2, 3...
・・・m)j=1, 2, 3・・・・・・・・・・・・n
-1) is the connection point ij, the output terminal of the capacitor Cin is in, and if the number of feeder lines = 2, the connection point 1 (j-1
) and the connection point 2j, a rectifier D2ja (j=1, 2, 3
・・・・・・・・・・・・N) is connected, and a rectifier D1jb(j
= 1, 2, 3n) respectively, and if the number of feeder lines m≧3, connect the connection point (i-1
) (j-1) and the connection point ij, a rectifier Dija (i=
2, 3......m, j=1, 2, 3n) and a rectifier D between the connection point m (j-1) and the connection point 1j.
1ja (j=1, 2, 3n) and connect the connection point (i+1) (j-1) and the connection point ij
Between the rectifier Dijb (i=1, 2, 3...
...m-1, j=1, 2, 3...
...n) and a rectifier Dmjb (j=1, 2, 3...) between connection point 1 (j-1) and connection point mj.
... n) respectively, and connect the connection points io (i=1, 2
, 3......m) to one of the output terminals of the rectifier circuit, and the connection point in(i
= 1, 2, 3...m) to the output terminal of the other rectifier circuit.
A full-wave voltage multiplication rectifier circuit characterized in that the rectifiers are connected to each other, and all of the rectifiers are oriented in the forward direction to supply the load current.
JP26516288A 1988-10-20 1988-10-20 Full-wave voltage multiplying rectifier circuit Pending JPH02111263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26516288A JPH02111263A (en) 1988-10-20 1988-10-20 Full-wave voltage multiplying rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26516288A JPH02111263A (en) 1988-10-20 1988-10-20 Full-wave voltage multiplying rectifier circuit

Publications (1)

Publication Number Publication Date
JPH02111263A true JPH02111263A (en) 1990-04-24

Family

ID=17413474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26516288A Pending JPH02111263A (en) 1988-10-20 1988-10-20 Full-wave voltage multiplying rectifier circuit

Country Status (1)

Country Link
JP (1) JPH02111263A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4294377C2 (en) * 1991-12-18 1997-08-14 Kobe Steel Ltd Process for synthesizing diamond using a combustion process
JP2016013015A (en) * 2014-06-30 2016-01-21 浜松ホトニクス株式会社 Step-up rectifier circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828626A (en) * 1971-06-30 1973-04-16
JPS5313843U (en) * 1976-07-16 1978-02-04

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828626A (en) * 1971-06-30 1973-04-16
JPS5313843U (en) * 1976-07-16 1978-02-04

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4294377C2 (en) * 1991-12-18 1997-08-14 Kobe Steel Ltd Process for synthesizing diamond using a combustion process
JP2016013015A (en) * 2014-06-30 2016-01-21 浜松ホトニクス株式会社 Step-up rectifier circuit

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