JPH02110930A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02110930A JPH02110930A JP26377788A JP26377788A JPH02110930A JP H02110930 A JPH02110930 A JP H02110930A JP 26377788 A JP26377788 A JP 26377788A JP 26377788 A JP26377788 A JP 26377788A JP H02110930 A JPH02110930 A JP H02110930A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- semiconductor device
- nitride film
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000002161 passivation Methods 0.000 claims abstract description 35
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 abstract description 11
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 230000009993 protective function Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000008569 process Effects 0.000 abstract description 2
- -1 silicon oxide nitride Chemical class 0.000 abstract 3
- 238000007599 discharging Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010574 gas phase reaction Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 101000883066 Chassalia parviflora Circulin-F Proteins 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置、特にパッシベーション膜を備
えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device provided with a passivation film.
半導体装置、例えば、微細加工を施した高耐圧半導体装
置ではパッシベーション膜に十分な機能をもたせること
が重要である。In a semiconductor device, for example, a high breakdown voltage semiconductor device subjected to microfabrication, it is important to provide a passivation film with a sufficient function.
従来、パッシベーション膜としては、シリコン酸化膜が
使われている。しかし、シリコン酸化膜は耐水性、耐ア
ルカリ汚染の点で十分ではない。Conventionally, a silicon oxide film has been used as a passivation film. However, the silicon oxide film is not sufficient in terms of water resistance and alkali contamination resistance.
最近、シリコン窒化膜が、シリコン酸化膜の前記欠点を
補う膜としてよく使われている。シリコン窒化膜は、シ
リコン酸化膜に比べ、耐水性やＮａ“イオンに対する障
壁効果に優れ、かつ機械的強度に優れるからである。特
に、プラズマ気相成長法（Ｐｌａｓｍａ−ＣＶＤ）によ
るシリコン窒化膜は、上記の長所が顕著であって、しか
も、膜形成が比較的低い温度で行えるという利点がある
（特公昭６２−１００１７号公報、特公昭６２−３４１
３９号公報）。Recently, a silicon nitride film is often used as a film that compensates for the above-mentioned drawbacks of a silicon oxide film. This is because, compared to silicon oxide films, silicon nitride films have superior water resistance and barrier effects against Na" ions, as well as superior mechanical strength. In particular, silicon nitride films produced by plasma-chemical vapor deposition (Plasma-CVD) In addition to the above-mentioned advantages, there is also the advantage that film formation can be performed at a relatively low temperature (Japanese Patent Publication No. 62-10017, Japanese Patent Publication No. 62-341).
Publication No. 39).
しかしながら、このようなシリコン窒化膜は、封止工程
でのボンディングや樹脂封止に伴う熱処理でクランクが
入りやすい。パッシベーション膜に十分な機能を発揮さ
せるために１１通常、膜にある程度の厚みをもたせるの
であるが、シリコン窒化膜は、膜の内部応力が大きく、
１μｍ前後の膜厚になるとクラックが入りやすいのであ
る。クランクの入ったパッシベーション膜は、保護機能
が著しく低下する。そのため、半導体装置は実用に耐え
なくなる。However, such a silicon nitride film is likely to be cranked during bonding in the sealing process or during heat treatment associated with resin sealing. In order for a passivation film to exhibit sufficient functionality, the film is usually made to have a certain thickness, but silicon nitride films have a large internal stress.
When the film thickness is around 1 μm, cracks are likely to occur. A passivation film containing a crank will have a significantly reduced protective function. Therefore, the semiconductor device becomes unusable.
この発明は、熱処理の際にクランクが入りにくく、しか
も、十分な保護機能をもつパッシベーション膜を備えた
半導体装置を提供することを課題とする。An object of the present invention is to provide a semiconductor device that is difficult to be cranked during heat treatment and is equipped with a passivation film that has a sufficient protective function.
前記課題を解決するため、請求項１記載の半導体装置は
、パッシベーション膜を、シリコン酸化膜、シリコン酸
化窒化膜、および、シリコン窒化膜の３層からなるもの
にしている。In order to solve the above problem, in a semiconductor device according to a first aspect of the present invention, the passivation film is made up of three layers: a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.
請求項２記載の半導体装置は、加えて、パッシベーショ
ン膜において、シリコン酸化膜の内部応力が約０．８〜
Ｉ Ｘ １０”ｄｙｎ／ ｃれシリコン酸化窒化膜の内
部応力が約１〜２ Ｘ １０ ’ｄｙｎ／ ｃｄ、シリ
コン窒化膜の内部応力が約２〜４ Ｘ １０ ’ｄｙｎ
／ ｃａｔとなるようにしている。In addition, in the semiconductor device according to claim 2, in the passivation film, the internal stress of the silicon oxide film is about 0.8 to about 0.8.
The internal stress of the silicon oxynitride film is approximately 1 to 2 X 10' dyn/cd, and the internal stress of the silicon nitride film is approximately 2 to 4 X 10' dyn/cd.
/cat.
この発明の半導体装置のパッシベーション膜は、シリコ
ン酸化膜、シリコン酸化窒化膜、および、シリコン窒化
膜の３層からなる構成であるため、膜に厚みをもたせて
も、熱処理によるクラックの発生は抑えられ、半導体装
置が十分な機能のパッシベーション膜を備えることにな
る。半導体装置は、ＴＨＢ、ＢＴ等の試験にかけても特
性の劣化が極めて少ない信頼性の高いものとなるのであ
る。Since the passivation film of the semiconductor device of the present invention is composed of three layers: a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, even if the film is made thick, the occurrence of cracks due to heat treatment can be suppressed. , the semiconductor device will be provided with a passivation film with sufficient functionality. The semiconductor device becomes highly reliable with extremely little deterioration in characteristics even when subjected to tests such as THB and BT.
パッシベーション膜において、シリコン酸化膜の内部応
力が０．８〜Ｉ Ｘ １０ ’ｄｙｎ／ ｃｎｌ、シリ
コン酸化窒化膜の内部応力が１〜２ Ｘ １０ ’ｄｙ
ｎ／ ｃｒＡ、シリコン窒化膜の内部応力が２〜４×１
０°ｄｙｎ／ｃｊとなっていると、クランクは、−層、
入り難くなる（この数値は、圧縮モードでのものである
）〔実 施 例〕
以下、この発明にかかる半導体装置を、その−例をあら
れす図面を参照しながら詳しく説明する第１図は、この
発明の半導体装置のパッシベーション膜まわりの構成を
あられす。In the passivation film, the internal stress of the silicon oxide film is 0.8 to I X 10' dyn/cnl, and the internal stress of the silicon oxynitride film is 1 to 2 X 10' dy.
n/crA, internal stress of silicon nitride film is 2 to 4×1
When it is 0°dyn/cj, the crank is -layer,
(This value is for the compressed mode) [Example] Hereinafter, an example of the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The structure around the passivation film of the semiconductor device of this invention will be described below.
半導体装置は、半導体素子として１０００ Ｖ耐圧のバ
イポーラトランジスタ（図示省略）が形成された半導体
基板ｌを備えるとともに、この基板ｌを覆うパッシベー
ション膜２を備えている。このパッシベーション膜２は
３種類の模からなる。すなわち、最下層にシリコン酸化
膜（ＳｉＯ□が主構成要素）２ａ、中間層にシリコン酸
化窒化膜２ｂ、最上層にシリコン窒化膜（ＳｉｓＮ４が
主構成要素）２Ｃが積層形成されているである。これら
３つの膜は、いずれも、プラズマ気相反応法（Ｐｌａｓ
ｍａ−ＣＶＤ）により形成されたものである。なお、５
は半導体素子の電極（、＋１電極）であり、６は絶縁層
（熱酸化層）である。The semiconductor device includes a semiconductor substrate l on which a 1000 V bipolar transistor (not shown) is formed as a semiconductor element, and a passivation film 2 covering the substrate l. This passivation film 2 consists of three types of patterns. That is, a silicon oxide film (mainly composed of SiO□) 2a is formed in the bottom layer, a silicon oxynitride film 2b is formed in the middle layer, and a silicon nitride film (mainly composed of SisN4) 2C is formed in the uppermost layer. These three films are all produced using plasma gas phase reaction method (Plasma gas phase reaction method).
It was formed by ma-CVD). In addition, 5
is an electrode (+1 electrode) of the semiconductor element, and 6 is an insulating layer (thermal oxidation layer).
パッシベーション膜における各膜２ ａ、２ｂ、２Ｃは
、第２図に示すプラズマ気相反応法による膜形成装置に
よって製膜されている。Each of the films 2a, 2b, and 2C in the passivation film is formed by a film forming apparatus using a plasma vapor phase reaction method shown in FIG.
この第２図の装置は、反応室ＩＯ内に対向する一対の上
電極１１、下電極１２を備えており、上電極１１面から
反応ガスを供給できるようになっている。一方、ＲＦ電
源１３から画電極１１．１２間に高周波電力を供給でき
るようになっている。そして、この装置は、下電極１２
上に素子が形成された半導体基板１を置いて、反応ガス
および高周波電力の供給を行いプラズマを発生させて半
導体基板の表面に膜を被着させるようになっている。な
お、１４は基板１加熱用ヒータ、１５．１５′は皐色縁
物、１６はシャターリングである。The apparatus shown in FIG. 2 includes a pair of upper electrodes 11 and lower electrodes 12 facing each other in a reaction chamber IO, and a reaction gas can be supplied from the surface of the upper electrodes 11. On the other hand, high frequency power can be supplied from the RF power source 13 between the picture electrodes 11 and 12. In this device, the lower electrode 12
A semiconductor substrate 1 on which elements are formed is placed, and reactive gas and high frequency power are supplied to generate plasma to deposit a film on the surface of the semiconductor substrate. Note that 14 is a heater for heating the substrate 1, 15 and 15' are brown edges, and 16 is a shutter ring.
各１ｆｆ２ａ〜２Ｃ形成条件、および、形成された膜の
内部応力はつぎのとおりであった。The conditions for forming each of 1ff2a to 2C and the internal stress of the formed films were as follows.
■ シリコン酸化膜（Ｐｌａｓｍａ−３ｉＯ膜）２ａｆ
ａ＋ 膜厚み ・・・５０００人（ｂ）Ｒ
Ｆ電源の周波数 ＝ ５０ ｋ Ｈｚ（ＣＩＲＦ電源
の出力 ・・・１５０ Ｗ（ｄ） 反応室圧力
−０，４０Ｔｏｒｒ（Ｑ） 反応ガス Ｎ２
ガス ・１００ ＳＣＣＭＮｚ ＋ ５ｉｌｌ＋
（２０χ）・・・１００ ＳＣＣＭＮ、０
・・・５００ ＳＣＣＭウェハ加熱温度
・・・３００℃膜の内部応力（圧縮モード）
−０，８〜Ｉ Ｘ １０ ’ｄｙｎ／ ｃＪシリコン酸
化窒化膜（Ｐｌａｓｍｓ−ＳｉＯＮ膜）２ｂ膜厚み
・・・５０００人
ＲＦ電源の周波数 ・・・５０ ｋ ＨｚＲＦ電源の
出力 ・・・１１５ Ｗ反応室圧力 ・・
・０．４５Ｔｏｒｒ反応ガス ＮＺガス ・・・
１５０ ＳＣＣＭＮ２ ＋５ｉｌ１４（２０χ）・・・
９０５ＣＣ１’ｌＮｚ０ ・・・ ４３
ＳＣＣＭウェハ加熱温度 ・・・３００℃
膜の内部応力（圧縮モード）
”’ １〜２ Ｘ １０ ’ｄｙｎ／ ｃｎｌシリコン
窒化膜（Ｐｌａｓｍａ−５ｉＮｌｐＪ） ２ ｃ膜厚
み ・・・５０００人
ＲＦ電源の周波数 ・・・５０ｋＨｚＲＦ電源の出力
・・・１１５Ｗ
反応室圧力 ・・・Ｑ、５ＱＴｏｒｒ反応ガス
Ｎ２ガス ・・・４００ ＳＣＣＭＮ！ ＋
５ｉＨ４（２０χ） ・・・ ４２ ＳＣＣＭ（ｆｌ
ウェハ加熱温度 ・・・３００℃（ｇｌ
膜の内部応力（圧縮モード）・・・ ２〜４ Ｘ
１ ０ ”ｄｙｎ／ ｃｄ二の°ように上記パッ
シベーション膜２を形成した半導体装置を熱処理し、パ
ッシベーション膜におけるクランク発生の有無を調べた
。なお、比較のために、パッシベーション膜が、シリコ
ン酸化膜、シリコン窒化膜、シリコン酸化窒化膜の単独
膜からなる（第１表参照）他は実施例と同じ半導体装置
（比較例１〜９）をそれぞれ作製し、やはり同様に熱処
理し、パッシベーション膜におけるクランクの発生の有
無を調べた。なお、単独膜の場合、厚みが、５０００人
、１００００人、１５０００人と異なる３種類のものを
作製した。■ Silicon oxide film (Plasma-3iO film) 2af
a+ Film thickness...5000 people (b)R
Frequency of F power supply = 50 kHz (output of CIRF power supply...150 W (d) Reaction chamber pressure
-0,40Torr(Q) Reaction gas N2
Gas ・100 SCCMNz + 5ill+
(20χ)...100 SCCMN, 0
...500 SCCM wafer heating temperature
...Internal stress of 300℃ film (compression mode) -0,8~I
...5000 people Frequency of RF power supply ...50 kHz RF power supply output ...115 W Reaction chamber pressure ...
・0.45Torr reaction gas NZ gas...
150 SCCMN2 +5il14(20χ)...
905CC1'lNz0...43
SCCM wafer heating temperature...300℃
Internal stress of the film (compression mode) 1~2 x 10' dyn/ cnl silicon nitride film (Plasma-5iNlpJ) 2c film thickness...5000 people Frequency of RF power supply...Output of 50kHz RF power supply... 115W Reaction chamber pressure...Q, 5QTorr Reaction gas N2 gas...400 SCCMN! +
5iH4 (20χ) ... 42 SCCM (fl
Wafer heating temperature...300℃ (gl
Internal stress of membrane (compression mode)... 2 to 4 X
The semiconductor device on which the passivation film 2 was formed was heat-treated to a temperature of 10" dyn/cd 2°, and the presence or absence of cranking in the passivation film was examined. For comparison, the passivation film was a silicon oxide film, a silicon oxide film, Semiconductor devices (Comparative Examples 1 to 9) consisting of single films of silicon nitride film and silicon oxynitride film (see Table 1), which were otherwise the same as those of the examples, were fabricated and heat-treated in the same manner to improve the crankshaft in the passivation film. The presence or absence of occurrence was investigated. In the case of single films, three types with different thicknesses were prepared: 5,000, 10,000, and 15,000.
なお、熱処理は、半導体装置を、ＧＧガス（Ｎ。Note that the heat treatment is performed on the semiconductor device using GG gas (N.
ガスをベースにＨ１ガスを５〜１５％混合したガス）中
、４５０℃の温度下、３０分間放置するというものであ
る。結果、すなわちクランク発生の有無を、第１表に記
す。The sample is left for 30 minutes at a temperature of 450° C. in a gas mixture of 5 to 15% H1 gas based on a gas mixture. The results, ie, whether or not cranking occurred, are shown in Table 1.
第１
表
一方、上記実施例および比較例の半導体装置のパッシベ
ーション膜の機能を調べるために、各半導体装置をＴＨ
Ｂ試験にかけた。Table 1 On the other hand, in order to investigate the function of the passivation film of the semiconductor devices of the above example and comparative example, each semiconductor device was subjected to TH
I took the B test.
試験条件は、温度：８５℃、湿度：８５％、バイアス電
圧：８００Ｖ （１００ＯＶの８０％）である。バイポ
ーラトランジスタのベース・コレクタ間の漏れ電流が、
１００μＡ以上となったものを不合格と判定するように
した。結果を第２表に示す、なお、第２表において、○
印は、１０個の同じ供試半導体装置が全て合格であるこ
とを示し、Δ印は８個以上が合格であることを示し、×
は合格個数が７個以下であることを示している。The test conditions were: temperature: 85°C, humidity: 85%, bias voltage: 800V (80% of 100OV). The leakage current between the base and collector of a bipolar transistor is
Those with a value of 100 μA or more were determined to be rejected. The results are shown in Table 2. In Table 2, ○
The mark indicates that all 10 of the same test semiconductor devices passed, the Δ mark indicates that 8 or more passed, and ×
indicates that the number of passed items is 7 or less.
第２表
実施例のパッシベーション膜は、膜の厚みが厚くても、
第１表にみるように、比較例のそれに比べ、熱処理によ
るクランクが発生しにくい。しかも、実施例のパッシベ
ーション膜は、第２表にみるように、膜の厚みが十分で
あるため十分な機能をもっている。比較例１．４．７の
半導体装置のパッシベーション膜は、厚みが薄い分、第
１表にみるように、クランクは入り難いが、第２表にみ
るように、機能が十分でない。Even if the passivation film of the example in Table 2 is thick,
As shown in Table 1, cranking due to heat treatment is less likely to occur compared to that of the comparative example. Moreover, as shown in Table 2, the passivation film of the example has sufficient thickness and therefore has a sufficient function. Since the passivation film of the semiconductor device of Comparative Example 1.4.7 is thin, as shown in Table 1, it is difficult to insert a crank, but as shown in Table 2, the function is not sufficient.
この発明は上記実施例に限らない。半導体基板に形成さ
れる素子は、前記例示のバイポーラトランジスタの他、
ＤＭＯ５ＦＥＴ 、 Ｃ−ＭＯＳ 、あるいは、多種頬
の素子からなるＩＣ等であってもよい。シリコン酸化膜
、シリコン酸化窒化膜、あるいは、シリコン窒化膜は、
プラズマ気相反応性以外の方法で形成された膜であって
もよい。ただ、プラズマ気相反応法によれば、緻密な膜
が形成でき、しかも、低温で形成可能である等の利点が
ある。各膜の厚みは上記実施例の５０００人に躍らず、
２０００人程度０薄いものから例えば、６０００人程度
０厚いもの等、適宜に選択すればよいことはいうまでも
ない。This invention is not limited to the above embodiments. Elements formed on the semiconductor substrate include the above-mentioned bipolar transistor,
It may be a DMO5FET, C-MOS, or an IC made of various types of elements. Silicon oxide film, silicon oxynitride film, or silicon nitride film is
The film may be formed by a method other than plasma gas phase reactivity. However, the plasma vapor phase reaction method has advantages such as being able to form a dense film and also at a low temperature. The thickness of each membrane is not as high as 5000 in the above example,
Needless to say, the thickness may be selected as appropriate, such as from a thickness of about 2,000 thick to a thickness of about 6,000.
各３つの膜の積層順序も実施例に限定されない。The stacking order of each of the three films is also not limited to the example.
例えば、中間層にシリコン窒化膜、最上層にシリコン酸
化窒化膜を形成したり、最下層にシリコン酸化窒化膜、
中間層にシリコン酸化膜、最上層にシリコン窒化膜を形
成するようにしてもよい。For example, a silicon nitride film may be formed in the middle layer, a silicon oxynitride film may be formed in the top layer, or a silicon oxynitride film may be formed in the bottom layer.
A silicon oxide film may be formed as an intermediate layer, and a silicon nitride film may be formed as an uppermost layer.
以上に述べたように、請求項１．２記載の半導体装置の
パッシベーション膜は、シリコン酸化膜、シリコン酸化
窒化膜、シリコン窒化膜の３層からなるため、厚くても
熱処理の際にクラックが入り難く、しかも、膜自体に十
分な機能をもたせられる。請求項２記載の半導体装置で
は、パッシベーション膜を構成する３層の股が、それぞ
れ、パッシベーション膜がより優れたものとなるような
内部応力をもっている。そのため、請求項１．２記載の
半導体装置は信頼性が極めて高い。As described above, the passivation film of the semiconductor device according to claim 1.2 is composed of three layers: a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, so even if it is thick, cracks may occur during heat treatment. However, it is possible to provide the membrane itself with sufficient functionality. In the semiconductor device according to the second aspect of the present invention, each of the three layers constituting the passivation film has an internal stress that makes the passivation film more excellent. Therefore, the semiconductor device according to claim 1.2 has extremely high reliability.
第１図は、この発明にかかる半導体装置におけるパッシ
ベーション膜まわりの構成をあられす概略断面図、第２
図は、このパッシベーション膜の形成に使われる膜形成
装置をあられす模式的説明図である。
ｌ・・・半導体Ｍｔ＆ ２・・・バノシヘーシミ
Ｉン恢２ａ・・・シリコン酸化膜 ２ｂ・・・シリコ
ン酸化窒化膜 ２Ｃ・・・シリコン窒化膜
代理人 弁理士 松 本 武 彦FIG. 1 is a schematic cross-sectional view showing the structure around the passivation film in a semiconductor device according to the present invention, and FIG.
The figure is a schematic explanatory diagram showing a film forming apparatus used for forming this passivation film. l...Semiconductor Mt& 2...Silicon oxide film 2b...Silicon oxynitride film 2C...Silicon nitride film Agent Patent attorney Takehiko Matsumoto
Claims (1)
ン膜を備えた半導体装置において、前記パッシベーショ
ン膜が、シリコン酸化膜、シリコン酸化窒化膜、および
、シリコン窒化膜の３層からなることを特徴とする半導
体装置。 ２ パッシベーション膜において、シリコン酸化膜の内
部応力が約０．８〜１×１０＾９ｄｙｎ／ｃｍ＾２、シ
リコン酸化窒化膜の内部応力が約１〜２×１０＾９ｄｙ
ｎ／ｃｍ＾２、シリコン窒化膜の内部応力が約２〜４×
１０＾９ｄｙｎ／ｃｍ＾２である請求項１記載の半導体
装置。[Scope of Claims] 1. In a semiconductor device including a passivation film covering a substrate on which a semiconductor element is formed, the passivation film is composed of three layers: a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. A semiconductor device characterized by: 2 In the passivation film, the internal stress of the silicon oxide film is approximately 0.8 to 1 x 10^9 dyn/cm^2, and the internal stress of the silicon oxynitride film is approximately 1 to 2 x 10^9 dyn/cm^2.
n/cm^2, the internal stress of the silicon nitride film is approximately 2 to 4×
2. The semiconductor device according to claim 1, wherein the density is 10^9 dyn/cm^2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26377788A JPH02110930A (en) | 1988-10-19 | 1988-10-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26377788A JPH02110930A (en) | 1988-10-19 | 1988-10-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02110930A true JPH02110930A (en) | 1990-04-24 |
Family
ID=17394136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26377788A Pending JPH02110930A (en) | 1988-10-19 | 1988-10-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02110930A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100643493B1 (en) * | 2004-09-23 | 2006-11-10 | 삼성전자주식회사 | Method for forming silicon oxynitride layer in semiconductor device and fabricating equipment thereof |
| KR100716904B1 (en) * | 2005-12-28 | 2007-05-10 | 동부일렉트로닉스 주식회사 | Passivation layer for semiconductor device and manufacturging method thereof |
| JP2010166081A (en) * | 2010-03-25 | 2010-07-29 | Renesas Electronics Corp | Mis transistor |
| CN111512440A (en) * | 2017-12-27 | 2020-08-07 | 美光科技公司 | Transistors and arrays of elevationally extended memory cell strings |
-
1988
- 1988-10-19 JP JP26377788A patent/JPH02110930A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100643493B1 (en) * | 2004-09-23 | 2006-11-10 | 삼성전자주식회사 | Method for forming silicon oxynitride layer in semiconductor device and fabricating equipment thereof |
| KR100716904B1 (en) * | 2005-12-28 | 2007-05-10 | 동부일렉트로닉스 주식회사 | Passivation layer for semiconductor device and manufacturging method thereof |
| JP2010166081A (en) * | 2010-03-25 | 2010-07-29 | Renesas Electronics Corp | Mis transistor |
| CN111512440A (en) * | 2017-12-27 | 2020-08-07 | 美光科技公司 | Transistors and arrays of elevationally extended memory cell strings |
| JP2021509226A (en) * | 2017-12-27 | 2021-03-18 | マイクロン テクノロジー，インク． | An array of transistors and strings extending in the height direction of the memory cells |
| CN111512440B (en) * | 2017-12-27 | 2023-11-03 | 美光科技公司 | Array of vertical, horizontal transistors, and vertically extending strings of memory cells |
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