JPH02110614A - Data processor - Google Patents

Abstract

PURPOSE:To make a data processor high in performance by providing a measuring means to measure the delay time of a logic circuit, and changing the operating system of the logic circuit when the delay time exceeds the range of some definite value. CONSTITUTION:A clock signal outputted from a clock signal generation circuit 1 is supplied to the logic circuit 5 through a clock signal line 6, and simultaneously, is inputted to a comparator 4. The delay time of the logic circuit 5 is measured by a ring oscillator 2, and the output of the ring oscillator 2 is connected to the input of another side of the comparator 4 through a frequency division circuit 3. Thus, the delay time of the logic circuit 5 and a clock signal period are compared in the comparator 4, and when the delay time is late, an operating system instruction signal 7 is outputted to the logic circuit 5. Thus, since the operating system optimum to the delay time of the logic circuit can be selected dynamically, the performance of the logic circuit can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and more particularly to a data processing device that changes the operating method of a logic circuit in response to variations in delay time of the logic circuit.

[Conventional technology]

One of the factors that determines the operating method of a logic circuit in a data processing device is the delay time of the logic circuit. The delay time of a logic circuit changes depending on element variations, temperature conditions, voltage fluctuations, etc., so when designing a logic circuit, the operation method should be determined by considering the delay time under all conditions that guarantee operation. There must be. Therefore, the tarock signal given to the logic circuit has also been determined with consideration given to allowing this variation in delay time. Since the worst case for a clock signal is the slowest delay time, a clock signal suitable for the delay time in this case is provided. Therefore, even in the normal case, a slow clock signal is always given in consideration of the worst case, which is a factor that hinders the performance improvement of logic circuits.

To solve the above problem, in conventional systems, a lock signal suitable for the delay time of the logic circuit is obtained by varying the period of the tarock signal in proportion to the variation of the delay time of the logic circuit. ing. Such a technique is described in, for example, Japanese Patent Laid-Open No. 62-60020.

[Problem to be solved by the invention]

In the above conventional technology, in order to vary the clock signal period in proportion to the delay time of the logic circuit, firstly, the delay time differs from logic circuit to logic circuit due to variations in elements, etc., so the clock signal period also varies from logic circuit to logic circuit. Second, as the delay time changes due to voltage fluctuations, temperature fluctuations, etc., the clock signal period changes even during the operation of the logic circuit. Data processing devices generally include other components such as memory elements in addition to logic circuits, but these are often required to operate at a fixed time independent of the delay of the logic circuits. , voltage fluctuations, and temperature fluctuations also show different characteristics from the delay time fluctuations of logic circuits.

Therefore, if the tarok signal to the logic circuit is varied moment by moment in proportion to the delay time as in the prior art described above, the operating time for other components other than the logic circuit will not be constant, resulting in problems. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that eliminates the above-mentioned drawbacks and improves the performance of a logic circuit by selecting an operation method that is optimal for the delay time of the logic circuit. It is in.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a clock signal generation circuit that generates a reference clock signal, a measuring means that measures the delay time of a logic circuit, and a comparison between the clock signal period and the measured value of the logic circuit delay time. In addition, the logic circuit has a plurality of operating methods, and any one of these operating methods can be selected, and when the delay time becomes slower than the clock signal period, This is achieved by changing the operating method of the logic circuit.

According to another method, the above object is a variable clock signal generation circuit that can vary the clock signal period, and has a plurality of clock signal periods as options for the operation method of the logic circuit. This is achieved by changing the tarok signal period when the delay time becomes slower than the clock signal period.

However, in the solutions for the above two points, changing the operating method of the logic circuit may change the performance of the data processing device. Has a choice of circuit operation methods,
In addition, the second operating method option is such that the performance of the data processing device is changed respectively, and when the first operating method is changed, the second operating method is selected so as to offset the change in the performance of the data processing device caused by the change. This problem can be solved by controlling the operation method of No. 2 to be changed.

Furthermore, if the performance of the data processing device also changes due to a change in the second operation method, there is a means for notifying the performance deterioration of the data processing device; This makes it possible to notify users of performance deterioration.

[Effect]

In data processing equipment, by constantly measuring the delay time of logic circuits and comparing this measurement value with the clock signal,
It is possible to detect a mismatch between the delay time of a logic circuit and the cycle of a clock signal, which occurs due to variations in conditions such as element variations, voltage variations, and temperature conditions. Therefore, when the delay time of the logic circuit becomes slower than the clock signal, malfunction of the logic circuit due to the mismatch can be prevented by detecting this mismatch and changing the operation method.

Examples of changing the operating method of the logic circuit include changing the operating mode and changing the clock signal period. The operation method is changed when the measured delay time of the logic circuit becomes slower than the clock signal period, including when the clock signal period is changed. In other words, the operation method is changed continuously. Since the time of operation of other components of the logic circuit does not become constant, the operation time of the other components of the logic circuit does not become constant.

〔Example〕

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a data processing apparatus according to the present invention. In FIG. 1, the clock signal output from the clock signal generation circuit 1 is connected to the clock signal line 6.
The signal is supplied to the logic circuit 5 through the signal line and simultaneously input to the comparator 4. The delay time of the logic circuit is measured by a ring oscillator 2, and the output of the ring oscillator 2 is connected to the other input of a comparator 4 through a frequency dividing circuit 3. As a result, the comparator 4 compares the delay time of the logic circuit with the clock signal period, and when the delay time is slow, an operation method change instruction signal 7 is output to the logic circuit 5.

FIG. 2 is a diagram showing an example of changing the operating method. In this embodiment, a route for transferring data from register All to register C13 via gate logic circuit 12 will be explained.

Since both the register All and the register C15 are set in synchronization with the clock signal phase A16, the gate logic circuit 12
If the minimum delay time is not large enough, old data will be transferred during transfer, resulting in malfunction. Therefore, it is necessary to provide a register B13 between the gate logic circuit 12 and the register C15, which is set at a clock signal phase B17 which is different in phase from the clock signal phase A, for transfer.

FIG. 3 shows a time chart of the operation method shown in FIG. 2. Data set in register A at clock signal phase A is transferred to register B at clock signal phase B, and further transferred to register C at the next clock signal phase A. In the above operation method, the delay time of the gate logic circuit 12 needs to be within the difference between the clock signal phase A and the clock signal phase B.

Here, assume a case where the delay time of the logic circuit increases due to element variations, voltage fluctuations, temperature fluctuations, etc., and the delay time of the gate logic 12 cannot keep up with the difference between clock signal phase A and clock signal phase B. In the above case, it is detected by the comparator 4 in FIG. 1, and the operation method change instruction signal 7 is output. In response to the operation method change instruction signal 7, the selector 14 provided between the register B13 and the register C15 directly transfers the output of the gate logic circuit 12 to the register C15 instead of the register B13. As in this case, when the delay time of the logic circuit is slow, the maximum delay time of the gate logic circuit 12 also becomes sufficiently large.

Direct transfer from register A to register C at the same level does not cause any problem. FIG. 4 shows a time chart of the operation method in this case.

FIG. 5 is a diagram showing another example of changing the operating method. In FIG. 5, a route for transferring data from register D21 to register E23 via gate logic 22 will be explained.

FIG. 6 shows a normal operating system time chart of FIG. 5. In the normal operation mode, the operation mode change instruction signal line 7 is 0', so the NOTOR gate 26 output is 1' and the output of the OR gate 26.27 is always 1'. The outputs of the AND gates 24.25 therefore correspond to the respective clock signal phases D31. Since it is output when the clock signal phase E32 is output, the register D21 is set at the clock signal phase D31, and the set data is sent to the register E at the clock signal phase E32 via the gate logic circuit 22.
It is set to 23. In the above operating system, the delay time of the gate logic circuit 22 must be within the difference between the tarlock signal phase difference and the tarlock signal phase E.

When the delay time of the logic circuit increases and the delay time of the loop circuit 22 cannot keep up with the difference between the clock signal phase difference and the clock signal phase difference, the operation method is changed as in the embodiment shown in FIG. The instruction signal line 7 becomes 1' and the operation method is changed.

A time chart of this operation method is shown in FIG.

Since the operation method change instruction signal line 7 is 1', the NOTOR gate 26 output is always O', and the OR gates 26 and 27 indicate that the output Q of the first FF circuit 30 or the output Q of the second FF circuit 31 is 1'. FI whose output is 1' only when ? The output Q of the circuit 30 is connected to the input terminal of the second FF circuit 31, and the output Q of the second FF circuit is connected to the input terminal of the first FF circuit. Therefore, the output Q of the first OFF circuit repeatedly outputs 0' and 1' every time the clock signal phase is inputted. Similarly, the output Q of the second FF circuit also repeats O' and 1' every time the clock signal phase E is input. As a result, the AND gate 24 outputs the clock signal phase every other time, and the AND gate 25 similarly outputs the tarock signal phase E every other time. The data set in the register D21 at the clock signal phase is passed through the gate logic circuit 22, and is set at the register E23 at the clock signal phase E one cycle later.

In other words, by changing the operation method, the gate logic circuit 22
This means that the delay time has been extended by one cycle.

However, in the embodiment shown in FIG. 5, unlike the embodiment shown in FIG. 2, the performance of data processing "A" deteriorates.

FIG. 8 is a block diagram of another embodiment of the data processing device according to the present invention. In this embodiment, the clock signal generation circuit is a variable clock signal generation circuit 41, which is composed of a clock oscillator 42 and a variable frequency dividing circuit 43. In addition, the output operation method change instruction signal l of the comparator 4
;A7 is not input to the logic circuit 5 and is input to the performance adjustment circuit 44. Performance degradation notification circuit 45. The signal is input to a variable frequency divider circuit 43.

Similar to the embodiment shown in FIG. 1, when the ratio 1 diaphragm 4 detects that the delay time of the logic circuit is slower than the clock signal period, the operation method change instruction signal line 7 becomes 1', and the variable frequency divider circuit 4
This will be communicated to 3. When the variable frequency divider circuit 43 receives the signal J:, it changes the frequency division value and delays the clock signal period of the clock signal line 6. This makes it possible to cope with an increase in delay time of the logic circuit.

However, in this embodiment, since the tarock signal period is delayed, the performance of the data processing device is degraded.

Generally, data processing devices often have a performance adjustment circuit in order to create multiple models with different performances using the same logic circuit. In all but the top models, performance adjustment circuitry always reduces some percentage of performance. If the performance that has decreased due to the change in the operating system is within the range that is reduced by the performance adjustment circuit, it is possible to avoid the decrease by correcting the decreased amount using the performance adjustment circuit. Therefore, in this embodiment, the operation method change instruction signal, line 7
is connected to a performance adjustment circuit to compensate for the performance that has decreased due to the change in operating method.

If the data processing device whose operating method is to be changed is a top-of-the-line model, or if the performance improvement achieved by the performance adjustment circuit does not make up for the loss, it is necessary to promptly notify the hardware and software of the performance degradation of the data processing device. be. Therefore, in this case, the operation method change instruction signal line 7 is connected to the performance deterioration notification circuit, and notification is performed by this circuit.

〔Effect of the invention〕

As explained above, according to the present invention, in a data processing device, it becomes possible to dynamically select an operation method that is optimal for the delay time of a logic circuit, thereby improving the performance of the logic circuit and improving data processing. This has the effect of improving the performance of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a logic diagram showing an embodiment of changing the operation method,
Figure 3 is a time chart of the logic in Figure 2 during normal operation, Figure 4 is a time chart of the logic in Figure 2 after changing the operating method,
FIG. 5 is a logic diagram showing another example of changing the operation method;
Figure 6 shows the time chart during normal operation of the logic in Figure 5.
FIG. 7 is a time chart after changing the operating system of the logic shown in FIG. 5, and FIG. 8 is a block diagram of a data processing device according to another embodiment of the present invention. 1... Clock signal generation circuit. 2... Ring oscillator, 3... Frequency divider circuit, 4...
- Comparator, 5...Logic circuit, 6...Clock signal line. 7... Operation method change instruction signal line, 11... Register A, 12... Gate logic circuit, 13... Register B, 14... Selector, 15
...Register C1■6...Clock signal phase A. 17...Clock signal phase B. 21...Register D, 22...Gate logic circuit, 23...Register E, 24.25...
AND gate, 26, 2? ,...OR gate, 28-
...NOT gate, 29...first FF circuit, 30
. . . second FF circuit, 31 . . . clock signal phase difference. 32...Clock signal phase E. 41... Variable clock signal generation circuit, 42... Clock oscillator, 43... Variable frequency dividing circuit, 44... Performance adjustment circuit, 45... Low performance disconnection circuit. Otoko 4th ro t 70-・7 ni 1 ga ko 11 narrow net fear Akira Otoguchi Taku 7 ward

Claims (1)

[Claims] 1. It has a measuring means for measuring the delay time of the logic circuit, and when the delay time exceeds a certain predetermined value range, the operating method of the logic circuit is changed. data processing equipment. 2. The data processing device according to item 1, comprising a variable clock signal generation circuit capable of varying the clock cycle time of the reference clock signal, and when the delay time exceeds a certain predetermined value range, the reference clock signal is A data processing device characterized by changing the cycle time of a signal. 3. The data processing device according to item 1, wherein the logic circuit has a plurality of logic operation methods, and when the delay time exceeds a certain predetermined range, the logic operation method is changed. data processing equipment. 4. The data processing device according to item 1, having an external factor that affects the delay time of the logic circuit, and changing the external factor when the delay time exceeds a certain predetermined range. data processing equipment. 5. In the data processing device according to paragraph 1, if the delay time exceeds a certain predetermined range, one or more of the means described in paragraphs 2, 3, and 4. A data processing device characterized by simultaneously employing the following. 6. In a system where multiple data processing devices described in paragraph 1 operate together, if the logic circuit delay time of a certain data processing device exceeds a certain value range, the operation method of the data processing device will be changed. 1. A data processing device characterized in that the data processing device changes the operation method of one or more other data processing devices other than the data processing device.