JPH0211022A - Pll circuit - Google Patents

Abstract

PURPOSE:To prevent a level difference from generating at the phase and frequency of an output signal in any case by comparing the output signal and applying a prescribed bias to the input side of a low pass filter when an abnormality is detected. CONSTITUTION:The title circuit provides a detecting means 6 to detect the abnormality of an output signal, a signal switching means 5 to input an output signal to a comparing means 1 in place of a reference signal 100 when an abnormality is detected by the detecting means 6 and a bias impressing means 7 to apply a prescribed bias to the input side of a low pass filter when at least the detecting means 6 detects the abnormality. When the abnormality is detected, the comparing means 1 compares the output signal, outputs the result of the phase difference zero to a low pass filter 2, a prescribed bias is applied to the input side of the low pass filter 2, the output is continuously changed and the central voltage to oscillate the fundamental frequency is obtained. Thus, the level difference does not occur at the phase and frequency of the output signal always in any case.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a PLL (phase locked loop) circuit that outputs a signal having a predetermined phase and frequency.

(Prior Art) Conventionally, this type of PLL circuit is configured as shown in FIG. That is, the reference clock 100 and the frequency-divided signal of the frequency divider 4 are input to the phase comparator 1, and their phases are compared. (The oscillator 3 adjusts the phase of its oscillation output signal so that the input difference becomes zero.This oscillation output signal is input to the next stage.) At the same time as it is output, it is input to the frequency divider, and the divided signal becomes the input signal of the phase comparator 1. Therefore, the signal output from the generator 1 is an output signal whose phase and frequency are constant.However, If an abnormality such as a momentary interruption of the clock 100 or a frequency fluctuation occurs in the above circuit, the frequency of the signal output from the oscillator 3 will also fluctuate, making the entire system using the above circuit unstable. There was a drawback.

Therefore, in the circuit shown in FIG. 3, a switch 5 is inserted between the LPF 2 and the oscillator 3 in order to avoid the above-mentioned problems. Normally, the switch 5 is switched so that the output signal of the LPF 2 is input to the oscillator 3. However, when the detector 6 installed on the output side of the LPF 2 detects an abnormality such as frequency fluctuation, this is input to the switch 5 so that the center potential E is supplied to the oscillator 3 via the switch 5. Switch to. This allows the output signal of the oscillator 3 to maintain its fundamental frequency even if there is a momentary interruption or fluctuation in the input clock 100. However, in this case as well, if the switch 5 operates, the oscillator 3
Since the input potential of LPF 2 changes rapidly and discontinuously from the output potential of LPF 2 to the center potential, the frequency of the output signal of oscillator 3 also varies discontinuously, and for a certain period of time after the switching, the above-mentioned effect is applied to the entire system. This will be affected by the output fluctuations of the PLL circuit.

<Problems to be Solved by the Invention> The above-mentioned conventional PLL circuit has the drawback that when a fluctuation in the reference clock occurs, this directly affects the output of the circuit, making the system unstable. Therefore, when the clock fluctuates, there is a method to avoid the above drawback by applying the center potential to the oscillator, but in this case as well, the center potential is switched discontinuously, so for a certain period of time after the above switching, the entire system is It had the drawback of being unstable. Therefore, the present invention aims to eliminate the above-mentioned drawbacks, and aims to provide a PLL circuit that can stabilize the system by always preventing steps in the phase and frequency of its output signal from occurring under any circumstances. There is.

[Structure of the Invention] (Means for Solving the Problem) The present invention has a comparison means for comparing the phases of a reference signal and an output signal, and a phase difference voltage obtained by smoothing the comparison result with a low-pass filter. In a PLL circuit that controls the oscillation frequency of the output signal so that the phase difference becomes zero based on the following, a detection means for detecting an abnormality in the output signal, and when the abnormality is detected by the detection means, the A configuration comprising signal switching means for inputting the output signal instead of the reference signal to the comparison means, and bias application means for applying a predetermined bias to the input side of the low-pass filter at least when the detection means detects an abnormality. have.

(Operation) In the PLL circuit of the present invention, the detection means detects an abnormality in the output signal and notifies the signal switching means of the abnormality. The signal switching means inputs the output signal instead of the reference signal to the comparison means when an abnormality is detected by the detection means. Thereby, the comparison means compares the output signals and outputs a result of zero phase difference to the low-pass filter. At this time,
The bias applying means applies a predetermined bias to the input side of the low-pass filter. As a result, the low-pass filter continuously changes its output to provide a center voltage that oscillates at the fundamental frequency.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the PLL circuit of the present invention. 1 is a phase comparator that compares the phase of the clock 100 and the frequency-divided output signal, 2 is an LPF that smoothes the difference between the phase comparators, 3 is an oscillator that controls the frequency of the output signal by a phase difference voltage, and 4 is an oscillator. A frequency divider that divides the output signal of 3, 5 outputs the reference clock to the next stage,
A switch that switches whether to output the frequency-divided signal from the frequency divider 4 to the next stage, 6 a detector that detects an abnormality in the phase difference voltage input to the oscillator 3, and 7 the input of the LPF 2 set to a predetermined voltage. This is a bias circuit for biasing.

Here, the detector 6 corresponds to a detection means, the switch 5 corresponds to a signal switching means, and the bias circuit 7 corresponds to a bias application means.

Next, the operation of this embodiment will be explained. Normally, switch 5
is switched so that the clock 100 is input to the phase comparator 1. Therefore, the phase comparator 1 normally has a clock of 100
and the frequency-divided signal output from the frequency divider 4, and the difference is smoothed by the LPF 2 and output to the oscillator 3. The oscillator 3 adjusts the phase and frequency of its oscillation output signal and outputs it so that the input phase difference voltage is zero. The frequency divider 4 divides the frequency of the output signal of the oscillator 3 and supplies the divided signal to the phase comparator 1. As a result, the oscillator 3 outputs an oscillation output 19 with a phase and frequency determined by the clock 100. In this situation, LPF
When the detector 6 detects an abnormality such as an extreme variation in the phase difference voltage of the two, it outputs this detection signal to the switch 5. As a result, the switch 5 selects the frequency-divided signal of the frequency divider 4 and inputs it to the phase comparator 1. Therefore, since the same frequency-divided signal is input to both input terminals of the phase comparator 1, the difference therebetween becomes zero. At this time, the bias circuit 7 operates and the LPF
The input side of 2 is set to a predetermined bias voltage.

Due to its time constant, the LPF 2 continuously shifts its output to the center potential after the predetermined bias voltage is applied to its input. As a result, the output of the oscillator 3 continuously and quickly changes the frequency of its oscillation output signal to the fundamental frequency after the abnormality is detected.

According to this embodiment, when an abnormality is detected in the output signal, the output signal (divided signal) is input to the comparator 1 instead of the clock 100, and the comparison result of the comparator at this time is The discontinuity of changes continuously depending on the time constant of the LPF 2, and finally the center potential is input to the oscillator 3. Therefore, the oscillator 3 can continuously set the frequency of its output signal to the fundamental frequency during the abnormality, and the entire system can operate stably. Also, input clock 10
Even if there is a momentary abnormality at 0, which is detected by the detector 6 and the switch 5 is switched to the output signal side, the influence of the momentary abnormality can be eliminated by the time constant of the LPF 2.

[Effects of the Invention] As described above, the PLL circuit of the present invention has the effect of making the system stable at all times by preventing any step in the phase and frequency of the output signal from occurring in any case.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the PLL circuit of the present invention, Fig. 2 is a block diagram showing an example of a conventional PLL circuit, and Fig. 3 is a block diagram showing an example of a conventional PLL circuit. The block diagram shown is shown below. 1... Phase comparator 2... LPF3... Oscillator 4... Frequency divider 5... Switcher
6...Detector 7...Bias circuit agent Patent attorney Noriyuki Chika Yudo Sanno Figure 1 Figure 2

Claims (1)

[Claims] oscillation of the output signal such that the phase difference becomes zero based on a phase difference voltage obtained by smoothing the comparison result with a low-pass filter; In a PLL circuit that controls frequency, a detection means detects an abnormality in the output signal, and a signal switching means inputs the output signal instead of the reference signal to the comparison means when the abnormality is detected by the detection means. and,
A PLL circuit comprising: bias application means for applying a predetermined bias to the input side of the low-pass filter at least when the detection means detects an abnormality.