JPH021074A - Picture reader - Google Patents

Abstract

PURPOSE:To surely actuate the title device synchronously with a picture reproducing device and to prevent an error in reading a picture by providing a feedback circuit to feed back the digital signal of the last bit out of plural bits to the picture reproducing device. CONSTITUTION:A timing generating circuit 102 in a control circuit starts the reading start of a CCD25, supplies a timing clock for driving main scanning to the CCD25, and outputs a clock pulse successively synchronized with the output of each picture element of 1024 picture elements of the CCD25 to a decoder circuit 103. As respective control signals of a reading mode, etc., selected by the picture reproducing device are inputted through an interface circuit to an 8-BIT shift register 126, the circuit 103 obtains a reading mode signal from an output terminal Qa of the 8-bit shift register 126, sets and changes the mode, and outputs the respective control signals accompanying the setting and the changing of the mode. The mode signal of this terminal Qa is fed back from a terminal 4 of a hand scanner input-output connector HC to the side of the picture reproducing device. Thus, the synchronization between both devices can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device used in an image reproduction device such as a word processor or a personal computer.

[Conventional technology]

Conventionally, this type of image reading device has a reading mode in which the image is enlarged or reduced, a dither control mode in which the image is switched between a simple binary image such as text, and a flattened image such as a photograph. An operating means is provided which can select a density control mode for adjusting the density of the output image, etc., and the image on the recording medium is read by changing the mode as appropriate depending on the image on the recording medium.

[Problem to be solved by the invention]

However, in recent years, image reproducing devices have not only been able to simply reproduce the image data read by an image reading device, display it on a CRTt', or print it out using a printer, but also perform further reprocessing such as enlarging or reducing the image data. There is a growing demand for the ability to reproduce the data after it has been performed.

For this reason, all of the above-mentioned operating means that were conventionally provided on the image reading apparatus can now be performed on the image reproducing apparatus.

However, if the compatibility between the image playback device and the image reading device is even slightly poor, the timing of the signals often does not match, and the image reading device cannot receive the foot roll signal output from the image playback device, resulting in reading errors. Something happened.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and its main object is to provide an image reading device in which an image reproducing device and an image reading device operate reliably in synchronization and do not cause reading errors.

[Means to solve the problem]

In order to achieve the above object, the present invention is connected to an image reproducing device, slides and scans a recording medium, and converts the image on the recording medium into multi-bit digital data from the image reproducing device. In an image reading device that outputs image data read by an image sensor according to a signal, a feedback circuit is provided for feeding back a digital signal of the last bit among the plurality of bits to the image reproducing device.

<Configuration> The hand scanner 1 shown in FIG. The width of the grip 3 is narrow and the width of the head 5 is wide so that it is easy to grip and operate.

As shown in FIGS. 4 and 6, the lower cover IA has a lip 60 that contacts the original 8SP, a reading port 11,
An arc-shaped shielding plate 61 that accommodates the row 217 and a plurality of glue pros 3 are provided.

The reading port 11 is covered with a platen glass 12 as shown in FIG.

The upper cover IB is provided with a viewing window 13 through which the state of the original 8IP can be seen through the reading port 11, and a light shielding protrusion 14 formed on the rear periphery of the viewing window 13.

The viewing window 13 is covered with a colored (smoked) transparent synthetic resin 13' such as glass or acrylic. When looking through the viewing window 13, for example, the roller 17 (described later)
The position that can be seen in front of the arc-shaped shielding plate 61 that houses the camera is read and set as the reference position.

Incidentally, even if external light directly enters through the viewing window 13, it is tilted toward the C0D25 side so that the reflected light does not enter the C0D25, which will be described later, so that the reflected light is reflected toward the light source side.

As shown in FIGS. 2, 4, and #S6, the hand scanner 1 having such a shape includes a roller 17 made of rubber or the like that contacts the document P and rotates around a rotation shaft 15, and a document A light source that irradiates light to P, for example, an LED 7 ray 19 that emits green light (red light or the like), a reflector 21 such as a mirror that reflects light from the document, and light from this reflector 21 is input. image input unit 2 that converts light into electrical signals
2, a reading start button 39, and a control board 27.

The roller 17 is provided between the LED array 19 and the image input section 22, and is lower than the optical path between the reflection plate 21 and the image input section 22.
It protrudes higher than the straight line connecting the entrance to the document, focuses on the document surface, contacts the document surface, and rotates as it moves on the document surface.

A gear 29 is attached to the rotating shaft 15 of the roller 17 as shown in FIGS. 2 and 4.
The clock plate 35 is driven as the roller 17 rotates. The clock plate 35 has a plurality of holes arranged at equal intervals on a concentric circumference, and an automatic interrupter 37 detects the amount of rotation, and the amount of linear movement of the hand scanner 1 that slides on the document by manual operation. can be captured as a position signal.

The gears 31, 33 and the clock plate 35 are supported by a support member 45. The support member 45 includes left and right side plates 47L and 47R, as shown in FIGS. 8 to 10.

The side plate 47L is a support bin 4 that rotatably supports the gear 31.
9, a support stepped portion 53L1 forming one bearing of the rotating shaft 51 of the gear 33 and the clock plate 35, and a 7-m 55L.
It is equipped with

Further, the side plate 47R includes a support step portion 35R and an arm 55R that form the other bearing of the rotating shaft 51.

In addition, the arms 55L and 55R are elastically deformable, and the rotation axis 5
1 can be attached and detached.

The LED array 19 and the reflection plate 21 are attached to a seven-frame frame 69 that is inclined at, for example, 45 degrees with respect to the original P, as shown in FIG. This 7 frame 69 has both side parts 69 L * 69 R attached to the lower cover IA with screws 7 as shown in Fig. 2.
It is fixed at 1.

The image input unit 22 includes a lens unit 23 that collects light from the reflection plate 21, and an image sensor such as a CCD 25 (line sensor) that receives the light collected by the lens unit 23 and converts it into an electrical signal. Be prepared.

When the reading start button 39 is pressed, the sub-scanning detection circuit 112 becomes the 7th mark, and the 7th interrupter 3
The position signal of the hand scanner 1 detected by the hand scanner 7 is now detected.

The control board 27 includes the CC as shown in #S11 (A).
D25, the timing generation circuit 102, and the intermediate r! by the dither pattern. 4 Decoder circuit 1 for reading
03, a video amplification circuit 104, an envelope detection circuit 105, a division circuit 106, a switching circuit 107 for reading characters (simple binary) from a halftone reading state of a photograph, etc., and a shading amount. By selectively connecting the correction circuit 103 and the terminals J1 to J4 by the decoder circuit 103, a voltage drop is applied to the reference 5V of the common terminal v109, and a voltage value corresponding to each dither value is set. and t
Eight 7-lip prop circuits are connected in series, as shown in the diagram J44S and the timing chart shown in FIG. 46. Serial input with date inputs information signals selected by external connections such as mouse operation, and input from a reset circuit installed in the image reproduction device by asynchronously turning on the power of the image reproduction device such as a word processor or personal computer. A reset signal is input from the clear terminal, clearing the output state up to that point and resetting the outputs of output terminals Qa to 11 to O or low level L. Which is the other (
Or, by setting the “L” level to 4 to 4 (both), data input is prohibited, and the first 7 lip props are reset to the “L” level with the next clock pulse, and the one-man power is set to the “H” level. enables the other inputs, and the next clock pulse inputs data into the first 7 lip props.
6, and a density control circuit 110 that adjusts the image density to 32 levels by the density signals outputted from the terminals Qd-Qh via the 8-BIT shift register in response to signals from an image reproducing device such as a word processor/panfun. , the current-voltage conversion circuit 111, the sub-scanning detection circuit 112, and the outputs from the terminals Q b - Q c of the 8-BIT shift register, similar to the density control 110, are used to control the Bayer, spiral, and halftone halftone modes. a dither control circuit 113 that selects a pattern and controls the dither matrix resistance circuit 109 via a decoder circuit 103; a read mode selection circuit 114; and a CCD 2.
A comparator 12 that outputs the image data read in step 5.
5, and is attached to the lower cover IA with pins 65 and screws 67 as shown in FIG.

The timing generation circuit 102 starts the reading of the CCD 25, supplies a timing lock (main scan start pulse) for driving the main scan to the CCD 25, and sequentially synchronizes with the output of each one of the 1024 pixels of the CCD 25. The clock pulse (timing pulse for reading the video signal) is output to the decoder circuit 103.

The decoder circuit 103 is connected to an image reproducing device P such as a personal computer/word processor via an interface circuit I/F to be described later.
Reading mode selected by C/WC (1x mode/
reduction mode) dither control (character [simple binary],
Control signals such as payer pattern, spiral pattern, halftone dot pattern), density control (32 density levels) are input to the 8-BIT shift lens star 126 via the terminal of the interface circuit I/F, and A reading mode signal is obtained from the output terminal Qa of the 8-BIT shift register to change to the same size or 1/2 reduced image mode, and a dither control signal is obtained from the output signals Qb and Qc via the dither control circuit 113. When reading a character image, the potential of the output terminal JO is changed, the transistor Q1 of the envelope detection circuit 105 is turned on, the capacitor C2 is placed in parallel with the capacitor C1, and the image judgment reference value is changed.
The dither matrix resistor circuit 109 is controlled by the output terminals J1 to J4, and the output terminals Qd to Qh of the 8-BIT shift register 126 are used to control the dither matrix resistor circuit 109, respectively, by grayscale signals expressed in 5 bits from the image reproduction device PC/WC. 5 of the grayscale control circuit 110
The output potential 109 of the dither matrix resistor circuit 109 is changed using two resistors according to the 32-step gray level value, and JO is selected when taking a photo, and J1 to J4 are selected when a dither matrix is selected. Each switch is switched to the ground side depending on the matrix.

The video amplification circuit 104 includes resistors R1 to R5, variable resistors VRI and VR5, and tbear:z;/121, 122, and inputs the video signal A of C0D25 and outputs the amplified signal B.

The envelope detection circuit 105 includes a diode D1, capacitors C1, C2, transistors Q1, Q2, and resistors R6, R8, R9, and receives input from the image reproduction device NPC/WC via the capacitor C1 and the interface I/F. 8-BIT
In response to the state of the output signals Qb and Qc of the shift register 126, the output terminal JO is made to respond in accordance with the signal input to the a terminal of the decoder circuit 103, and the switching circuit 1
The envelope is detected using a time constant determined by the capacitor C2 and the resistor R6, which are connected and separated via the capacitor C1 and the resistor R6, or by a time constant determined by the capacitor C1 and the resistor R6.

The envelope dividing circuit 106 includes a resistor R7, a variable resistor -VH2, and an amplifier 123, and divides the envelope detected by the envelope detecting circuit 105 into voltages to determine the shading correction width.

The switching circuit 107 is connected to the image reproducing device PC as described above.
/WC, and the state of the output terminals Qb and Qc of the interface circuit 8-BIT shift Renoster 126 is used to switch between the text mode and the photo mode.

The shading amount correction circuit 108 includes a variable resistor VR3, and determines the amount of correction for the shading correction output E.

The dither matrix resistor circuit 109 changes the pseudo-binary reference voltage shown in the photograph, and includes a resistor ".~r3, which is connected to the ground or 5" in the decoder circuit 103 by a semiconductor switch.

In addition, the resistance r0 ~ ", is, for example, ro = 8 x r3
, r+==4Xrl, r2=2Xr=.

The density control circuit 110 is an image reproducing device PC/W.
8-BIT shift register 1 via the interface circuit I/F according to the 5-bit gray signal selected by C.
It is controlled by 26 output multipliers Qd-Qh, and the density level is adjusted in 32 steps.

Further, the density control circuit 110 has a resistance value of 2'R.
An inverter IN is interposed at one of the output terminals, in this case, the output terminal Qh, and the five resistors set at t' are connected to one of the output terminals, in this case, the output terminal Qh.
This inverter IN activates the grayscale control input method described later, that is, the image reproduction 1fiPc/WC,
At that time, in the initial state, consideration is given so that the potential 109 of the output terminal of the dithering circuit 109 does not change excessively.

In other words, the current i flowing through this concentration control circuit 110 becomes 1 (as shown in FIG. 47), for example, 00
When receiving a digital signal of 001 (left end in the figure), Qh
The output of is softened from H level to level by the inverter, the output level of all output terminals Qa-Qh becomes L level, and the terminals of output terminals Qd-Qh fall almost to ground (:OV), so at that time The combined resistance is 1/(1/r+ 1/2r+1/4r+ 1/8r+
1/16r) = 1/[(16+8+4+2+1)/
16・1/“1=1/(31/16・1/r)=16/31r :0.52r.

Also, when inputting the central 11111 denotal signal to Q d −Q l+, only the output terminal Qh is grounded (:O
(2), and the other voltages v109 are maintained at almost the same potential, so the combined resistance at that time is 1/+=r.

Furthermore, when a digital signal of 11110 (right end in the figure) is input to Qd-Qh, all of the output terminals Qd-Qh become H level and no potential is generated between each resistance, so the combined resistance at that time is: It becomes infinitely large.

The power supply i of the density control circuit in each case is =V. , /r0.

Therefore, the current i flowing through the concentration control circuit 110 is changed to adjust the current 10 of the current-voltage conversion circuit 111, which is a composite current of this current i and the current of the decoder circuit 103 via the dither matrix resistor circuit 109. As a result, the output voltage of the current-voltage conversion circuit 111 is changed by 5 V + io-R0, and the threshold voltage of the binarization converter 125 is adjusted.

The current-voltage conversion circuit 111 includes an operational amplifier 124, a resistor R12, and a variable resistor VR4.
A comparison voltage F having a value obtained by multiplying the value of the current flowing from one side to the ground by the sum of the resistor R12 and the variable resistor VR5 is output.

The sub-scanning detection circuit 112 is a circuit that generates a pulse when the paper is fed in a direction perpendicular to the scanning direction of the CCD 25 or when the rotation of the roller 17 is detected and moved by an arbitrary amount. Occur.

The dither control circuit 113 controls the interface circuit I/C in response to the bibium dither control signal selected by the image reproduction device ff1Pc/WC as described above.
It is controlled by the output terminals Qb and Qc of the 8-BIT shift register 126 via F, and depending on the state, connects JO and J1 to J4 to ground or 5.

As described above, the reading mode selection circuit 114 selects an
- The decoder circuit 103 is controlled according to the output state of the output signal Qa of the BIT shift reno star 126.

That is, when the output terminal Qa of the 8-BIT shift register 126 is 1 (high level: H), the decoder circuit 103 applies changes in the dither matrix to each bit in the main scan via the read mode selection circuit 114. On the other hand, it is changed for each effective line in the sub-scanning.

That is, as shown in the circuit diagram of FIG. 50, by switching the voltage level of the X terminal of the decoder circuit 103 to high (I) or low (L), 1 in FIG.
1-scan side timing chart and Fig. 51 (B)
As shown in the timing chart on the main scanning side of , when the sub-scanning judgment output and the main scanning judgment output are output and one pulse is generated from the sub-scanning judgment output, the matrix in the line direction of the dither in the sub-scanning direction becomes 1. One change is made. Furthermore, when one pulse is generated from the main scanning determination output, the matrix in the main scanning direction of the dither CCD changes by one.

Therefore, if you want to reduce an image to 1/2, when reading, if the voltage level of the , which is 4×4 at the same size, is
The size will be doubled to 8×8.

In other words, as shown in FIG. 52, by selecting the 1/2 reduction mode, the 4×4 halftone dot pattern
The dither pattern shown in the figure is obtained.

Image data read using this pattern, for example,
In the state shown in Fig. 54, the part marked with ☆ in Fig. 55, I:l
By removing the part marked with ◯ in Fig. 553 and reducing it to 1/2, the dither pattern becomes the same as the 4×4 dither pattern, and there is almost no change in density.

Further, FIG. 56 shows the image state obtained depending on how data is taken during reduction.Incidentally, in the above case, the image state is shown in FIG. 56a.

The binarization comparator 125 converts the amplified signal B of the video signal A and the binarized comparison voltage F into black and white.
Perform value conversion.

In addition, when reducing, the read binarized image is divided so that one section has an even number of pixels, and each even numbered pixel is made into one reduced pixel, and the reduced pixel is binarized into the even numbered pixels. On the other hand, the binarization of this reduced pixel is performed by setting as many pixels in advance as the pixel of interest to determine the binarization state in each of the above-mentioned sections. If the numbers of the two types of even-numbered pixels are equal, the binary state determined by the pixel of interest is determined and set.

In other words, if there are the same number of black and white pixels, if the pixel of interest is black, it will be black;
If it is white, set it to white.

For example, in the case of 1/2 reduction, the upper left position is temporarily set as the pixel of interest, as shown in Figure 58.

The midtone area now has 5 levels, which is much wider than the 3 levels explained previously. Concentrations also vary at intermediate levels.

Also, in order to improve the reproducibility of thin lines, instead of making the position of the pixel of interest constant such as only the top left position, a pattern is created in which the thin line falls on one of the pixels of interest no matter where it passes (Fig. 57). If you intersperse the pixels of interest like this, the feeling of a thin line will remain.

HC is a hand scanner human output connector, and the signals shown in FIG. 18 are inputted or outputted from terminals 1 to 8, respectively.

Incidentally, the CCD 25 mentioned above is a charge coupled device (Charge coupled device).
), which is an element that transfers and transports charge from one capacitor to another, and is generally called a charge transfer element. Figure 20 shows the basic block of C0D25, which consists of a large number of minute 7t It consists of a charging conversion section made of a diode, a transfer section for reading out signals, and a buffer amplifier for impedance conversion. In addition, some products are equipped with drivers and output signal processing circuits.

As shown in Figure 20, a CCD image sensor uses many minute diodes to convert light into electrical strengths, which are sequentially read out by the CCD, and can be connected to other circuits using a buffer amplifier. It can be said to be a device that outputs impedance.

Further, as shown in FIGS. 21 and 22, the CCD 25 has a photoelectric conversion section. Light enters through the N layer on the surface and generates charges mainly within the depletion layer of the PN noyankushishin. This charge converter has been charged in advance with a reverse bias voltage, so the charges are generated by the light. The generated charge flows as reverse leakage of the diode, discharging the charge stored in the shank capacitance.Therefore, the charge conversion section consists of a capacitor and a resistor whose resistance value changes depending on the light, as shown in the broken line circle. You can think of replacing it.

As shown in Figure 22, when charging the charging converter, the signal input from the charging converter to the CCD directly charges the charging converter. However, as shown in Figure 22,
Since the capacitor is charged by a capacitor, it seems that the level after charging will be uneven depending on the signal level before charging on the charging element side. After the output, it is considered that the level remains the same, and at that time, it is assumed that the readout transistors Q, ~Q, are short-circuited between the transfer part bit and the corresponding charging element, and each charging element after charging is The levels are different for each, and at this time, if the date voltage of the transistor is applied appropriately (so that the source voltage becomes the date voltage (drain voltage)) and the transistors Q1 to Q are considered to operate as source 7 lower, all photoelectric conversion will be charged to the same level.

In addition, as shown in Figures 23 and 24, there are two-phase, three-phase, and four-phase drive methods for the COD signal transfer section, but the dimensional image sensor is
Basically, most are 2-phase drive.

Although the internal structure differs slightly depending on each drive method, two-phase drive CCDs usually have a potential diagram like the one shown in Figure 23. The signal charge indicated by is sent from left to right.

Also, if this is expressed as an equivalent circuit, it will be as shown in Figure 24.

The operation of this transfer section is as follows.

As shown in FIG. 25, FIG. 26, and FIG. 27, the transfer state is shown in FIG. 25! Terminal I
is 12V and terminal ■ is in ov state.

If all capacitors C7 to C4 are fully discharged,
In this way, all transistors are turned off.
In this state, apply voltage externally to point A and lower it by 1v to II.
When set to V, all transistors remain OFF.

Next, in Fig. 26, terminal ■ is ov, terminal ■ is 12
Let's set it to V. Initially, point A is -1V and point C is 12V.
When Qll+ becomes ■^<VB, current flows from ONL and point Cl11 to capacitor C1. Qb++Qat is OFF.

When point A becomes 0■ and ■^=VB=OV, Qal
Yes, it turns off quickly (it turns off, this operation is the 22nd
It is the same as the transistor in the figure.If C1 and 02 have the same capacitance, the voltage at point A increases by the same amount as the voltage at point CI! The voltage will drop, so the voltage at point C will be 11v.

This is the great thing about Qal; with a simple switch, V^ = VC = 5.5V.

Next, in Fig. 27, terminals I and ■ have returned to the state shown in Fig. 25, but point A has suddenly returned to 12V, and instead becomes Qb+, exactly as what happened to Qal in Fig. 26. The same thing is happening, and in the end, point E becomes IIV.Looking at it this way, the 12V initially applied to point A, C is not a voltage applied externally, but is built into the element. ing.

Further, as shown in FIG. 28, the CDD 25 includes a buffer 7 amplifier section, and this 8777771 section receives the transferred signal charge in a capacitor C, and converts the voltage change generated there into Q2. It outputs from the source 7 lower of Q, and some have an amplifier or waveform shaping circuit after this. The source load of the 7-slower varies depending on the type of CCD.
It can be a constant current source or a resistor.

Q, when signal charges are sent one after another from the CCD,
Since capacitor C will overflow, the purpose is to cancel the previous signal and return the charge amount of capacitor C to a constant value before the next signal arrives.Therefore, it is normally OF.
F is turned on, but it is turned ON just before the next signal is output. Then, positive charge corresponding to the negative charge flowing from the CCD flows through Ql, and the charge amount of capacitor C returns to the specified value. .

→The change in 11v passes through point C and is sent to point El:lle.

In this embodiment, a drive circuit is built-in, and the TT
It can be directly connected to L, has high blue sensitivity due to the PN junction structure of the light receiving part, can be operated with a 12V311-power supply, has 1024 elements on one chip, and has an output signal amplifier and sample-and-hold circuit built-in. , a one-dimensional image that can receive light with a resolution of 8 originals/-102
It consists of a 4-bit photoelectric conversion section, a 525-bit CCD charge transfer register on each side, and an output amplifier.The charge conversion section has a PN connection and a V# connection, and the charge transfer register has a buried channel type structure with high transfer efficiency. The part is 14μ theory ×
9μ- and separated by 5μ ring channel stops.

Also, Figures 29 to 36 show the CCD used in the example.
2S internal block diagram (Figure 29) and terminal connection diagram (Figure 3)
0 figure), drive pulse timing chart figure ($31 figure ~
Figure 34), drive circuit diagram (Figure 35) and binarization circuit (
Figure 36) are shown respectively.

15, 16 and 17 show the hand scanner 1
The input/output connector and one end side or the other end side is the image playback 11
11i! This is an interface circuit 17F connected to the PC/WC, and can be roughly divided into J-, which is composed of a general preset, a complementary output Q, and a latch circuit consisting of 70 loops in Fig. 15. R
CI~RCII.

It has an 8-BIT shift register CR and eight 7-lip 7tt-/p, divide-by-1
A counter circuit CD consisting of two sets of 6 counters.

8 pieces of Etsunotori-D type 7 riffs 70 flops circuit F
F1, output board circuit OPI, which constitutes the path drive circuit BD and consists of eight 8771 circuits in FIG.
A current circuit consisting of a D type 7 riff 70 tube circuit FF2 and a voltage stabilizing IC of a voltage regulator circuit VR is constructed, and FIG. 17 shows which control unit on the image reproduction device PC/WC side the hand scanner 1 is connected to. According to the conditions of three select inputs and three input inputs to determine
It is composed of a 3-to-8 line decoder LD that decodes one of the 8 output lines, a bus drive circuit BD1, a Guilecum clear, a Guilecum preset, and complementary outputs Q and Q, and the input data is the rising edge of the flock pulse. It is composed of an address setting circuit consisting of a 7-lip 70-circuit FF3 which is transmitted to the output by a circuit γ.

Note that HC in FIGS. 15 to #S17 is the hand scanner input/output connector in FIG. 11, and each numerical value has a one-to-one correspondence.

Further, PC/WC indicates an input/output terminal determined by the address setting circuit (FIG. 17) of the interface circuit I/F in order to connect the hand scanner 1 of the image reproduction device.

Therefore, first, latch circuits RC1 to R in Figure 1515
CII is connected to the star F pulse output terminal that starts the main scanning of the CCD 25 at the terminal 3 of the connector terminal HC of the hand scanner 1, and the sub-scanning signal output terminal generated by the sub-scanning detection circuit 112 at the terminal 7, It is reset by the main scanning start pulse, and one of the sub-scanning detection circuits 112
The image data latched by the scanning signal and input to the shift register CR for inspection is determined to be a valid image, and the image data is directly transferred to the memory of the image reproduction device PC/WC.

Incidentally, the 8-BIT shift register CR is similar to the shift register previously explained in 45th shift C/FIG. 46,
It receives signals from the image data output terminal 2 of the terminal 6 of the input/output connector HC of the hand scanner 1, the timing pulse output terminal for reading the video signal of the terminal 5, and the counter circuit CO, and in this case, it outputs image data every 8 bits. While shifting, the data is transferred to the image reproduction device fftPc/We.

The CCD 2S is composed of 1024 bits, and after each 8 bits are transferred 128 times, the next line is read.

The counter circuit CO is connected to the video signal reading timing pulse output terminal of the terminal 5 of the input/output connector HC of the hand scanner 1, calculates the reading timing pulse, and outputs an output signal every 8 bits to the shift register CR. , transfer control of the image data to be input to the SH7 TRENOSTER CH to the image reproduction device PC/WC in units of 8 bits.

The output boat circuits OPI and OF2 are composed of a bow circuit and are selected by the image reproduction device PC/WC.

Generate control data (FIG. 19), which will be described later, and send it via the terminal 8 of the input/output connector of the hand scanner 1.
This controls the control circuit of the hand scanner 1 shown in FIG.

Also, Figure 18 shows the terminal names and 8! of the input/output connector of the hand scanner. Figure #S19 shows the image reproduction HM
Operated by P C/W C, generated by output port circuits OPI and OF2 of interface circuit I/F, and terminal 8 of input/output connector HC of hand scanner 1.
This is a motor rotor that is input to the 8-BIT shift reno star 126 of the control circuit shown in FIG.

Operation> First, use an image reproducing device PC/WC such as a word processor or personal computer.
The hand scanner 1 is connected to the camera via the interface circuit 1/F, and the power of the image reproduction device rIIPc/WC is turned on.

Then, press the PC/WC keyboard or C on image playback.
On the mouse input selection board displayed in the RT, select each mode shown in Figure 19, set each mode of hand scanner 1, and set it to run or start mode, then power on hand scanner 1 as well. is added, and the LED 7 ray 19 in FIG. 4 emits light. Then, while turning on the reading start button 39, hand scanner 1
When pulled, as the roller 17 rotates, the sub-scanning detection circuit 1
A pulse is supplied from 12 to the decoder circuit 103.

On the other hand, the timing generation circuit 102 shown in FIG.
D25 is driven to convert the light input through the reflection plate 21 into an electrical signal. The signal is output as video signal A.

Video signal A is amplified by video amplification circuit 104. This amplified signal B is directly passed to the binarization comparator 1.
25 and an envelope detection circuit 105 for shading correction of the video waveform.

In the previous operation, the envelope detection circuit 105 is switched between simple binary and pseudo-binary, in other words, text and photographs (or dither method), by the image reproduction device PC/WC.
The time constants for envelope detection are switched to C102 and R6 for text, and to C1 and R6 for photos. Therefore,
The output C of the envelope detection circuit 105, whose time constant is smaller for photographs than for letters, is output by the Volteno 7-year-old lower.

This output is divided into an output E having a certain ratio by a variable resistor VR2, and is supplied to an operational amplifier 124 through a variable resistor VR3.

The shading amount correction circuit 103 determines the amount of correction for the shading correction output E.

A current-voltage conversion circuit 111 and a shading amount correction circuit 1 that supplies current to the current-voltage conversion circuit 111.
08, a dither matrix resistor circuit 109 for changing the reference voltage at the time of photography, and a density control circuit 110, a binarized frequency voltage F is obtained.

The output from the decoder circuit 103 to the resistors r0 to r of the dither matrix resistor circuit 109 is output to the dither pattern by the 8-BIT shift Renoster 126 when the photo so-called dither mode is selected in the image reproduction device PC/WC. It is switched to cause voltage fluctuations like a). At this time, the pattern change in the main scanning direction is synchronized with driving of the CCD 25 of the timing generation circuit 102, and the pattern change in the sub-scanning direction is performed according to the clock from the sub-scanning detection circuit 112.

When the simple binary value is selected by the image reproducing device PC/WC, a predetermined pattern, in other words, a fixed offset voltage is applied to the humval rate voltage F. This determined value is the image reproduction device f? 2Pc/W
Ct' selection Z is determined by the dither control circuit 113 controlled by the output of the 8-BIT shift register 126.

Furthermore, the movement of the dither pattern in the dither mode is modulated by the decoder circuit 103 according to the read mode, as described above, by the output of the read mode selection circuit 114.

As explained earlier, the comparator voltage F for binarization is a current flowing into the shading amount correction circuit 108 in FIG. Determined by value.

If the image that becomes the video signal in Figure 12 is processed using the time constant of character shade envelope detection, the result will be 0 as shown in Figure 13.
When the time constant is large, when a large area of intermediate color of the same density is read, the density of the output image changes as the scan bits of the main scan advance within the intermediate tone area.

On the other hand, if the image shown in FIG. 12 is processed using the time constant of the photo mode, or in other words, if the time constant is made smaller, the image shown in FIG. 14 will be obtained.

If the colors are the same in the middle tone area, they should be output with the same density. However, in reality, when shading correction using an envelope is performed, even if the time constant is made small, a changing area as shown in Figure #414 appears (it is better to make this as narrow as possible.) , select either text mode or photo mode to read.

In this case, when reading in text mode, the neutral colors do not appear in the photo area. Also, when reading in photo mode, it becomes difficult to see the lines of the characters.

The image data output from the comparator 125 is output from the terminal 6, the main scanning start pulse for starting the main scanning of the CCD 25 is transmitted from the terminal 3, the timing pulse for reading the video signal is transmitted from the terminal 5, and the sub-scanning detection circuit 112
The sub-scanning signal generated by
It is input to the interface circuit 1/F shown in the figure.

This interface circuit I/F first starts with a latch circuit RC by a main scanning start pulse input from terminal 3.
I to RCII are reset and latched by the sub-scanning signal of the sub-scanning detection circuit 112 input manually from the terminal 7, so that the image data read by the CCD 25 and output from the comparator 125 is transferred from the terminal 6 to the shift register CR. The counter circuit CO counts the timing pulses for reading the video signal that are captured and simultaneously input from the terminal 5, and the image data, which is shifted every 8 bits to the shift register CR, is transferred to the image reproduction unit 11fffPc/W.
Transfer directly to C memory.

This transfer is performed 128 times for every 8 bits, that is, 1 line of 1024 bit image data is transferred. This transfer operation is repeated synchronously while determining the validity of the image data based on a sub-scanning signal generated by manual scanning, and the image on the document is read.

In FIG. 37, when the reading start button 39 is pressed, the sub-scanning detection circuit 112 is activated and the decoder circuit 103 is activated.
And from the terminal 7 of the hand scanner human output connector HC, the latch circuit RCI of the interface circuit I/F
A position detection signal LP for detecting a reading position synchronized with the rotation of the roller 17 by manual scanning is generated and input to the RCII.

38th U! i is input by the image reproduction device flPc/WC at 300 mst from power on? ) A signal for controlling the hand scanner 1 is sent to the terminal of the input/output connector HC of the hand scanner 1 via the output port circuit OPI and the D type 7 lift circuit FF2 of the interface circuit I/F shown in FIG. 8th, 19th
The signals shown in the figure are transferred in the order from A to H, and these signals are transferred to the control circuit 8-8 of the hand scanner 1 shown in FIG.
Each mode is set for processing by the BIT shift register.

39 and 41 show the relationship between the sub-scanning signal LP, the main-scanning start pulse SP of C0D25, and the timing pulse WR for reading image data (video signal) vSS and 1 video signal in the same-magnification mode. be.

FIGS. 40 and 42 show the relationships among the above signals in the 1/2 reduction mode.

Figure 43 shows how to process -line image data in the same magnification mode, and Figure 44 shows how to process -line image data in 1/2 reduction mode.

Further, after the reading is completed, by turning off the reading start button 39 of the hand scanner 1, the sub-scanning signal of the g11 scanning detection circuit 112 is stopped.

Then, as shown in FIG. 49, the image reproduction device rfI
A pulse monitoring routine using a subroutine for repeatedly detecting changes in the sub-scanning signal LP (position detection signal) of the sub-scanning detection circuit 112 consisting of an instruction circuit provided in the control software of the PC/WC is provided,
The number N of executions of this subroutine is set in advance to a predetermined number of times, and reset every time an image is read.If the sub-scanning signal is stopped in this way and the LP small output high level (H) state is maintained, The subroutine is executed, and when a predetermined number of times is reached (N=O), the software determines that reading is complete, outputs a reading completion signal, and stops reading.

Alternatively, as shown in Fig. 48, a pulse monitoring circuit using a timer circuit is provided in the interface circuit that transfers the image from the image sensor on the hand scanner side to the image reproducing device, and a pulse monitoring circuit using a timer circuit is provided. Detects the fluctuation time, detects the completion of image reading, and outputs it to the image reproducing device PC/
WC reading operation stops.

In addition, in FIG. 11, the reading mode signal which is the output of the output terminal Qa of the 8-BIT shift reno star 126 is transmitted from the terminal 4 of the hand scanner human output connector HC to the image reproduction device ff1P via the interface circuit I/F.
It is fed back to c/WC and the image reproduction device aPC
/ Characteristics of WC and reasons for the scanner 1 1Iiii
This allows k4 to be constantly monitored.

Furthermore, the image data is transferred to the interface circuit T/F.
Image playback device without H memory! lPC/W
By storing the data in memory in C, the reading status can be quickly checked and displayed on the CRT"ch.

〔Effect of the invention〕

As explained above, according to the present invention, the device is connected to an image reproducing device, is slidably scanned over a recording medium, and images on the recording medium are generated according to multi-bit digital signals from the image reproducing device. In an image reading device that outputs image data read by an image sensor, a 7-doppack circuit is provided to feed back a denotal signal of the last bit among the plurality of bits to the image reproducing device, and the denotal signal transferred to the image reading device is By receiving the last bit of the image with the image reproducing device RA, it is possible to confirm that the image reading device has reliably received the signal, and it is also possible to check compatibility with the image reading device to be installed.
Image processing without reading errors is possible.

[Brief explanation of the drawing]

#S1 to FIG. 58 show an embodiment of this invention, and each figure represents the following. Figure 1 is a top perspective view of the hand scanner, Figure 2 is a diagram showing the internal structure of the hand scanner, Figure 3 is a bottom perspective view of the hand scanner, Figure 4 is a sectional view of the hand scanner, and Figure 5 is a diagram showing the internal structure of the hand scanner. The left side view of the hand scanner, Figure 6 is a sectional view of the hand scanner, Figure 7 is the right side view of the hand scanner, Figures 8 to 10
The figure shows the structure of the gears 31, 33 and the supporting members of the clock plate 35, Figure 11 (A> is the control circuit diagram, and Figure 12 is the envelope detection waveform diagram when the time constant is changed for the video signal. , Fig. 13 is a waveform diagram showing changes in the video signal and comparator voltage when the time constant is large, Fig. 14 is a waveform diagram showing changes in the video signal and comparator voltage when the time constant is small, Fig. 15 ~Figure 17 is the interface circuit diagram, Figure 18
The figure shows the hand scanner's input/output connector name table, Figure 19 shows the control data table, Figures 20 to 36 explain the CCD, Figure 20 shows the basic block of COD, Figure 21,
Figure 22 is a diagram for explaining the photoelectric conversion section of the CCD, Figures 23 and 24 are diagrams for explaining the signal transfer section of the COD, and Figures 25, 26, and 27 are diagrams for explaining the signal transfer section of the COD. Figure 28 is a diagram to explain the transfer state of the signal transfer section of the COD, Figure 28 is a diagram to explain the buffer 7 amplifier section of the CCD, Figure 29 is an internal block diagram of the COD, Figure 30 is the terminal connection of the COD. Figures 31 to 34 are CCD drive pulse timing charts, Figure 35 is a COD drive circuit diagram, Figure 36 is a COD binarization circuit diagram, f: 1% Figures 37 to 44 Each shows a timing chart. FIG. 45 and FIG. 46 show a circuit configuration diagram of the shift reno star and its timing chart. The ts47 diagram is a characteristic diagram showing changes in current from each shift reno star with respect to digital signals caused by the concentration adjustment circuit. FIGS. 48 and 49 are 70-charts of the reading completion detection means. 50 and 51 (A) and (B) are a dither pattern modulation circuit and its timing chart. FIGS. 52 to 56 are diagrams showing dither patterns and image processing data. FIGS. 57 and 58 are image pattern diagrams for explaining an image reduction method. 1...Hand scanner 11...Reading port 13
...Peep window 17...Roller 19...
LED array 21 Reflector plate 22... Image input section 23... Lens unit 25... CCD
61... Shielding plates RCI to RCII... Latch circuit CR... Shift register CO... Counter circuit ☆... Engraving of the drawing of the pixel of interest Patent applicant Nippon Seimitsu Kogyo Co., Ltd. Figure 2 Figure 8 7 Figure 1O Figure 12- Figure DC voltage to open voltage Figure 18 Figure 19 Figure 20 Figure 22 Figure Z, j Figure 28 Figure 30 No. fPI37 Source reading button 39-- -------v-----LP signal Fig. 38 t → CKQ uuuulU口□ \ > Fig. 39 Fig. 40 LPINT: Sub-scanning period (every 1/4-1) Fig. 41 t, : sp pulse width t2: WR pulse width t, : data setup time (WR↑) t4: data retention time (vs. WRT) ts: 5P-WR delay time TINT: W integrated time ; 5.33 usec ; 333 nsec '; 2.33 usec ; 333 nsec ; 73 usec, 2.8 m5 ec WR↑) t, :5P-WR delay time TINT:W integrated time ; 5.33 usec ; 333 nsec : 2.33 usec : 333 nsee ; 76 usec ; 2.8 theorySee Figure 43 Figure 44 Figure 48 Eνe Figure 49 (cl) gf! Figure 5 + Figure f5 Figure 57 Procedural Amendment Form % Formula % Display of the Case Patent Application No. 686 No. 2 of 1983. Title of the invention Image reading device 3, Person making the amendment Related to the case Patent applicant Address 3167-6, Yamamiya-cho, Kofu-shi, Yamanashi Prefecture The detailed description and drawings of the amendment will be printed as attached.

Claims (1)

[Claims] The device is connected to an image reproducing device, slides and scans the recording medium, and outputs image data by reading the image on the recording medium with an image sensor according to a multi-bit digital signal from the image reproducing device. 1. An image reading device comprising: a feedback circuit for feeding back a digital signal of the last bit among the plurality of bits to the image reproducing device.