JPH02106965A - semiconductor storage device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Prior Art] A read-only memory device (hereinafter referred to as ROM), which is a type of semiconductor memory device, has been known as the most highly integrated memory device (memory) and has been put into practical use as the mainstream of LSI. . Various circuit configurations have been devised, and efforts are still being made to improve the degree of integration. For example, a typical example of mask ROMs that have already been patented is Japanese Patent Publication No. 19144/1981, and a general review of semiconductor memory is published by Nikkan Kogyo Shimbun, ``Semiconductor Memory J,'' 1981.
1-2, pages 123-131 (February 1988).

FIG. 3 is a circuit diagram of a main part showing a circuit of a mask ROM which is a highly integrated version of the conventional parallel cell type mask ROM disclosed in the above-mentioned publication. In the figure, 1 is the gate line (also called word line or drive line) of the memory cell, 2 is
is the output line of the memory cell (also called the bit line)
3 is the ground wire (written as Vss), 411"
41, 42', etc. denoted by 12', 4.4, etc. are MOS transistors forming a memory cell.Actually, many more of these lines and memory cells are connected in the same way.
In the circuit example shown in the figure, one grounding wire 3 is used in common for every two output lines 2, thereby reducing the number of grounding wires 3 as much as possible. Such an arrangement is similar to the RO of parallel cells.
It is called M and is the most common configuration.

FIG. 4 is a plan view of the main IC pattern of a mask ROM in which the conventional circuit shown in FIG. 3 is formed in a MOS type integrated circuit device. 5 is a schematic sectional view taken along the line AA shown in FIG. 4, and FIG. 6 is a schematic sectional view taken along the line BB shown in FIG. 4.

4 to 6, the first conductivity type p-type Sl (
On the (silicon) substrate 8, a second conductivity type n+ diffusion layer 6, which constitutes the source/drain region of the MOS transistor 4, is formed.
6a is formed. Also, a thin insulating film (gate oxide film) 9 formed on the channel region on the p-type Sl substrate 8
A gate line 1 made of polycrystalline Sl and sharing the gate electrode is formed in the lateral direction (FIG. 4) via the gate line 1. (5th
In the figure, the direction is perpendicular to the plane of the paper). Further, in the vertical direction, an output line 2 made of an A[(-generally metal) film, and in the horizontal direction, a polycrystalline St
The ground line 3 consisting of the gate line 1 is formed so as not to come into contact with the gate line 1. The output line 2 is connected to the n1 diffusion layer (drain region) 6 via the contact 7, and the ground line 3 is connected to the one diffusion layer (source region) 6a and drawn out. In this way, the gate electrode connected to the gate line 1 and the first diffusion layer 6.6a constitute, for example, a MOS transistor 4.4, each forming a unit memory cell. Note that 5 is an element isolation insulating film (LOCO8
field oxide film).

In this case, as seen in the schematic diagram of the IC pattern plane in FIG. 4, the -diffusion layers 6, 6a are arranged in multiple rows at predetermined intervals in one direction, and the memory cell 4 is formed by the circuit in FIG. A queue is forming.

In the above mask ROM configuration, the memory cells 4, .
Writing of information to . be exposed.

As is well known, reading information is also done using gate lines]
, the output line 2, and the ground line 3 are connected to peripheral circuits (not shown). When a driving pulse is applied to the gate line 1, conduction occurs between the source and drain of the MOS transistor 4.
This is done by utilizing the fact that the output line 2 is at ground potential. That is, the information when the output line 2 is at the ground Tu level is made to correspond to the information "1", for example.
In the part of the cell where the OS transistor does not function, output line 2
Since there is no change in the potential of
If so, it can be distinguished from information “1”, and information “Om”
It can be read as In other words, gate line 1 and output line 2
Depending on the selection, the information "1" or "0°" written in the MOS transistor 4 is read out.

In the conventional example shown in FIG. 4, as shown in the figure, the area per bit, that is, the unit area of the memory cell (S-mXj)
-3,55X4. The area of ROMs such as Ou-14, 2p2 and recent mask ROMs has been significantly reduced, and, for example, IM bit class ROMs have been formed.

[Problems to be Solved by the Invention] Although a considerable degree of integration has already been achieved in the conventional semiconductor memory devices as described above, in the development of ROMs including mask ROMs, there is always a need for higher integration. There is an issue of aiming to achieve this goal.

That is, as office automation equipment, electronic musical instruments, and the like become more multifunctional and of higher quality, the demand for larger capacity ROMs is increasing year by year. Conventionally, high stacking is not limited to mask ROM, for example, EP.
This applies to all storage devices such as ROM and E2PROM, and has been supported by the development of microfabrication technology in IC processes.

However, as we enter the submicron era in recent years, processing technology has become even more difficult, and some even whisper that it has reached its limits. In other words, now that two-dimensional reduction has become difficult,
The next issue to be considered for downsizing is downsizing from a three-dimensional perspective.

This invention was made to solve the above-mentioned problems, and in particular aims to increase the degree of integration through a three-dimensional MOS transistor structure by burying a gate line connected to a gate electrode in a trench. It is something to do.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a plurality of columns of diffusion layers formed at predetermined intervals on the main surface of a semiconductor substrate, and a plurality of rows of trenches formed on the semiconductor substrate between the diffusion layers. A gate electrode is buried through a gate insulating film provided in this trench, and a row wiring using this buried line as a gate line intersects with this gate line and is connected to every other column scattering layer. Column wiring of output lines is formed.

[Function] In the present invention, a plurality of rows of trenches are provided between row diffusion layers arranged in rows and columns on a semiconductor substrate, a gate electrode is buried in the trench, and a row wiring using the gate electrode as a gate line is formed. , and a ground line taken out from the source region of the MOS transistor is formed between the row wirings, so that the MOS transistor is structured three-dimensionally. Therefore, the distance between the contact where the output line connects to the drain region and the end of the trench, that is, the alignment margin, can be formed using the same rule in both the row and column directions, and in particular, it is possible to shorten the distance by this alignment margin.

[Embodiment] FIG. 1 is a schematic plan view of a mask ROM showing an embodiment of the present invention. Figure 2 also shows C shown in Figure 1.
It is a schematic sectional view along the -C line.

Note that the circuit diagram corresponding to the pattern in FIG. 1 is the same as the circuit diagram shown in the conventional column of FIG. Also, D- in Figure 1
The cross-sectional view along line D is B in Fig. 4 shown in the conventional example in Fig. 6.
Since it is the same as the cross-sectional view taken along line -B, illustration is omitted.

1 and 2, the same as the conventional example shown in FIGS. 3 to 6.
Or equivalent parts are indicated using the same symbols.

Since the structure of the ROM according to the present invention is characterized by a structure having a row wiring gate line buried in a trench and a ground line adjacent to the gate line, this part will be mainly explained.

As shown in FIGS. 1 and 2, trenches 11 are formed on a p-type Sl substrate (hereinafter referred to as the substrate) 8 and are continuous in the row direction at predetermined intervals in the column direction. One diffusion layer 6.6a having the same composition is alternately formed on the substrate 8 in the region between these trenches 11, for example, I] dozens of diffusion layers 6.
The drain region and n upper diffusion layer 6a are used as a source region.

On the other hand, in the vertical (column) direction, Ag (
A column line made of a (metal) film is wired to be connected to the n-dozen scattering layer 6 via a contact 7 provided in an interlayer insulating film 10, thereby forming a column line as an output line 2. At this time, an element isolation insulating film 5 is formed in a region formed between adjacent output lines 2 and trenches 11, and an n-dozen scattered layer 6 is formed separately. The n-type diffusion layer 6a is not separated and forms a continuous ground line 3 between adjacent trenches 11 in one phase.

A thin insulating film as a gate oxide film 9 is provided at the bottom and sidewalls of the trench 11.
A gate line 1 is formed as a row wiring, which is buried so as to be insulated by a gate electrode, and shares a gate electrode made of polycrystalline St.

With the above wiring, MOS transistor 4 (4
,...444) It is formed by the bald diffusion layer 6 (drain), the I diffusion layer 6a (source), and the gate shared by the gate line 1, and constitutes a memory cell for one bit.

The gate line 1, output line 2, and ground line 3 are connected to a peripheral circuit (not shown), and the mask R is connected in the same manner as described in the conventional example.
It is designed to operate as an OM.

In the embodiment shown in FIG. 1, the unit area constituting the memory cell is S = 3.25X4. OIJIll-13,0I
JIn”, and S of the conventional column in Fig. 4 = 14.2+
The area has been reduced by approximately 10% compared to JA2.

[Effects of the Invention] As described above, according to the present invention, the gate line that shares the gate electrode of the semiconductor memory device is buried in the trench, and the MOS transistor constituting the memory cell has a three-dimensional structure. In addition, the distance between the contact hole and each edge of the trench can be reduced, and furthermore, the contact hole and column wiring can be formed according to the same rule. Therefore, taking a mask ROM as an example, the unit area of a memory cell can be reduced by about 10%, contributing to higher integration of semiconductor memory devices.

Note that the present invention can be implemented not only in the mask ROM used in the embodiments but also in various ROMs and RAMs. For example, in the case of SRAM, an MO formed using a trench
An S transistor may be used as a transfer gate in a known memory cell.

[Brief explanation of the drawing]

Fig. 1 is a schematic plane pattern diagram of a ROM using MOS transistors showing an embodiment of the present invention, Fig. 2 is a sectional view taken along the line CC in Fig. 1, and Fig. 3 is a main circuit of a conventional parallel cell type ROM. Figure 4 is a plan view of the main IC pattern of a ROM formed by MOS transistors based on the circuit diagram of Figure 3;
The figure is a sectional view taken along the line AA in FIG. 4, and FIG. 6 is a sectional view taken along the line BB in FIG. 4. In the figure, 1 is the gate line (row wiring), 2 is the output line, and 3
is ground line (row wiring), 4 (4,...444) is MOS
transistor (memory cell), 15 is an element isolation insulating film, 6
6a is a diffusion layer (source), and 6a is a diffusion layer (source).
7 is a contact, 8 is a p-type S1 substrate, 9 is a gate oxide film, 10 is an interlayer insulating film, and 11 is a trench.

Claims (1)

[Scope of Claims] A plurality of rows of diffusion layers of a second conductivity type formed at predetermined intervals in one direction on one main surface of a semiconductor substrate of a first conductivity type, and a surface of the semiconductor substrate between the diffusion layers. a ground line consisting of a plurality of rows of second conductivity type diffusion layers formed on the semiconductor substrate; a plurality of trenches formed on the semiconductor substrate of the diffusion layer and the ground line; and a thin insulating film provided in the trenches. A MOS transistor type semiconductor memory device, comprising: a row wiring embedded in the trench via a column wiring; and a column wiring formed to intersect with the row wiring and connected to the diffusion layer.